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+ Thu, 28 Apr 2022 15:58:06 -0700 (PDT)
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+From: Rui Salvaterra <[email protected]>
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+To: [email protected], [email protected],
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+ [email protected]
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+Cc: [email protected], [email protected], [email protected],
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+ Rui Salvaterra <[email protected]>
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+Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology
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+Date: Thu, 28 Apr 2022 23:57:55 +0100
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+ linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
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+
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+On an MT7622 system, the kernel complains of not being able to detect the cache
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+hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
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+order to fix this.
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+
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+Signed-off-by: Rui Salvaterra <[email protected]>
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+---
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+ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
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+ 1 file changed, 7 insertions(+)
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+
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+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+@@ -80,6 +80,7 @@
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+ enable-method = "psci";
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+ clock-frequency = <1300000000>;
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+ cci-control-port = <&cci_control2>;
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++ next-level-cache = <&L2>;
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+ };
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+
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+ cpu1: cpu@1 {
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+@@ -94,6 +95,12 @@
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+ enable-method = "psci";
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+ clock-frequency = <1300000000>;
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+ cci-control-port = <&cci_control2>;
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++ next-level-cache = <&L2>;
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++ };
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++
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++ L2: l2-cache {
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++ compatible = "cache";
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++ cache-level = <2>;
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+ };
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+ };
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+
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Daniel Golle