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+From cd47d86ab09f1f3ec5c86441d4fe95e0cf597c06 Mon Sep 17 00:00:00 2001
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+From: Daniel Golle <[email protected]>
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+Date: Tue, 13 Sep 2022 00:56:24 +0100
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+Subject: [PATCH] thermal/drivers/mediatek: add support for MT7986 and MT7981
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+
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+Add support for V3 generation thermal found in MT7986 and MT7981 SoCs.
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+
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+Signed-off-by: Daniel Golle <[email protected]>
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+---
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+ drivers/thermal/mtk_thermal.c | 202 +++++++++++++++++++++++++++++++++-
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+ 1 file changed, 198 insertions(+), 4 deletions(-)
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+
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+--- a/drivers/thermal/mtk_thermal.c
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++++ b/drivers/thermal/mtk_thermal.c
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+@@ -150,6 +150,21 @@
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+ #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
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+ #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
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+
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++/*
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++ * Layout of the fuses providing the calibration data
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++ * These macros could be used for MT7981 and MT7986.
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++ */
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++#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
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++#define CALIB_BUF0_ADC_OE_V3(x) (((x) >> 10) & 0x3ff)
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++#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
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++#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
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++#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
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++#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
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++#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
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++#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
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++#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
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++#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
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++
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+ enum {
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+ VTS1,
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+ VTS2,
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+@@ -163,6 +178,7 @@ enum {
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+ enum mtk_thermal_version {
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+ MTK_THERMAL_V1 = 1,
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+ MTK_THERMAL_V2,
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++ MTK_THERMAL_V3,
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+ };
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+
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+ /* MT2701 thermal sensors */
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+@@ -245,6 +261,27 @@ enum mtk_thermal_version {
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+ /* The calibration coefficient of sensor */
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+ #define MT8183_CALIBRATION 153
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+
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++/* AUXADC channel 11 is used for the temperature sensors */
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++#define MT7986_TEMP_AUXADC_CHANNEL 11
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++
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++/* The total number of temperature sensors in the MT7986 */
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++#define MT7986_NUM_SENSORS 1
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++
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++/* The number of banks in the MT7986 */
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++#define MT7986_NUM_ZONES 1
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++
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++/* The number of sensing points per bank */
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++#define MT7986_NUM_SENSORS_PER_ZONE 1
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++
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++/* MT7986 thermal sensors */
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++#define MT7986_TS1 0
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++
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++/* The number of controller in the MT7986 */
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++#define MT7986_NUM_CONTROLLER 1
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++
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++/* The calibration coefficient of sensor */
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++#define MT7986_CALIBRATION 165
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++
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+ struct mtk_thermal;
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+
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+ struct thermal_bank_cfg {
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+@@ -279,6 +316,7 @@ struct mtk_thermal {
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+
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+ struct clk *clk_peri_therm;
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+ struct clk *clk_auxadc;
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++ struct clk *clk_adc_32k;
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+ /* lock: for getting and putting banks */
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+ struct mutex lock;
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+
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+@@ -386,6 +424,14 @@ static const int mt7622_mux_values[MT762
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+ static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
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+ static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
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+
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++/* MT7986 thermal sensor data */
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++static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
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++static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
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++static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
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++static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
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++static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
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++static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
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++
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+ /*
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+ * The MT8173 thermal controller has four banks. Each bank can read up to
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+ * four temperature sensors simultaneously. The MT8173 has a total of 5
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+@@ -549,6 +595,30 @@ static const struct mtk_thermal_data mt8
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+ .version = MTK_THERMAL_V1,
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+ };
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+
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++/*
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++ * MT7986 uses AUXADC Channel 11 for raw data access.
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++ */
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++static const struct mtk_thermal_data mt7986_thermal_data = {
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++ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
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++ .num_banks = MT7986_NUM_ZONES,
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++ .num_sensors = MT7986_NUM_SENSORS,
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++ .vts_index = mt7986_vts_index,
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++ .cali_val = MT7986_CALIBRATION,
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++ .num_controller = MT7986_NUM_CONTROLLER,
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++ .controller_offset = mt7986_tc_offset,
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++ .need_switch_bank = true,
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++ .bank_data = {
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++ {
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++ .num_sensors = 1,
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++ .sensors = mt7986_bank_data,
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++ },
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++ },
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++ .msr = mt7986_msr,
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++ .adcpnp = mt7986_adcpnp,
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++ .sensor_mux_values = mt7986_mux_values,
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++ .version = MTK_THERMAL_V3,
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++};
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++
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+ /**
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+ * raw_to_mcelsius - convert a raw ADC value to mcelsius
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+ * @mt: The thermal controller
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+@@ -603,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
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+ return (format_2 - tmp) * 100;
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+ }
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+
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++static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
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++{
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++ s32 tmp;
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++
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++ if (raw == 0)
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++ return 0;
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++
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++ raw &= 0xfff;
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++ tmp = 100000 * 15 / 16 * 10000;
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++ tmp /= 4096 - 512 + mt->adc_ge;
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++ tmp /= 1490;
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++ tmp *= raw - mt->vts[sensno] - 2900;
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++
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++ return mt->degc_cali * 500 - tmp;
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++}
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++
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+ /**
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+ * mtk_thermal_get_bank - get bank
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+ * @bank: The bank
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+@@ -659,9 +745,12 @@ static int mtk_thermal_bank_temperature(
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+ if (mt->conf->version == MTK_THERMAL_V1) {
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+ temp = raw_to_mcelsius_v1(
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+ mt, conf->bank_data[bank->id].sensors[i], raw);
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+- } else {
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++ } else if (mt->conf->version == MTK_THERMAL_V2) {
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+ temp = raw_to_mcelsius_v2(
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+ mt, conf->bank_data[bank->id].sensors[i], raw);
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++ } else {
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++ temp = raw_to_mcelsius_v3(
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++ mt, conf->bank_data[bank->id].sensors[i], raw);
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+ }
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+
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+ /*
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+@@ -887,6 +976,26 @@ static int mtk_thermal_extract_efuse_v2(
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+ return 0;
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+ }
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+
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++static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
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++{
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++ if (!CALIB_BUF1_VALID_V3(buf[1]))
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++ return -EINVAL;
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++
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++ mt->adc_oe = CALIB_BUF0_ADC_OE_V3(buf[0]);
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++ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
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++ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
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++ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
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++ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
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++ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
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++ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
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++ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
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++
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++ if (CALIB_BUF1_ID_V3(buf[1]) == 0)
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++ mt->o_slope = 0;
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++
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++ return 0;
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++}
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++
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+ static int mtk_thermal_get_calibration_data(struct device *dev,
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+ struct mtk_thermal *mt)
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+ {
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+@@ -897,6 +1006,7 @@ static int mtk_thermal_get_calibration_d
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+
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+ /* Start with default values */
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+ mt->adc_ge = 512;
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++ mt->adc_oe = 512;
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+ for (i = 0; i < mt->conf->num_sensors; i++)
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+ mt->vts[i] = 260;
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+ mt->degc_cali = 40;
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+@@ -924,8 +1034,10 @@ static int mtk_thermal_get_calibration_d
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+
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+ if (mt->conf->version == MTK_THERMAL_V1)
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+ ret = mtk_thermal_extract_efuse_v1(mt, buf);
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+- else
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++ else if (mt->conf->version == MTK_THERMAL_V2)
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+ ret = mtk_thermal_extract_efuse_v2(mt, buf);
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++ else
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++ ret = mtk_thermal_extract_efuse_v3(mt, buf);
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+
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+ if (ret) {
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+ dev_info(dev, "Device not calibrated, using default calibration values\n");
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+@@ -956,6 +1068,10 @@ static const struct of_device_id mtk_the
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+ .data = (void *)&mt7622_thermal_data,
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+ },
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+ {
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++ .compatible = "mediatek,mt7986-thermal",
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++ .data = (void *)&mt7986_thermal_data,
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++ },
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++ {
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+ .compatible = "mediatek,mt8183-thermal",
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+ .data = (void *)&mt8183_thermal_data,
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+ }, {
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+@@ -1009,6 +1125,12 @@ static int mtk_thermal_probe(struct plat
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+ if (IS_ERR(mt->clk_auxadc))
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+ return PTR_ERR(mt->clk_auxadc);
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+
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++ if (mt->conf->version == MTK_THERMAL_V3) {
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++ mt->clk_adc_32k = devm_clk_get(&pdev->dev, "adc_32k");
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++ if (IS_ERR(mt->clk_adc_32k))
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++ return PTR_ERR(mt->clk_adc_32k);
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++ }
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++
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(mt->thermal_base))
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+@@ -1058,10 +1180,18 @@ static int mtk_thermal_probe(struct plat
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+ if (ret)
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+ return ret;
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+
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++ if (mt->conf->version == MTK_THERMAL_V3) {
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++ ret = clk_prepare_enable(mt->clk_adc_32k);
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++ if (ret) {
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++ dev_err(&pdev->dev, "Can't enable auxadc 32k clk: %d\n", ret);
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++ return ret;
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++ }
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++ }
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++
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+ ret = clk_prepare_enable(mt->clk_auxadc);
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+ if (ret) {
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+ dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
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+- return ret;
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++ goto err_disable_clk_adc_32k;
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+ }
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+
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+ ret = clk_prepare_enable(mt->clk_peri_therm);
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+@@ -1070,7 +1200,8 @@ static int mtk_thermal_probe(struct plat
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+ goto err_disable_clk_auxadc;
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+ }
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+
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+- if (mt->conf->version == MTK_THERMAL_V2) {
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++ if (mt->conf->version == MTK_THERMAL_V2 ||
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++ mt->conf->version == MTK_THERMAL_V3) {
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+ mtk_thermal_turn_on_buffer(apmixed_base);
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+ mtk_thermal_release_periodic_ts(mt, auxadc_base);
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+ }
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+@@ -1099,6 +1230,9 @@ err_disable_clk_peri_therm:
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+ clk_disable_unprepare(mt->clk_peri_therm);
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+ err_disable_clk_auxadc:
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+ clk_disable_unprepare(mt->clk_auxadc);
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++err_disable_clk_adc_32k:
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++ if (mt->conf->version == MTK_THERMAL_V3)
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++ clk_disable_unprepare(mt->clk_adc_32k);
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+
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+ return ret;
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+ }
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+@@ -1110,6 +1244,9 @@ static int mtk_thermal_remove(struct pla
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+ clk_disable_unprepare(mt->clk_peri_therm);
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+ clk_disable_unprepare(mt->clk_auxadc);
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+
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++ if (mt->conf->version == MTK_THERMAL_V3)
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++ clk_disable_unprepare(mt->clk_adc_32k);
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++
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+ return 0;
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+ }
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+
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Daniel Golle