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@@ -7,21 +7,22 @@ RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
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Signed-off-by: John Crispin <[email protected]>
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---
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- drivers/gpio/Kconfig | 6 +
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+ drivers/gpio/Kconfig | 7 +
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drivers/gpio/Makefile | 1 +
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- drivers/gpio/gpio-ralink.c | 328 +++++++++++++++++++++++++++++++++++++
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- 3 files changed, 335 insertions(+)
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+ drivers/gpio/gpio-ralink.c | 273 +++++++++++++++++++++++++++++++++++++
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+ 3 files changed, 281 insertions(+)
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create mode 100644 drivers/gpio/gpio-ralink.c
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--- a/drivers/gpio/Kconfig
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+++ b/drivers/gpio/Kconfig
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-@@ -594,6 +594,12 @@ config GPIO_SNPS_CREG
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+@@ -594,6 +594,13 @@ config GPIO_SNPS_CREG
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where only several fields in register belong to GPIO lines and
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each GPIO line owns a field with different length and on/off value.
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+config GPIO_RALINK
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+ bool "Ralink GPIO Support"
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+ depends on RALINK
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++ select GPIO_GENERIC
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+ help
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+ Say yes here to support the Ralink SoC GPIO device
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+
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@@ -40,7 +41,7 @@ Signed-off-by: John Crispin <[email protected]>
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obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
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--- /dev/null
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+++ b/drivers/gpio/gpio-ralink.c
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-@@ -0,0 +1,328 @@
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+@@ -0,0 +1,273 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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@@ -110,52 +111,6 @@ Signed-off-by: John Crispin <[email protected]>
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+ return ioread32(rg->membase + rg->regs[reg]);
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+}
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+
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-+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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-+{
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-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
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-+
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-+ rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
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-+}
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-+
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-+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
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-+{
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-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
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-+
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-+ return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
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-+}
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-+
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-+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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-+{
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-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
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-+ unsigned long flags;
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-+ u32 t;
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-+
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-+ spin_lock_irqsave(&rg->lock, flags);
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-+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
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-+ t &= ~BIT(offset);
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-+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
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-+ spin_unlock_irqrestore(&rg->lock, flags);
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-+
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-+ return 0;
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-+}
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-+
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-+static int ralink_gpio_direction_output(struct gpio_chip *chip,
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-+ unsigned offset, int value)
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-+{
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-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
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-+ unsigned long flags;
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-+ u32 t;
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-+
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-+ spin_lock_irqsave(&rg->lock, flags);
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-+ ralink_gpio_set(chip, offset, value);
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-+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
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-+ t |= BIT(offset);
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-+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
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-+ spin_unlock_irqrestore(&rg->lock, flags);
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-+
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-+ return 0;
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-+}
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-+
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+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
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+{
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+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
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@@ -298,12 +253,12 @@ Signed-off-by: John Crispin <[email protected]>
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+
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+static int ralink_gpio_probe(struct platform_device *pdev)
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+{
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-+ struct device_node *np = pdev->dev.of_node;
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++ struct device *dev = &pdev->dev;
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++ struct device_node *np = dev->of_node;
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+ struct ralink_gpio_chip *rg;
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-+ const __be32 *ngpio;
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++ int ret;
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+
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-+ rg = devm_kzalloc(&pdev->dev,
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-+ sizeof(struct ralink_gpio_chip), GFP_KERNEL);
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++ rg = devm_kzalloc(dev, sizeof(struct ralink_gpio_chip), GFP_KERNEL);
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+ if (!rg)
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+ return -ENOMEM;
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+
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@@ -313,27 +268,20 @@ Signed-off-by: John Crispin <[email protected]>
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+
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+ if (of_property_read_u8_array(np, "ralink,register-map",
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+ rg->regs, GPIO_REG_MAX)) {
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-+ dev_err(&pdev->dev, "failed to read register definition\n");
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-+ return -EINVAL;
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-+ }
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-+
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-+ ngpio = of_get_property(np, "ngpios", NULL);
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-+ if (!ngpio) {
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-+ dev_err(&pdev->dev, "failed to read number of pins\n");
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++ dev_err(dev, "failed to read register definition\n");
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+ return -EINVAL;
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+ }
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+
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+ spin_lock_init(&rg->lock);
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+
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-+ rg->chip.base = -1;
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-+ rg->chip.parent = &pdev->dev;
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-+ rg->chip.label = dev_name(&pdev->dev);
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-+ rg->chip.fwnode = of_node_to_fwnode(np);
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-+ rg->chip.ngpio = be32_to_cpu(*ngpio);
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-+ rg->chip.direction_input = ralink_gpio_direction_input;
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-+ rg->chip.direction_output = ralink_gpio_direction_output;
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-+ rg->chip.get = ralink_gpio_get;
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-+ rg->chip.set = ralink_gpio_set;
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++ ret = bgpio_init(&rg->chip, dev, 4,
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++ rg->membase + rg->regs[GPIO_REG_DATA],
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++ rg->membase + rg->regs[GPIO_REG_SET],
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++ rg->membase + rg->regs[GPIO_REG_RESET],
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++ rg->membase + rg->regs[GPIO_REG_DIR],
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++ NULL, 0);
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++ if (ret)
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++ return dev_err_probe(dev, ret, "bgpio_init() failed\n");
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+ rg->chip.request = gpiochip_generic_request;
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+ rg->chip.to_irq = ralink_gpio_to_irq;
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+ rg->chip.free = gpiochip_generic_free;
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@@ -341,11 +289,9 @@ Signed-off-by: John Crispin <[email protected]>
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+ /* set polarity to low for all lines */
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+ rt_gpio_w32(rg, GPIO_REG_POL, 0);
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+
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-+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
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-+
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+ ralink_gpio_irq_init(np, rg);
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+
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-+ return gpiochip_add(&rg->chip);
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++ return devm_gpiochip_add_data(dev, &rg->chip, rg);
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+}
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+
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+static const struct of_device_id ralink_gpio_match[] = {
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Shiji Yang