uart_clk on Rt3352F is always 40MHz

Currently, sys_clk/10 is used which is just wrong.
cpu_clk/10 would work for systems with 400MHz CPU clock.

Signed-off-by: Daniel Golle <[email protected]>

SVN-Revision: 32812

target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c

@@ -60,7 +60,7 @@ void __init rt305x_clocks_init(void)
 			break;
 		}
 		rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
-		rt305x_uart_clk.rate = rt305x_sys_clk.rate / 10;
+		rt305x_uart_clk.rate = 40000000;
 		rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
 	} else {
 		BUG();