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@@ -1,19 +1,43 @@
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-From cc2cda651fcbc498bf513a6b802dca19944bcb37 Mon Sep 17 00:00:00 2001
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+From cf067bf8bb993d6cfdc42d750ae241c43f88403f Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <[email protected]>
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Date: Mon, 12 May 2014 11:55:20 +0200
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-Subject: [PATCH 13/17] pcie2-bcma: add new PCIe2 driver for bcma
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+Subject: [PATCH 1/2] PCI: BCM5301X: add PCIe2 driver for BCM5301X SoCs
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This driver supports the PCIe controller found on the BCM4708 and
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similar SoCs. The controller itself is automatically detected by bcma.
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+This controller is found on SoCs usually used in SOHO routers to
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+connect the wifi cards to the SoC. All the of the BCM5301X SoCs I know
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+of have 2 or 3 of these controllers in the SoC.
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+
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+I had to use PCI domains otherwise the pci_create_root_bus() function
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+in drivers/pci/probe.c would fail for the second controller being
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+registered because pci_find_bus() would find the same PCIe bus again
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+and assume it is already registered, which ends up in a kernel panic in
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+pcibios_init_hw() in arch/arm/kernel/bios32.c
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+
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+The ARM PCI code assumes that every controller has an I/O space and
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+adds a dummy area if the driver does not specify one. This will work
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+for the first controller, but when we register the second one this will
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+result in an error. To prevent this problem we add an empty I/O space.
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+
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+Currently I have problems with probing the devices on the bus, because
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+pci_bus_add_devices() is called too early in pci_scan_root_bus() in
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+drivers/pci/probe.c, before pci_bus_assign_resources() was called in
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+pci_common_init_dev() in arch/arm/kernel/bios32.c. When the devices are
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+added too early they do not have any resources and adding fails. I have
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+to remove the call to pci_bus_add_devices() in pci_scan_root_bus() to
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+make registration work, calling pci_bus_add_devices() later again does
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+not fix this problem.
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+
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Signed-off-by: Hauke Mehrtens <[email protected]>
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---
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- arch/arm/mach-bcm/Kconfig | 2 +
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- drivers/pci/host/Kconfig | 7 +
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- drivers/pci/host/Makefile | 1 +
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- drivers/pci/host/pcie2-bcma.c | 591 ++++++++++++++++++++++++++++++++++++++++++
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- 4 files changed, 601 insertions(+)
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- create mode 100644 drivers/pci/host/pcie2-bcma.c
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+ arch/arm/mach-bcm/Kconfig | 1 +
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+ drivers/pci/host/Kconfig | 7 +
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+ drivers/pci/host/Makefile | 1 +
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+ drivers/pci/host/pci-host-bcm5301x.c | 428 +++++++++++++++++++++++++++++++++++
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+ 4 files changed, 437 insertions(+)
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+ create mode 100644 drivers/pci/host/pci-host-bcm5301x.c
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--- a/arch/arm/mach-bcm/Kconfig
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+++ b/arch/arm/mach-bcm/Kconfig
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@@ -31,12 +55,12 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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There are 5 internal PCIe ports available. Each port is GEN3 capable
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and have varied lanes from x1 to x8.
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-+config PCI_BCMA
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-+ bool "BCMA PCIe2 host controller"
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-+ depends on BCMA && OF
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++config PCI_BCM5301X
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++ bool "BCM5301X PCIe2 host controller"
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++ depends on BCMA && OF && ARM && PCI_DOMAINS
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+ help
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-+ Say Y here if you want to support a simple generic PCI host
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-+ controller, such as the one emulated by kvmtool.
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++ Say Y here if you want to support the PCIe host controller found
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++ on Broadcom BCM5301X and BCM470X (Northstar) SoCs.
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+
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endmenu
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--- a/drivers/pci/host/Makefile
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@@ -45,10 +69,10 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
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obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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-+obj-$(CONFIG_PCI_BCMA) += pcie2-bcma.o
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++obj-$(CONFIG_PCI_BCM5301X) += pci-host-bcm5301x.o
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--- /dev/null
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-+++ b/drivers/pci/host/pcie2-bcma.c
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-@@ -0,0 +1,619 @@
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++++ b/drivers/pci/host/pci-host-bcm5301x.c
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+@@ -0,0 +1,428 @@
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+/*
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+ * Northstar PCI-Express driver
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+ * Only supports Root-Complex (RC) mode
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@@ -58,63 +82,25 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+ *
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+ * Only MEM access is supported, PAX does not support IO.
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+ *
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-+ * TODO:
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-+ * MSI interrupts,
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-+ * DRAM > 128 MBytes (e.g. DMA zones)
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++ * Copyright 2012-2014, Broadcom Corporation
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++ * Copyright 2014, Hauke Mehrtens <[email protected]>
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++ *
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++ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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-+#include <linux/bug.h>
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+#include <linux/delay.h>
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+#include <linux/pci.h>
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+#include <linux/io.h>
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+#include <linux/ioport.h>
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+#include <linux/interrupt.h>
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+#include <linux/bcma/bcma.h>
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-+
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-+#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
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-+
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-+/*
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-+ * Register offset definitions
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-+ */
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-+#define SOC_PCIE_CONTROL 0x000 /* a.k.a. CLK_CONTROL reg */
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-+#define SOC_PCIE_PM_STATUS 0x008
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-+#define SOC_PCIE_PM_CONTROL 0x00c /* in EP mode only ! */
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-+
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-+#define SOC_PCIE_EXT_CFG_ADDR 0x120
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-+#define SOC_PCIE_EXT_CFG_DATA 0x124
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-+#define SOC_PCIE_CFG_ADDR 0x1f8
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-+#define SOC_PCIE_CFG_DATA 0x1fc
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-+
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-+#define SOC_PCIE_SYS_RC_INTX_EN 0x330
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-+#define SOC_PCIE_SYS_RC_INTX_CSR 0x334
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-+#define SOC_PCIE_SYS_HOST_INTR_EN 0x344
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-+#define SOC_PCIE_SYS_HOST_INTR_CSR 0x348
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++#include <linux/bcma/bcma_driver_pcie2.h>
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++#include <linux/of_irq.h>
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+
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+#define SOC_PCIE_HDR_OFF 0x400 /* 256 bytes per function */
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+
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-+/* 32-bit 4KB in-bound mapping windows for Function 0..3, n=0..7 */
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-+#define SOC_PCIE_SYS_IMAP0(f, n) (0xc00 + ((f) << 9)((n) << 2))
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-+/* 64-bit in-bound mapping windows for func 0..3 */
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-+#define SOC_PCIE_SYS_IMAP1(f) (0xc80 + ((f) << 3))
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-+#define SOC_PCIE_SYS_IMAP2(f) (0xcc0 + ((f) << 3))
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-+/* 64-bit in-bound address range n=0..2 */
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-+#define SOC_PCIE_SYS_IARR(n) (0xd00 + ((n) << 3))
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-+/* 64-bit out-bound address filter n=0..2 */
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-+#define SOC_PCIE_SYS_OARR(n) (0xd20 + ((n) << 3))
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-+/* 64-bit out-bound mapping windows n=0..2 */
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-+#define SOC_PCIE_SYS_OMAP(n) (0xd40 + ((n) << 3))
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-+
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-+#define BCM4360_D11AC_ID 0x43a0
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-+#define BCM4360_D11AC2G_ID 0x43a1
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-+#define BCM4360_D11AC5G_ID 0x43a2
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-+#define BCM4352_D11AC_ID 0x43b1 /* 4352 802.11ac dualband device */
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-+#define BCM4352_D11AC2G_ID 0x43b2 /* 4352 802.11ac 2.4G device */
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-+#define BCM4352_D11AC5G_ID 0x43b3 /* 4352 802.11ac 5G device */
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-+
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-+static struct pci_ops bcma_pcie2_ops;
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-+
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+static int bcma_pcie2_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
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+{
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+ struct pci_sys_data *sys = pdev->sysdata;
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@@ -133,16 +119,17 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+ if (busno == 0) {
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+ if (slot >= 1)
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+ return 0;
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-+ bcma_write32(bdev, SOC_PCIE_EXT_CFG_ADDR, where & 0xffc);
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-+ return SOC_PCIE_EXT_CFG_DATA;
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++ bcma_write32(bdev, BCMA_CORE_PCIE2_CONFIGINDADDR,
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++ where & 0xffc);
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++ return BCMA_CORE_PCIE2_CONFIGINDDATA;
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+ }
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+ if (fn > 1)
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+ return 0;
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+ addr_reg = (busno & 0xff) << 20 | (slot << 15) | (fn << 12) |
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+ (where & 0xffc) | (1 & 0x3);
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+
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-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, addr_reg);
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-+ return SOC_PCIE_CFG_DATA;
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++ bcma_write32(bdev, BCMA_CORE_PCIE2_CFG_ADDR, addr_reg);
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++ return BCMA_CORE_PCIE2_CFG_DATA;
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+}
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+
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+static u32 bcma_pcie2_read_config(struct bcma_device *bdev, int busno,
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@@ -160,20 +147,6 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+
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+ data_reg = bcma_read32(bdev, base);
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+
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-+ /* NS: CLASS field is R/O, and set to wrong 0x200 value */
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-+ if (busno == 0 && devfn == 0) {
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-+ /*
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-+ * RC's class is 0x0280, but Linux PCI driver needs 0x604
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-+ * for a PCIe bridge. So we must fixup the class code
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-+ * to 0x604 here.
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-+ */
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-+ if ((where & 0xffc) == PCI_CLASS_REVISION) {
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-+ data_reg &= 0xff;
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-+ data_reg |= 0x604 << 16;
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-+ }
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-+ }
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-+ /* HEADER_TYPE=00 indicates the port in EP mode */
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-+
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+ if (size == 4)
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+ return data_reg;
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+
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@@ -208,42 +181,6 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+ bcma_write32(bdev, base, data_reg);
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+}
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+
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-+static u8 bcma_pcie2_read_config8(struct bcma_device *bdev, int busno,
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-+ unsigned int devfn, int where)
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-+{
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-+ return bcma_pcie2_read_config(bdev, busno, devfn, where, 1);
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-+}
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-+
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-+static u16 bcma_pcie2_read_config16(struct bcma_device *bdev, int busno,
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-+ unsigned int devfn, int where)
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-+{
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-+ return bcma_pcie2_read_config(bdev, busno, devfn, where, 2);
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-+}
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-+
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-+static u32 bcma_pcie2_read_config32(struct bcma_device *bdev, int busno,
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-+ unsigned int devfn, int where)
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-+{
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-+ return bcma_pcie2_read_config(bdev, busno, devfn, where, 4);
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-+}
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-+
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-+static void bcma_pcie2_write_config8(struct bcma_device *bdev, int busno,
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-+ unsigned int devfn, int where, u8 val)
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-+{
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-+ return bcma_pcie2_write_config(bdev, busno, devfn, where, 1, val);
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-+}
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-+
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-+static void bcma_pcie2_write_config16(struct bcma_device *bdev, int busno,
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-+ unsigned int devfn, int where, u16 val)
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-+{
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-+ return bcma_pcie2_write_config(bdev, busno, devfn, where, 2, val);
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-+}
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-+
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-+static void bcma_pcie2_write_config32(struct bcma_device *bdev, int busno,
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-+ unsigned int devfn, int where, u32 val)
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-+{
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-+ return bcma_pcie2_write_config(bdev, busno, devfn, where, 4, val);
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-+}
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-+
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+static int bcma_pcie2_read_config_pci(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 *val)
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+{
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@@ -267,31 +204,31 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+}
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+
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+/*
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++ * Methods for accessing configuration registers
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++ */
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++static struct pci_ops bcma_pcie2_ops = {
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++ .read = bcma_pcie2_read_config_pci,
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++ .write = bcma_pcie2_write_config_pci,
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++};
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++
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++/* NS: CLASS field is R/O, and set to wrong 0x200 value */
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++static void bcma_pcie2_fixup_class(struct pci_dev *dev)
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++{
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++ dev->class = PCI_CLASS_BRIDGE_PCI << 8;
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++}
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++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x8011, bcma_pcie2_fixup_class);
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++
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++/*
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+ * Check link status, return 0 if link is up in RC mode,
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+ * otherwise return non-zero
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+ */
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-+static int bcma_pcie2_check_link(struct bcma_device *bdev,
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-+ struct pci_sys_data *sys, u32 allow_gen2)
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++static int bcma_pcie2_check_link(struct bcma_device *bdev, bool allow_gen2)
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+{
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+ u32 devfn = 0;
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+ u32 tmp32;
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-+ u16 tmp16;
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+ u8 tmp8;
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-+ int pos;
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-+ bool link = false;
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-+ /*
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-+ * Setup callback (bcma_pcie2_setup) is called in pcibios_init_hw before
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-+ * creating bus root, so we don't have it here yet. On the other hand
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-+ * we really want to use pci_bus_find_capability helper to check NLW.
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-+ * Let's fake simple pci_bus just to query for capabilities.
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-+ */
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-+ struct pci_bus bus = {
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-+ .number = 0,
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-+ .ops = &bcma_pcie2_ops,
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-+ .sysdata = sys,
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-+ };
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+
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-+ tmp32 = bcma_pcie2_read_config32(bdev, 0, devfn, 0xdc);
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++ tmp32 = bcma_pcie2_read_config(bdev, 0, devfn, 0xdc, 4);
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+ tmp32 &= ~0xf;
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+ if (allow_gen2)
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+ tmp32 |= 2;
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@@ -299,28 +236,17 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+ /* force PCIE GEN1 */
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+ tmp32 |= 1;
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+ }
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-+ bcma_pcie2_write_config32(bdev, 0, devfn, 0xdc, tmp32);
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++ bcma_pcie2_write_config(bdev, 0, devfn, 0xdc, 4, tmp32);
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+
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+ /* See if the port is in EP mode, indicated by header type 00 */
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-+ tmp8 = bcma_pcie2_read_config8(bdev, 0, devfn, PCI_HEADER_TYPE);
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++ tmp8 = bcma_pcie2_read_config(bdev, 0, devfn, PCI_HEADER_TYPE, 1);
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+ if (tmp8 != PCI_HEADER_TYPE_BRIDGE) {
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+ dev_info(&bdev->dev, "Port %d in End-Point mode - ignored\n",
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+ bdev->core_unit);
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+ return -ENODEV;
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+ }
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+
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-+ /* NS PAX only changes NLW field when card is present */
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-+ pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
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-+ if (pos) {
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-+ u8 nlw;
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-+
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-+ pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_LNKSTA,
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-+ &tmp16);
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-+ nlw = (tmp16 & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
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-+ link = (tmp16 & PCI_EXP_LNKSTA_DLLLA) || nlw != 0;
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-+ }
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-+
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-+ return link ? 0 : -ENODEV;
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++ return 0;
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+}
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+
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+/*
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@@ -328,67 +254,52 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+ */
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+static void bcma_pcie2_hw_init(struct bcma_device *bdev)
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+{
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-+ u32 devfn = 0;
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+ u32 tmp32;
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+ u16 tmp16;
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+
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+ /* Change MPS and MRRS to 512 */
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-+ tmp16 = bcma_pcie2_read_config16(bdev, 0, devfn, 0x4d4);
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++ tmp16 = bcma_pcie2_read_config(bdev, 0, 0, 0x4d4, 2);
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+ tmp16 &= ~7;
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+ tmp16 |= 2;
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-+ bcma_pcie2_write_config16(bdev, 0, devfn, 0x4d4, tmp16);
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++ bcma_pcie2_write_config(bdev, 0, 0, 0x4d4, 2, tmp16);
|
|
|
+
|
|
|
-+ tmp32 = bcma_pcie2_read_config32(bdev, 0, devfn, 0xb4);
|
|
|
++ tmp32 = bcma_pcie2_read_config(bdev, 0, 0, 0xb4, 4);
|
|
|
+ tmp32 &= ~((7 << 12) | (7 << 5));
|
|
|
+ tmp32 |= (2 << 12) | (2 << 5);
|
|
|
-+ bcma_pcie2_write_config32(bdev, 0, devfn, 0xb4, tmp32);
|
|
|
-+
|
|
|
-+ /* Turn-on Root-Complex (RC) mode, from reset defailt of EP */
|
|
|
++ bcma_pcie2_write_config(bdev, 0, 0, 0xb4, 4, tmp32);
|
|
|
+
|
|
|
-+ /* The mode is set by straps, can be overwritten via DMU
|
|
|
-+ register <cru_straps_control> bit 5, "1" means RC
|
|
|
++ /*
|
|
|
++ * Turn-on Root-Complex (RC) mode, from reset default of EP
|
|
|
++ * The mode is set by straps, can be overwritten via DMU
|
|
|
++ * register <cru_straps_control> bit 5, "1" means RC
|
|
|
+ */
|
|
|
+
|
|
|
+ /* Send a downstream reset */
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_CONTROL, 0x3);
|
|
|
-+ udelay(250);
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_CONTROL, 0x1);
|
|
|
-+ mdelay(250);
|
|
|
++ bcma_write32(bdev, BCMA_CORE_PCIE2_CLK_CONTROL,
|
|
|
++ PCIE2_CLKC_RST_OE | PCIE2_CLKC_RST);
|
|
|
++ usleep_range(250, 400);
|
|
|
++ bcma_write32(bdev, BCMA_CORE_PCIE2_CLK_CONTROL, PCIE2_CLKC_RST_OE);
|
|
|
++ msleep(250);
|
|
|
+
|
|
|
+ /* TBD: take care of PM, check we're on */
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * Setup the address translation
|
|
|
++ *
|
|
|
++ * NOTE: All PCI-to-CPU address mapping are 1:1 for simplicity
|
|
|
+ */
|
|
|
-+static void bcma_pcie2_map_init(struct bcma_device *bdev)
|
|
|
++static int bcma_pcie2_map_init(struct bcma_device *bdev, u32 addr)
|
|
|
+{
|
|
|
-+ unsigned size, i;
|
|
|
-+ u32 addr;
|
|
|
++ /* 64MB alignment */
|
|
|
++ if (!addr || (addr & (SZ_64M - 1)))
|
|
|
++ return -EINVAL;
|
|
|
+
|
|
|
-+ /*
|
|
|
-+ * NOTE:
|
|
|
-+ * All PCI-to-CPU address mapping are 1:1 for simplicity
|
|
|
-+ */
|
|
|
++ bcma_write32(bdev, BCMA_CORE_PCIE2_OMAP0_LOWER, addr);
|
|
|
++ bcma_write32(bdev, BCMA_CORE_PCIE2_OARR0, addr | 0x01);
|
|
|
+
|
|
|
-+ /* Outbound address translation setup */
|
|
|
-+ size = SZ_128M;
|
|
|
-+ addr = bdev->addr_s[0];
|
|
|
-+ BUG_ON(!addr);
|
|
|
-+ BUG_ON(addr & ((1 << 25) - 1)); /* 64MB alignment */
|
|
|
-+
|
|
|
-+ for (i = 0; i < 3; i++) {
|
|
|
-+ const unsigned win_size = SZ_64M;
|
|
|
-+ /* 64-bit LE regs, write low word, high is 0 at reset */
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_SYS_OMAP(i), addr);
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_SYS_OARR(i), addr|0x1);
|
|
|
-+ addr += win_size;
|
|
|
-+ if (size >= win_size)
|
|
|
-+ size -= win_size;
|
|
|
-+ if (size == 0)
|
|
|
-+ break;
|
|
|
-+ }
|
|
|
-+ WARN_ON(size > 0);
|
|
|
++ bcma_write32(bdev, BCMA_CORE_PCIE2_OMAP1_LOWER, addr + SZ_64M);
|
|
|
++ bcma_write32(bdev, BCMA_CORE_PCIE2_OARR1, (addr + SZ_64M) | 0x01);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Inbound address translation setup
|
|
|
@@ -398,107 +309,46 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
|
|
|
+ * otherwise DMA bouncing mechanism may be required.
|
|
|
+ * Also consider DMA mask to limit DMA physical address
|
|
|
+ */
|
|
|
-+ size = SZ_128M;
|
|
|
-+ addr = PHYS_OFFSET;
|
|
|
-+
|
|
|
-+ size >>= 20; /* In MB */
|
|
|
-+ size &= 0xff; /* Size is an 8-bit field */
|
|
|
-+
|
|
|
-+ WARN_ON(size == 0);
|
|
|
+ /* 64-bit LE regs, write low word, high is 0 at reset */
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_SYS_IMAP1(0), addr | 0x1);
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_SYS_IARR(1), addr | size);
|
|
|
-+
|
|
|
-+#ifdef CONFIG_SPARSEMEM
|
|
|
-+ addr = PHYS_OFFSET2;
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_SYS_IMAP2(0), addr | 0x1);
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_SYS_IARR(2), addr | size);
|
|
|
-+#endif
|
|
|
++ bcma_write32(bdev, BCMA_CORE_PCIE2_FUNC0_IMAP1, PHYS_OFFSET | 0x1);
|
|
|
++ bcma_write32(bdev, BCMA_CORE_PCIE2_IARR1_LOWER,
|
|
|
++ PHYS_OFFSET | ((SZ_128M >> 20) & 0xff));
|
|
|
++ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * Setup PCIE Host bridge
|
|
|
+ */
|
|
|
-+static void bcma_pcie2_bridge_init(struct bcma_device *bdev)
|
|
|
++static int bcma_pcie2_bridge_init(struct bcma_device *bdev, u32 addr, u32 size)
|
|
|
+{
|
|
|
-+ u32 devfn = 0;
|
|
|
-+ u8 tmp8;
|
|
|
-+ u16 tmp16;
|
|
|
++ bcma_pcie2_write_config(bdev, 0, 0, PCI_PRIMARY_BUS, 1, 0);
|
|
|
++ bcma_pcie2_write_config(bdev, 0, 0, PCI_SECONDARY_BUS, 1, 1);
|
|
|
++ bcma_pcie2_write_config(bdev, 0, 0, PCI_SUBORDINATE_BUS, 1, 4);
|
|
|
+
|
|
|
-+ bcma_pcie2_write_config8(bdev, 0, devfn, PCI_PRIMARY_BUS, 0);
|
|
|
-+ bcma_pcie2_write_config8(bdev, 0, devfn, PCI_SECONDARY_BUS, 1);
|
|
|
-+ bcma_pcie2_write_config8(bdev, 0, devfn, PCI_SUBORDINATE_BUS, 4);
|
|
|
-+
|
|
|
-+ tmp8 = bcma_pcie2_read_config8(bdev, 0, devfn, PCI_PRIMARY_BUS);
|
|
|
-+ tmp8 = bcma_pcie2_read_config8(bdev, 0, devfn, PCI_SECONDARY_BUS);
|
|
|
-+ tmp8 = bcma_pcie2_read_config8(bdev, 0, devfn, PCI_SUBORDINATE_BUS);
|
|
|
++ bcma_pcie2_read_config(bdev, 0, 0, PCI_PRIMARY_BUS, 1);
|
|
|
++ bcma_pcie2_read_config(bdev, 0, 0, PCI_SECONDARY_BUS, 1);
|
|
|
++ bcma_pcie2_read_config(bdev, 0, 0, PCI_SUBORDINATE_BUS, 1);
|
|
|
+
|
|
|
+ /* MEM_BASE, MEM_LIM require 1MB alignment */
|
|
|
-+ BUG_ON((bdev->addr_s[0] >> 16) & 0xf);
|
|
|
-+ bcma_pcie2_write_config16(bdev, 0, devfn, PCI_MEMORY_BASE,
|
|
|
-+ bdev->addr_s[0] >> 16);
|
|
|
-+ BUG_ON(((bdev->addr_s[0] + SZ_128M) >> 16) & 0xf);
|
|
|
-+ bcma_pcie2_write_config16(bdev, 0, devfn, PCI_MEMORY_LIMIT,
|
|
|
-+ (bdev->addr_s[0] + SZ_128M) >> 16);
|
|
|
++ if (((addr >> 16) & 0xf) || (((addr + size) >> 16) & 0xf))
|
|
|
++ return -EINVAL;
|
|
|
++
|
|
|
++ bcma_pcie2_write_config(bdev, 0, 0, PCI_MEMORY_BASE, 2, addr >> 16);
|
|
|
++ bcma_pcie2_write_config(bdev, 0, 0, PCI_MEMORY_LIMIT, 2,
|
|
|
++ (addr + size) >> 16);
|
|
|
+
|
|
|
+ /* These registers are not supported on the NS */
|
|
|
-+ bcma_pcie2_write_config16(bdev, 0, devfn, PCI_IO_BASE_UPPER16, 0);
|
|
|
-+ bcma_pcie2_write_config16(bdev, 0, devfn, PCI_IO_LIMIT_UPPER16, 0);
|
|
|
++ bcma_pcie2_write_config(bdev, 0, 0, PCI_IO_BASE_UPPER16, 2, 0);
|
|
|
++ bcma_pcie2_write_config(bdev, 0, 0, PCI_IO_LIMIT_UPPER16, 2, 0);
|
|
|
+
|
|
|
+ /* Force class to that of a Bridge */
|
|
|
-+ bcma_pcie2_write_config16(bdev, 0, devfn, PCI_CLASS_DEVICE,
|
|
|
-+ PCI_CLASS_BRIDGE_PCI);
|
|
|
-+
|
|
|
-+ tmp16 = bcma_pcie2_read_config16(bdev, 0, devfn, PCI_CLASS_DEVICE);
|
|
|
-+ tmp16 = bcma_pcie2_read_config16(bdev, 0, devfn, PCI_MEMORY_BASE);
|
|
|
-+ tmp16 = bcma_pcie2_read_config16(bdev, 0, devfn, PCI_MEMORY_LIMIT);
|
|
|
-+}
|
|
|
++ bcma_pcie2_write_config(bdev, 0, 0, PCI_CLASS_DEVICE, 2,
|
|
|
++ PCI_CLASS_BRIDGE_PCI);
|
|
|
+
|
|
|
-+static int bcma_pcie2_allow_gen2_rc(struct bcma_device *bdev)
|
|
|
-+{
|
|
|
-+ u32 vendorid, devid, chipid, chiprev;
|
|
|
-+ u32 val, bar;
|
|
|
-+ void __iomem *base;
|
|
|
-+ int allow = 1;
|
|
|
-+
|
|
|
-+ /* Read PCI vendor/device ID's */
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x0);
|
|
|
-+ val = bcma_read32(bdev, SOC_PCIE_CFG_DATA);
|
|
|
-+ vendorid = val & 0xffff;
|
|
|
-+ devid = val >> 16;
|
|
|
-+ if (vendorid == PCI_VENDOR_ID_BROADCOM &&
|
|
|
-+ (devid == BCMA_CHIP_ID_BCM4360 || devid == BCM4360_D11AC_ID ||
|
|
|
-+ devid == BCM4360_D11AC2G_ID || devid == BCM4360_D11AC5G_ID ||
|
|
|
-+ devid == BCM4352_D11AC_ID || devid == BCM4352_D11AC2G_ID ||
|
|
|
-+ devid == BCM4352_D11AC5G_ID)) {
|
|
|
-+ /* Config BAR0 */
|
|
|
-+ bar = bdev->addr_s[0];
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x10);
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_CFG_DATA, bar);
|
|
|
-+ /* Config BAR0 window to access chipc */
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x80);
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_CFG_DATA, SI_ENUM_BASE);
|
|
|
-+
|
|
|
-+ /* Enable memory resource */
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_CFG_ADDR, 0x4);
|
|
|
-+ val = bcma_read32(bdev, SOC_PCIE_CFG_DATA);
|
|
|
-+ val |= PCI_COMMAND_MEMORY;
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_CFG_DATA, val);
|
|
|
-+ /* Enable memory and bus master */
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_HDR_OFF + 4, 0x6);
|
|
|
-+
|
|
|
-+ /* Read CHIP ID */
|
|
|
-+ base = ioremap(bar, 0x1000);
|
|
|
-+ val = __raw_readl(base);
|
|
|
-+ iounmap(base);
|
|
|
-+ chipid = val & 0xffff;
|
|
|
-+ chiprev = (val >> 16) & 0xf;
|
|
|
-+ if ((chipid == BCMA_CHIP_ID_BCM4360 ||
|
|
|
-+ chipid == BCMA_CHIP_ID_BCM43460 ||
|
|
|
-+ chipid == BCMA_CHIP_ID_BCM4352) && (chiprev < 3))
|
|
|
-+ allow = 0;
|
|
|
-+ }
|
|
|
-+ return allow;
|
|
|
++ bcma_pcie2_read_config(bdev, 0, 0, PCI_CLASS_DEVICE, 2);
|
|
|
++ bcma_pcie2_read_config(bdev, 0, 0, PCI_MEMORY_BASE, 2);
|
|
|
++ bcma_pcie2_read_config(bdev, 0, 0, PCI_MEMORY_LIMIT, 2);
|
|
|
++ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void bcma_pcie2_3rd_init(struct bcma_bus *bus)
|
|
|
@@ -537,7 +387,7 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
|
|
|
+ struct resource *res;
|
|
|
+ struct bcma_device *arm_core;
|
|
|
+ u32 cru_straps_ctrl;
|
|
|
-+ int allow_gen2, linkfail;
|
|
|
++ int ret;
|
|
|
+ int phyaddr;
|
|
|
+
|
|
|
+ if (bdev->core_unit == 2) {
|
|
|
@@ -561,8 +411,8 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ res->start = bdev->addr_s[0];
|
|
|
-+ res->end = res->start + SZ_128M - 1;
|
|
|
-+ res->name = "PCIe Configuration Space";
|
|
|
++ res->end = bdev->addr_s[0] + SZ_128M -1;
|
|
|
++ res->name = "PCIe dummy IO space";
|
|
|
+ res->flags = IORESOURCE_MEM;
|
|
|
+
|
|
|
+ pci_add_resource(&sys->resources, res);
|
|
|
@@ -572,55 +422,36 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
|
|
|
+ if (!res)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
-+ res->start = bdev->addr_s[0];
|
|
|
-+ res->end = res->start + SZ_128M - 1;
|
|
|
-+ res->name = "PCIe Configuration Space";
|
|
|
++ res->start = 0;
|
|
|
++ res->end = 0;
|
|
|
++ res->name = "PCIe dummy IO space";
|
|
|
+ res->flags = IORESOURCE_IO;
|
|
|
+
|
|
|
+ pci_add_resource(&sys->resources, res);
|
|
|
+
|
|
|
-+ for (allow_gen2 = 0; allow_gen2 <= 1; allow_gen2++) {
|
|
|
-+ bcma_pcie2_hw_init(bdev);
|
|
|
-+ bcma_pcie2_map_init(bdev);
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Skip inactive ports -
|
|
|
-+ * will need to change this for hot-plugging
|
|
|
-+ */
|
|
|
-+ linkfail = bcma_pcie2_check_link(bdev, sys, allow_gen2);
|
|
|
-+ if (linkfail)
|
|
|
-+ break;
|
|
|
-+
|
|
|
-+ bcma_pcie2_bridge_init(bdev);
|
|
|
-+
|
|
|
-+ if (allow_gen2 == 0) {
|
|
|
-+ if (bcma_pcie2_allow_gen2_rc(bdev) == 0)
|
|
|
-+ break;
|
|
|
-+ dev_info(&bdev->dev, "switching to GEN2\n");
|
|
|
-+ }
|
|
|
-+ }
|
|
|
++ bcma_pcie2_hw_init(bdev);
|
|
|
++ ret = bcma_pcie2_map_init(bdev, bdev->addr_s[0]);
|
|
|
++ if (ret)
|
|
|
++ return ret;
|
|
|
++
|
|
|
++ /*
|
|
|
++ * Skip inactive ports -
|
|
|
++ * will need to change this for hot-plugging
|
|
|
++ */
|
|
|
++ ret = bcma_pcie2_check_link(bdev, true);
|
|
|
++ if (ret)
|
|
|
++ return ret;
|
|
|
+
|
|
|
-+ if (linkfail)
|
|
|
-+ return -1;
|
|
|
++ ret = bcma_pcie2_bridge_init(bdev, bdev->addr_s[0], SZ_128M);
|
|
|
++ if (ret)
|
|
|
++ return ret;
|
|
|
+
|
|
|
+ return 1;
|
|
|
+}
|
|
|
+
|
|
|
-+/*
|
|
|
-+ * Methods for accessing configuration registers
|
|
|
-+ */
|
|
|
-+static struct pci_ops bcma_pcie2_ops = {
|
|
|
-+ .read = bcma_pcie2_read_config_pci,
|
|
|
-+ .write = bcma_pcie2_write_config_pci,
|
|
|
-+};
|
|
|
-+
|
|
|
+static int bcma_pcie2_probe(struct bcma_device *bdev)
|
|
|
+{
|
|
|
-+ struct hw_pci hw;
|
|
|
-+
|
|
|
-+ dev_info(&bdev->dev, "scanning bus\n");
|
|
|
-+
|
|
|
-+ hw = (struct hw_pci) {
|
|
|
++ struct hw_pci hw = {
|
|
|
+ .nr_controllers = 1,
|
|
|
+ .domain = bdev->core_unit,
|
|
|
+ .private_data = (void **)&bdev,
|
|
|
@@ -629,11 +460,13 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
|
|
|
+ .ops = &bcma_pcie2_ops,
|
|
|
+ };
|
|
|
+
|
|
|
++ dev_info(&bdev->dev, "initializing PCIe controller\n");
|
|
|
++
|
|
|
+ /* Announce this port to ARM/PCI common code */
|
|
|
+ pci_common_init_dev(&bdev->dev, &hw);
|
|
|
+
|
|
|
+ /* Setup virtual-wire interrupts */
|
|
|
-+ bcma_write32(bdev, SOC_PCIE_SYS_RC_INTX_EN, 0xf);
|
|
|
++ bcma_write32(bdev, BCMA_CORE_PCIE2_SYS_RC_INTX_EN, 0xf);
|
|
|
+
|
|
|
+ /* Enable memory and bus master */
|
|
|
+ bcma_write32(bdev, SOC_PCIE_HDR_OFF + 4, 0x6);
|
|
|
@@ -666,5 +499,5 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
|
|
|
+module_exit(bcma_pcie2_exit);
|
|
|
+
|
|
|
+MODULE_AUTHOR("Hauke Mehrtens");
|
|
|
-+MODULE_DESCRIPTION("PCIe Gen2 driver for BCMA");
|
|
|
++MODULE_DESCRIPTION("BCM5301X PCIe host controller");
|
|
|
+MODULE_LICENSE("GPLv2");
|
Hauke Mehrtens