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@@ -0,0 +1,220 @@
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+From e5ee12817e9eac891c6b2a340f64d94d9abd355f Mon Sep 17 00:00:00 2001
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+From: Maxime Ripard <[email protected]>
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+Date: Thu, 8 Jan 2015 18:38:09 +0100
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+Subject: [PATCH 4/4] ARM: mvebu: Add Armada 385 Access Point Development Board
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+ support
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+
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+The A385-AP is a board produced by Marvell that holds 3 mPCIe slot, a 16MB
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+SPI-NOR, 3 Gigabit Ethernet ports, USB3 and NAND flash storage.
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+
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+[[email protected]: switch the license to the dual
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+X11/GPL with the agreement of the author]
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+
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+Signed-off-by: Maxime Ripard <[email protected]>
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+Signed-off-by: Gregory CLEMENT <[email protected]>
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+Signed-off-by: Andrew Lunn <[email protected]>
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+---
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+ arch/arm/boot/dts/Makefile | 1 +
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+ arch/arm/boot/dts/armada-385-db-ap.dts | 178 +++++++++++++++++++++++++++++++++
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+ 2 files changed, 179 insertions(+)
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+ create mode 100644 arch/arm/boot/dts/armada-385-db-ap.dts
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+
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+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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+index 6dc9c17f9ff5..d34837104949 100644
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+--- a/arch/arm/boot/dts/Makefile
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++++ b/arch/arm/boot/dts/Makefile
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+@@ -536,6 +536,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \
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+ armada-375-db.dtb
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+ dtb-$(CONFIG_MACH_ARMADA_38X) += \
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+ armada-385-db.dtb \
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++ armada-385-db-ap.dtb \
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+ armada-385-rd.dtb
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+ dtb-$(CONFIG_MACH_ARMADA_XP) += \
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+ armada-xp-axpwifiap.dtb \
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+diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
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+new file mode 100644
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+index 000000000000..57b9119fb3e0
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+--- /dev/null
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++++ b/arch/arm/boot/dts/armada-385-db-ap.dts
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+@@ -0,0 +1,178 @@
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++/*
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++ * Device Tree file for Marvell Armada 385 Access Point Development board
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++ * (DB-88F6820-AP)
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++ *
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++ * Copyright (C) 2014 Marvell
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++ *
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++ * Nadav Haklai <[email protected]>
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++ *
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++ * This file is dual-licensed: you can use it either under the terms
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++ * of the GPL or the X11 license, at your option. Note that this dual
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++ * licensing only applies to this file, and not this project as a
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++ * whole.
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++ *
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++ * a) This file is licensed under the terms of the GNU General Public
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++ * License version 2. This program is licensed "as is" without
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++ * any warranty of any kind, whether express or implied.
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++ *
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++ * Or, alternatively,
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++ *
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++ * b) Permission is hereby granted, free of charge, to any person
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++ * obtaining a copy of this software and associated documentation
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++ * files (the "Software"), to deal in the Software without
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++ * restriction, including without limitation the rights to use,
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++ * copy, modify, merge, publish, distribute, sublicense, and/or
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++ * sell copies of the Software, and to permit persons to whom the
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++ * Software is furnished to do so, subject to the following
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++ * conditions:
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++ *
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++ * The above copyright notice and this permission notice shall be
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++ * included in all copies or substantial portions of the Software.
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++ *
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++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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++ * OTHER DEALINGS IN THE SOFTWARE.
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++ */
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++
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++/dts-v1/;
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++#include "armada-385.dtsi"
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++
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++#include <dt-bindings/gpio/gpio.h>
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++
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++/ {
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++ model = "Marvell Armada 385 Access Point Development Board";
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++ compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
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++
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++ chosen {
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++ bootargs = "console=ttyS0,115200";
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++ stdout-path = &uart1;
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++ };
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++
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++ memory {
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++ device_type = "memory";
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++ reg = <0x00000000 0x80000000>; /* 2GB */
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++ };
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++
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++ soc {
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++ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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++ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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++
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++ internal-regs {
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++ spi1: spi@10680 {
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++ pinctrl-names = "default";
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++ pinctrl-0 = <&spi1_pins>;
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++ status = "okay";
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++
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++ spi-flash@0 {
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++ compatible = "st,m25p128";
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++ reg = <0>; /* Chip select 0 */
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++ spi-max-frequency = <54000000>;
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++ };
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++ };
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++
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++ i2c0: i2c@11000 {
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++ pinctrl-names = "default";
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++ pinctrl-0 = <&i2c0_pins>;
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++ status = "okay";
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++
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++ /*
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++ * This bus is wired to two EEPROM
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++ * sockets, one of which holding the
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++ * board ID used by the bootloader.
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++ * Erasing this EEPROM's content will
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++ * brick the board.
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++ * Use this bus with caution.
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++ */
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++ };
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++
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++ mdio@72004 {
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++ pinctrl-names = "default";
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++ pinctrl-0 = <&mdio_pins>;
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++
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++ phy0: ethernet-phy@1 {
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++ reg = <1>;
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++ };
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++
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++ phy1: ethernet-phy@4 {
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++ reg = <4>;
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++ };
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++
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++ phy2: ethernet-phy@6 {
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++ reg = <6>;
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++ };
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++ };
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++
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++ /* UART0 is exposed through the JP8 connector */
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++ uart0: serial@12000 {
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++ pinctrl-names = "default";
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++ pinctrl-0 = <&uart0_pins>;
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++ status = "okay";
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++ };
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++
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++ /*
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++ * UART1 is exposed through a FTDI chip
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++ * wired to the mini-USB connector
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++ */
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++ uart1: serial@12100 {
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++ pinctrl-names = "default";
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++ pinctrl-0 = <&uart1_pins>;
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++ status = "okay";
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++ };
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++
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++ ethernet@30000 {
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++ status = "okay";
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++ phy = <&phy2>;
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++ phy-mode = "sgmii";
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++ };
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++
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++ ethernet@34000 {
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++ status = "okay";
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++ phy = <&phy1>;
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++ phy-mode = "sgmii";
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++ };
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++
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++ ethernet@70000 {
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++ pinctrl-names = "default";
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++
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++ /*
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++ * The Reference Clock 0 is used to
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++ * provide a clock to the PHY
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++ */
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++ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
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++ status = "okay";
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++ phy = <&phy0>;
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++ phy-mode = "rgmii-id";
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++ };
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++ };
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++
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++ pcie-controller {
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++ status = "okay";
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++
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++ /*
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++ * The three PCIe units are accessible through
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++ * standard mini-PCIe slots on the board.
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++ */
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++ pcie@1,0 {
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++ /* Port 0, Lane 0 */
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++ status = "okay";
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++ };
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++
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++ pcie@2,0 {
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++ /* Port 1, Lane 0 */
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++ status = "okay";
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++ };
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++
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++ pcie@3,0 {
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++ /* Port 2, Lane 0 */
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++ status = "okay";
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++ };
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++ };
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++ };
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++};
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+--
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+2.2.1
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+
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Imre Kaloz