realtek: restructure Zyxel XGS1210-12 device tree files

This is a preparation for adding support for XGS1010-12, which is almost
identical to XGS1210-12, with some small differences (partition layout,
missing reset key).

In addition to moving the common parts to a new file, also simplify the
definition of the 2.5G PHYs to reduce duplication. With this change, the
revision-specific files only have to specify the SMI addresses.

Signed-off-by: Jan Hoffmann <[email protected]>
Link: https://github.com/openwrt/openwrt/pull/20469
Signed-off-by: Robert Marko <[email protected]>

target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-a1.dts

@@ -8,41 +8,10 @@
 	model = "Zyxel XGS1210-12 A1 Switch";
 };
 
-&mdio_bus0 {
-	phy24: ethernet-phy@24 {
-		reg = <24>;
-		compatible = "ethernet-phy-ieee802.3-c45";
-		rtl9300,smi-address = <1 8>;
-		// Disabled because we do not know how to bring up again
-		// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
-	};
-
-	phy25: ethernet-phy@25 {
-		reg = <25>;
-		compatible = "ethernet-phy-ieee802.3-c45";
-		rtl9300,smi-address = <2 9>;
-		// Disabled because we do not know how to bring up again
-		// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
-	};
+&phy24 {
+	rtl9300,smi-address = <1 8>;
 };
 
-&switch0 {
-	ports {
-		port@24 {
-			reg = <24>;
-			label = "lan9";
-			pcs-handle = <&serdes6>;
-			phy-handle = <&phy24>;
-			phy-mode = "2500base-x";
-			led-set = <1>;
-		};
-		port@25 {
-			reg = <25>;
-			label = "lan10";
-			pcs-handle = <&serdes7>;
-			phy-handle = <&phy25>;
-			phy-mode = "2500base-x";
-			led-set = <1>;
-		};
-	};
+&phy25 {
+	rtl9300,smi-address = <2 9>;
 };

target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-b1.dts

@@ -8,41 +8,10 @@
 	model = "Zyxel XGS1210-12 B1 Switch";
 };
 
-&mdio_bus0 {
-	phy24: ethernet-phy@24 {
-		reg = <24>;
-		compatible = "ethernet-phy-ieee802.3-c45";
-		rtl9300,smi-address = <1 1>;
-		// Disabled because we do not know how to bring up again
-		// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
-	};
-
-	phy25: ethernet-phy@25 {
-		reg = <25>;
-		compatible = "ethernet-phy-ieee802.3-c45";
-		rtl9300,smi-address = <2 2>;
-		// Disabled because we do not know how to bring up again
-		// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
-	};
+&phy24 {
+	rtl9300,smi-address = <1 1>;
 };
 
-&switch0 {
-	ports {
-		port@24 {
-			reg = <24>;
-			label = "lan9";
-			pcs-handle = <&serdes6>;
-			phy-handle = <&phy24>;
-			phy-mode = "2500base-x";
-			led-set = <1>;
-		};
-		port@25 {
-			reg = <25>;
-			label = "lan10";
-			pcs-handle = <&serdes7>;
-			phy-handle = <&phy25>;
-			phy-mode = "2500base-x";
-			led-set = <1>;
-		};
-	};
+&phy25 {
+	rtl9300,smi-address = <2 2>;
 };

target/linux/realtek/dts/rtl9302_zyxel_xgs1210-12-common.dtsi

@@ -1,21 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /dts-v1/;
 
-#include "rtl930x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/thermal/thermal.h>
+#include "rtl9302_zyxel_xgs1x10-12-common.dtsi"
 
 / {
-	aliases {
-		led-boot = &led_pwr_sys;
-		led-failsafe = &led_pwr_sys;
-		led-running = &led_pwr_sys;
-		led-upgrade = &led_pwr_sys;
-	};
-
 	keys {
 		compatible = "gpio-keys";
 
@@ -25,76 +13,6 @@
 			linux,code = <KEY_RESTART>;
 		};
 	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinmux_disable_sys_led>;
-
-		led_pwr_sys: led-0 {
-			label = "green:power";
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_POWER;
-			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	sfp0: sfp-p11 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c0>;
-		los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
-	};
-
-	sfp1: sfp-p12 {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c1>;
-		los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
-	};
-
-	led_set: led_set {
-		compatible = "realtek,rtl9300-leds";
-		active-low;
-
-		// LED set 0:
-		// Amber: 100M/10M
-		// Yellow: 1G
-		led_set0 = <0x0a20 0x0b80>;
-
-		// LED set 1:
-		// Blue: 2.5G
-		// Green: 2.5G
-		// Yellow: 1G
-		// Amber: 100M/10M
-		// (Blue + Green = Cyan)
-		led_set1 = <0x0b80 0x0a20 0x0a08 0x0a08>;
-
-		// LED set 2:
-		// Blue: 10G/5G/2.5G
-		// Yellow: 5G/2.5G/1G
-		// (Blue + Yellow = Purple)
-		led_set2 = <0x0a2a 0x0a0b>;
-	};
-};
-
-&i2c_mst1 {
-	status = "okay";
-
-	/* i2c of the left SFP+ cage seen from the front; port 11 */
-	i2c0: i2c@0 {
-		reg = <0>;
-	};
-
-	/* i2c of the right SFP+ cage seen from the front; port 12 */
-	i2c1: i2c@1 {
-		reg = <1>;
-	};
 };
 
 &spi0 {
@@ -145,151 +63,3 @@
 		};
 	};
 };
-
-&mdio_bus0 {
-	/* External RTL8218D PHY */
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		compatible = "ethernet-phy-ieee802.3-c22";
-		rtl9300,smi-address = <0 0>;
-		// Disabled because we do not know how to bring up again
-		// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
-	};
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-		compatible = "ethernet-phy-ieee802.3-c22";
-		rtl9300,smi-address = <0 1>;
-	};
-	phy2: ethernet-phy@2 {
-		reg = <2>;
-		compatible = "ethernet-phy-ieee802.3-c22";
-		rtl9300,smi-address = <0 2>;
-	};
-	phy3: ethernet-phy@3 {
-		reg = <3>;
-		compatible = "ethernet-phy-ieee802.3-c22";
-		rtl9300,smi-address = <0 3>;
-	};
-	phy4: ethernet-phy@4 {
-		reg = <4>;
-		compatible = "ethernet-phy-ieee802.3-c22";
-		rtl9300,smi-address = <0 4>;
-	};
-	phy5: ethernet-phy@5 {
-		reg = <5>;
-		compatible = "ethernet-phy-ieee802.3-c22";
-		rtl9300,smi-address = <0 5>;
-	};
-	phy6: ethernet-phy@6 {
-		reg = <6>;
-		compatible = "ethernet-phy-ieee802.3-c22";
-		rtl9300,smi-address = <0 6>;
-	};
-	phy7: ethernet-phy@7 {
-		reg = <7>;
-		compatible = "ethernet-phy-ieee802.3-c22";
-		rtl9300,smi-address = <0 7>;
-	};
-};
-
-&switch0 {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-			label = "lan1";
-			pcs-handle = <&serdes2>;
-			phy-handle = <&phy0>;
-			phy-mode = "usxgmii";
-			led-set = <0>;
-		};
-		port@1 {
-			reg = <1>;
-			label = "lan2";
-			pcs-handle = <&serdes2>;
-			phy-handle = <&phy1>;
-			phy-mode = "usxgmii";
-			led-set = <0>;
-		};
-		port@2 {
-			reg = <2>;
-			label = "lan3";
-			pcs-handle = <&serdes2>;
-			phy-handle = <&phy2>;
-			phy-mode = "usxgmii";
-			led-set = <0>;
-		};
-		port@3 {
-			reg = <3>;
-			label = "lan4";
-			pcs-handle = <&serdes2>;
-			phy-handle = <&phy3>;
-			phy-mode = "usxgmii";
-			led-set = <0>;
-		};
-		port@4 {
-			reg = <4>;
-			label = "lan5";
-			pcs-handle = <&serdes2>;
-			phy-handle = <&phy4>;
-			phy-mode = "usxgmii";
-			led-set = <0>;
-		};
-		port@5 {
-			reg = <5>;
-			label = "lan6";
-			pcs-handle = <&serdes2>;
-			phy-handle = <&phy5>;
-			phy-mode = "usxgmii";
-			led-set = <0>;
-		};
-		port@6 {
-			reg = <6>;
-			label = "lan7";
-			pcs-handle = <&serdes2>;
-			phy-handle = <&phy6>;
-			phy-mode = "usxgmii";
-			led-set = <0>;
-		};
-		port@7 {
-			reg = <7>;
-			label = "lan8";
-			pcs-handle = <&serdes2>;
-			phy-handle = <&phy7>;
-			phy-mode = "usxgmii";
-			led-set = <0>;
-		};
-
-		port@26 {
-			reg = <26>;
-			label = "lan11";
-			pcs-handle = <&serdes8>;
-			phy-mode = "1000base-x";
-			sfp = <&sfp0>;
-			led-set = <2>;
-			managed = "in-band-status";
-		};
-
-		port@27 {
-			reg = <27>;
-			label = "lan12";
-			pcs-handle = <&serdes9>;
-			phy-mode = "1000base-x";
-			sfp = <&sfp1>;
-			led-set = <2>;
-			managed = "in-band-status";
-		};
-
-		port@28 {
-			ethernet = <&ethernet0>;
-			reg = <28>;
-			phy-mode = "internal";
-			fixed-link {
-				speed = <10000>;
-				full-duplex;
-			};
-		};
-	};
-};

target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi

@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "rtl930x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	aliases {
+		led-boot = &led_pwr_sys;
+		led-failsafe = &led_pwr_sys;
+		led-running = &led_pwr_sys;
+		led-upgrade = &led_pwr_sys;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinmux_disable_sys_led>;
+
+		led_pwr_sys: led-0 {
+			label = "green:power";
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	sfp0: sfp-p11 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c0>;
+		los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
+		tx-disable-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+	};
+
+	sfp1: sfp-p12 {
+		compatible = "sff,sfp";
+		i2c-bus = <&i2c1>;
+		los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
+		tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+	};
+
+	led_set: led_set {
+		compatible = "realtek,rtl9300-leds";
+		active-low;
+
+		// LED set 0:
+		// Amber: 100M/10M
+		// Yellow: 1G
+		led_set0 = <0x0a20 0x0b80>;
+
+		// LED set 1:
+		// Blue: 2.5G
+		// Green: 2.5G
+		// Yellow: 1G
+		// Amber: 100M/10M
+		// (Blue + Green = Cyan)
+		led_set1 = <0x0b80 0x0a20 0x0a08 0x0a08>;
+
+		// LED set 2:
+		// Blue: 10G/5G/2.5G
+		// Yellow: 5G/2.5G/1G
+		// (Blue + Yellow = Purple)
+		led_set2 = <0x0a2a 0x0a0b>;
+	};
+};
+
+&i2c_mst1 {
+	status = "okay";
+
+	/* i2c of the left SFP+ cage seen from the front; port 11 */
+	i2c0: i2c@0 {
+		reg = <0>;
+	};
+
+	/* i2c of the right SFP+ cage seen from the front; port 12 */
+	i2c1: i2c@1 {
+		reg = <1>;
+	};
+};
+
+&mdio_bus0 {
+	/* External RTL8218D PHY */
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+		rtl9300,smi-address = <0 0>;
+		// Disabled because we do not know how to bring up again
+		// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+	};
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+		rtl9300,smi-address = <0 1>;
+	};
+	phy2: ethernet-phy@2 {
+		reg = <2>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+		rtl9300,smi-address = <0 2>;
+	};
+	phy3: ethernet-phy@3 {
+		reg = <3>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+		rtl9300,smi-address = <0 3>;
+	};
+	phy4: ethernet-phy@4 {
+		reg = <4>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+		rtl9300,smi-address = <0 4>;
+	};
+	phy5: ethernet-phy@5 {
+		reg = <5>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+		rtl9300,smi-address = <0 5>;
+	};
+	phy6: ethernet-phy@6 {
+		reg = <6>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+		rtl9300,smi-address = <0 6>;
+	};
+	phy7: ethernet-phy@7 {
+		reg = <7>;
+		compatible = "ethernet-phy-ieee802.3-c22";
+		rtl9300,smi-address = <0 7>;
+	};
+
+	phy24: ethernet-phy@24 {
+		reg = <24>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		// Disabled because we do not know how to bring up again
+		// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+	};
+
+	phy25: ethernet-phy@25 {
+		reg = <25>;
+		compatible = "ethernet-phy-ieee802.3-c45";
+		// Disabled because we do not know how to bring up again
+		// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&switch0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			label = "lan1";
+			pcs-handle = <&serdes2>;
+			phy-handle = <&phy0>;
+			phy-mode = "usxgmii";
+			led-set = <0>;
+		};
+		port@1 {
+			reg = <1>;
+			label = "lan2";
+			pcs-handle = <&serdes2>;
+			phy-handle = <&phy1>;
+			phy-mode = "usxgmii";
+			led-set = <0>;
+		};
+		port@2 {
+			reg = <2>;
+			label = "lan3";
+			pcs-handle = <&serdes2>;
+			phy-handle = <&phy2>;
+			phy-mode = "usxgmii";
+			led-set = <0>;
+		};
+		port@3 {
+			reg = <3>;
+			label = "lan4";
+			pcs-handle = <&serdes2>;
+			phy-handle = <&phy3>;
+			phy-mode = "usxgmii";
+			led-set = <0>;
+		};
+		port@4 {
+			reg = <4>;
+			label = "lan5";
+			pcs-handle = <&serdes2>;
+			phy-handle = <&phy4>;
+			phy-mode = "usxgmii";
+			led-set = <0>;
+		};
+		port@5 {
+			reg = <5>;
+			label = "lan6";
+			pcs-handle = <&serdes2>;
+			phy-handle = <&phy5>;
+			phy-mode = "usxgmii";
+			led-set = <0>;
+		};
+		port@6 {
+			reg = <6>;
+			label = "lan7";
+			pcs-handle = <&serdes2>;
+			phy-handle = <&phy6>;
+			phy-mode = "usxgmii";
+			led-set = <0>;
+		};
+		port@7 {
+			reg = <7>;
+			label = "lan8";
+			pcs-handle = <&serdes2>;
+			phy-handle = <&phy7>;
+			phy-mode = "usxgmii";
+			led-set = <0>;
+		};
+
+		port@24 {
+			reg = <24>;
+			label = "lan9";
+			pcs-handle = <&serdes6>;
+			phy-handle = <&phy24>;
+			phy-mode = "2500base-x";
+			led-set = <1>;
+		};
+		port@25 {
+			reg = <25>;
+			label = "lan10";
+			pcs-handle = <&serdes7>;
+			phy-handle = <&phy25>;
+			phy-mode = "2500base-x";
+			led-set = <1>;
+		};
+
+		port@26 {
+			reg = <26>;
+			label = "lan11";
+			pcs-handle = <&serdes8>;
+			phy-mode = "1000base-x";
+			sfp = <&sfp0>;
+			led-set = <2>;
+			managed = "in-band-status";
+		};
+
+		port@27 {
+			reg = <27>;
+			label = "lan12";
+			pcs-handle = <&serdes9>;
+			phy-mode = "1000base-x";
+			sfp = <&sfp1>;
+			led-set = <2>;
+			managed = "in-band-status";
+		};
+
+		port@28 {
+			ethernet = <&ethernet0>;
+			reg = <28>;
+			phy-mode = "internal";
+			fixed-link {
+				speed = <10000>;
+				full-duplex;
+			};
+		};
+	};
+};