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@@ -176,8 +176,10 @@ static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, struct list_head *qh_list)
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qtd_item = qh->qtd_list.next) {
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qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
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if (qtd->urb != NULL) {
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+ SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
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dwc_otg_hcd_complete_urb(hcd, qtd->urb,
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-ETIMEDOUT);
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+ SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
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}
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dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
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}
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@@ -589,6 +591,7 @@ static void hcd_reinit(dwc_otg_hcd_t *hcd)
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hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
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hcd->non_periodic_channels = 0;
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hcd->periodic_channels = 0;
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+ hcd->nakking_channels = 0;
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/*
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* Put all channels in the free channel list and clean up channel
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@@ -853,10 +856,10 @@ static void dump_channel_info(dwc_otg_hcd_t *hcd,
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//OTG host require the DMA addr is DWORD-aligned,
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//patch it if the buffer is not DWORD-aligned
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inline
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-void hcd_check_and_patch_dma_addr(struct urb *urb){
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+int hcd_check_and_patch_dma_addr(struct urb *urb){
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if((!urb->transfer_buffer)||!urb->transfer_dma||urb->transfer_dma==0xffffffff)
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- return;
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+ return 0;
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if(((u32)urb->transfer_buffer)& 0x3){
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/*
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@@ -881,11 +884,12 @@ void hcd_check_and_patch_dma_addr(struct urb *urb){
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kfree(urb->aligned_transfer_buffer);
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}
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urb->aligned_transfer_buffer=kmalloc(urb->aligned_transfer_buffer_length,GFP_KERNEL|GFP_DMA|GFP_ATOMIC);
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- urb->aligned_transfer_dma=dma_map_single(NULL,(void *)(urb->aligned_transfer_buffer),(urb->aligned_transfer_buffer_length),DMA_FROM_DEVICE);
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if(!urb->aligned_transfer_buffer){
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DWC_ERROR("Cannot alloc required buffer!!\n");
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- BUG();
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+ //BUG();
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+ return -1;
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}
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+ urb->aligned_transfer_dma=dma_map_single(NULL,(void *)(urb->aligned_transfer_buffer),(urb->aligned_transfer_buffer_length),DMA_FROM_DEVICE);
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//printk(" new allocated aligned_buf=%.8x aligned_buf_len=%d\n", (u32)urb->aligned_transfer_buffer, urb->aligned_transfer_buffer_length);
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}
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urb->transfer_dma=urb->aligned_transfer_dma;
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@@ -894,6 +898,7 @@ void hcd_check_and_patch_dma_addr(struct urb *urb){
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dma_sync_single_for_device(NULL,urb->transfer_dma,urb->transfer_buffer_length,DMA_TO_DEVICE);
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}
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}
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+ return 0;
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}
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@@ -910,7 +915,15 @@ int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
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int retval = 0;
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dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
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dwc_otg_qtd_t *qtd;
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+ unsigned long flags;
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+
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+ SPIN_LOCK_IRQSAVE(&dwc_otg_hcd->lock, flags);
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+
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+ if (urb->hcpriv != NULL) {
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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+ return -ENOMEM;
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+ }
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#ifdef DEBUG
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if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
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dump_urb_info(urb, "dwc_otg_hcd_urb_enqueue");
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@@ -918,13 +931,19 @@ int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
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#endif
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if (!dwc_otg_hcd->flags.b.port_connect_status) {
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/* No longer connected. */
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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return -ENODEV;
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}
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- hcd_check_and_patch_dma_addr(urb);
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+ if (hcd_check_and_patch_dma_addr(urb)) {
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+ DWC_ERROR("Unable to check and patch dma addr\n");
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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+ return -ENOMEM;
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+ }
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qtd = dwc_otg_hcd_qtd_create(urb);
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if (qtd == NULL) {
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DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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return -ENOMEM;
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}
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@@ -934,7 +953,7 @@ int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
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"Error status %d\n", retval);
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dwc_otg_hcd_qtd_free(qtd);
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}
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-
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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return retval;
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}
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@@ -948,6 +967,7 @@ int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
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dwc_otg_qtd_t *urb_qtd;
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dwc_otg_qh_t *qh;
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struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
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+ int rc;
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DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
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@@ -958,10 +978,6 @@ int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
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urb_qtd = (dwc_otg_qtd_t *)urb->hcpriv;
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qh = (dwc_otg_qh_t *)ep->hcpriv;
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- if (urb_qtd == NULL) {
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- SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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- return 0;
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- }
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#ifdef DEBUG
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if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
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dump_urb_info(urb, "dwc_otg_hcd_urb_dequeue");
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@@ -971,7 +987,7 @@ int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
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}
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#endif
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- if (urb_qtd == qh->qtd_in_process) {
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+ if (qh && urb_qtd == qh->qtd_in_process) {
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/* The QTD is in process (it has been assigned to a channel). */
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if (dwc_otg_hcd->flags.b.port_connect_status) {
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@@ -982,7 +998,7 @@ int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
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* written to halt the channel since the core is in
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* device mode.
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*/
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- dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
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+ dwc_otg_hc_halt(dwc_otg_hcd, qh->channel,
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DWC_OTG_HC_XFER_URB_DEQUEUE);
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}
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}
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@@ -992,22 +1008,28 @@ int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
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* schedule if it has any remaining QTDs.
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*/
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dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd, urb_qtd);
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- if (urb_qtd == qh->qtd_in_process) {
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- /* Note that dwc_otg_hcd_qh_deactivate() locks the spin_lock again */
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- SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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+ if (qh && urb_qtd == qh->qtd_in_process) {
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dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
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qh->channel = NULL;
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qh->qtd_in_process = NULL;
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} else {
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- if (list_empty(&qh->qtd_list))
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+ if (qh && list_empty(&qh->qtd_list)) {
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dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
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- SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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+ }
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}
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+
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+ rc = usb_hcd_check_unlink_urb(hcd, urb, status);
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+
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+ if (!rc) {
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+ usb_hcd_unlink_urb_from_ep(hcd, urb);
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+ }
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urb->hcpriv = NULL;
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+ SPIN_UNLOCK_IRQRESTORE(&dwc_otg_hcd->lock, flags);
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- /* Higher layer software sets URB status. */
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- usb_hcd_giveback_urb(hcd, urb, status);
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+ if (!rc) {
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+ usb_hcd_giveback_urb(hcd, urb, status);
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+ }
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if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
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DWC_PRINT("Called usb_hcd_giveback_urb()\n");
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DWC_PRINT(" urb->status = %d\n", urb->status);
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@@ -2035,15 +2057,19 @@ static void assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
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dwc_otg_qtd_t *qtd;
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struct urb *urb;
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- DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
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-
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+ DWC_DEBUGPL(DBG_HCD_FLOOD, "%s(%p,%p)\n", __func__, hcd, qh);
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hc = list_entry(hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
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+ qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
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+ urb = qtd->urb;
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+
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+ if (!urb){
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+ return;
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+ }
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+
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/* Remove the host channel from the free list. */
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list_del_init(&hc->hc_list_entry);
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- qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
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- urb = qtd->urb;
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qh->channel = hc;
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qh->qtd_in_process = qtd;
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@@ -2202,16 +2228,24 @@ static void assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
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dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
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{
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struct list_head *qh_ptr;
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- dwc_otg_qh_t *qh;
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+ dwc_otg_qh_t *qh = NULL;
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int num_channels;
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dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
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+ uint16_t cur_frame = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
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+ unsigned long flags;
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+ int include_nakd, channels_full;
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+ /* This condition has once been observed, but the cause was
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+ * never determined. Check for it here, to collect debug data if
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+ * it occurs again. */
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+ WARN_ON_ONCE(hcd->non_periodic_channels < 0);
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+ check_nakking(hcd, __FUNCTION__, "start");
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#ifdef DEBUG_SOF
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DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
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#endif
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- spin_lock(&hcd->lock);
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- /* Process entries in the periodic ready list. */
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+ SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
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+ /* Process entries in the periodic ready list. */
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qh_ptr = hcd->periodic_sched_ready.next;
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while (qh_ptr != &hcd->periodic_sched_ready &&
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!list_empty(&hcd->free_hc_list)) {
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@@ -2234,36 +2268,139 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
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* schedule. Some free host channels may not be used if they are
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* reserved for periodic transfers.
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*/
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- qh_ptr = hcd->non_periodic_sched_inactive.next;
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num_channels = hcd->core_if->core_params->host_channels;
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- while (qh_ptr != &hcd->non_periodic_sched_inactive &&
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- (hcd->non_periodic_channels <
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- num_channels - hcd->periodic_channels) &&
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- !list_empty(&hcd->free_hc_list)) {
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- qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
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- assign_and_init_hc(hcd, qh);
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+ /* Go over the queue twice: Once while not including nak'd
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+ * entries, one while including them. This is so a retransmit of
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+ * an entry that has received a nak is scheduled only after all
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+ * new entries.
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+ */
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+ channels_full = 0;
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+ for (include_nakd = 0; include_nakd < 2 && !channels_full; ++include_nakd) {
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+ qh_ptr = hcd->non_periodic_sched_inactive.next;
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+ while (qh_ptr != &hcd->non_periodic_sched_inactive) {
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+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
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+ qh_ptr = qh_ptr->next;
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- /*
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- * Move the QH from the non-periodic inactive schedule to the
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- * non-periodic active schedule.
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- */
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- qh_ptr = qh_ptr->next;
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- list_move(&qh->qh_list_entry, &hcd->non_periodic_sched_active);
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+ /* If a nak'd frame is in the queue for 100ms, forget
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+ * about its nak status, to prevent the situation where
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+ * a nak'd frame never gets resubmitted because there
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+ * are continously non-nakking tranfsfers available.
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+ */
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+ if (qh->nak_frame != 0xffff &&
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+ dwc_frame_num_gt(cur_frame, qh->nak_frame + 800))
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+ qh->nak_frame = 0xffff;
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- if (ret_val == DWC_OTG_TRANSACTION_NONE) {
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- ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
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- } else {
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- ret_val = DWC_OTG_TRANSACTION_ALL;
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+ /* In the first pass, ignore NAK'd retransmit
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+ * alltogether, to give them lower priority. */
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+ if (!include_nakd && qh->nak_frame != 0xffff)
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+ continue;
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+
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+ /*
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+ * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission
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+ * we hold off on bulk retransmissions to reduce NAK interrupt overhead for
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+ * cheeky devices that just hold off using NAKs
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+ */
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+ if (dwc_full_frame_num(qh->nak_frame) == dwc_full_frame_num(dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd))))
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+ continue;
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+
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+ /* Ok, we found a candidate for scheduling. Is there a
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+ * free channel? */
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+ if (hcd->non_periodic_channels >=
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+ num_channels - hcd->periodic_channels ||
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+ list_empty(&hcd->free_hc_list)) {
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+ channels_full = 1;
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+ break;
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+ }
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+
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+ /* When retrying a NAK'd transfer, we give it a fair
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+ * chance of completing again. */
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+ qh->nak_frame = 0xffff;
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+ assign_and_init_hc(hcd, qh);
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+
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+ /*
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+ * Move the QH from the non-periodic inactive schedule to the
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+ * non-periodic active schedule.
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+ */
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+ list_move(&qh->qh_list_entry, &hcd->non_periodic_sched_active);
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+
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+ if (ret_val == DWC_OTG_TRANSACTION_NONE) {
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+ ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
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+ } else {
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+ ret_val = DWC_OTG_TRANSACTION_ALL;
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+ }
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+
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+ hcd->non_periodic_channels++;
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}
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+ if (hcd->core_if->dma_enable && channels_full &&
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+ hcd->periodic_channels + hcd->nakking_channels >= num_channels) {
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+ /* There are items queued, but all channels are either
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+ * reserved for periodic or have received NAKs. This
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+ * means that it could take an indefinite amount of time
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+ * before a channel is actually freed (since in DMA
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+ * mode, the hardware takes care of retries), so we take
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+ * action here by forcing a nakking channel to halt to
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+ * give other transfers a chance to run. */
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+ dwc_otg_qtd_t *qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
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+ struct urb *urb = qtd->urb;
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+ dwc_hc_t *hc = dwc_otg_halt_nakking_channel(hcd);
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+
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+ if (hc)
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+ DWC_DEBUGPL(DBG_HCD "Out of Host Channels for non-periodic transfer - Halting channel %d (dev %d ep%d%s) to service qh %p (dev %d ep%d%s)\n", hc->hc_num, hc->dev_addr, hc->ep_num, (hc->ep_is_in ? "in" : "out"), qh, usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe), (usb_pipein(urb->pipe) != 0) ? "in" : "out");
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- hcd->non_periodic_channels++;
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+ }
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}
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|
- spin_unlock(&hcd->lock);
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+
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+ SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
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|
|
return ret_val;
|
|
|
}
|
|
|
|
|
|
+/**
|
|
|
+ * Halt a bulk channel that is blocking on NAKs to free up space.
|
|
|
+ *
|
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|
+ * This will decrement hcd->nakking_channels immediately, but
|
|
|
+ * hcd->non_periodic_channels is not decremented until the channel is
|
|
|
+ * actually halted.
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|
+ *
|
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|
+ * Returns the halted channel.
|
|
|
+ */
|
|
|
+dwc_hc_t *dwc_otg_halt_nakking_channel(dwc_otg_hcd_t *hcd) {
|
|
|
+ int num_channels, i;
|
|
|
+ uint16_t cur_frame;
|
|
|
+
|
|
|
+ cur_frame = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
|
|
|
+ num_channels = hcd->core_if->core_params->host_channels;
|
|
|
+
|
|
|
+ for (i = 0; i < num_channels; i++) {
|
|
|
+ int channel = (hcd->last_channel_halted + 1 + i) % num_channels;
|
|
|
+ dwc_hc_t *hc = hcd->hc_ptr_array[channel];
|
|
|
+ if (hc->xfer_started
|
|
|
+ && !hc->halt_on_queue
|
|
|
+ && !hc->halt_pending
|
|
|
+ && hc->qh->nak_frame != 0xffff) {
|
|
|
+ dwc_otg_hc_halt(hcd, hc, DWC_OTG_HC_XFER_NAK);
|
|
|
+ /* Store the last channel halted to
|
|
|
+ * fairly rotate the channel to halt.
|
|
|
+ * This prevent the scenario where there
|
|
|
+ * are three blocking endpoints and only
|
|
|
+ * two free host channels, where the
|
|
|
+ * blocking endpoint that gets hc 3 will
|
|
|
+ * never be halted, while the other two
|
|
|
+ * endpoints will be fighting over the
|
|
|
+ * other host channel. */
|
|
|
+ hcd->last_channel_halted = channel;
|
|
|
+ /* Update nak_frame, so this frame is
|
|
|
+ * kept at low priority for a period of
|
|
|
+ * time starting now. */
|
|
|
+ hc->qh->nak_frame = cur_frame;
|
|
|
+ return hc;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ dwc_otg_hcd_dump_state(hcd);
|
|
|
+ return NULL;
|
|
|
+}
|
|
|
+
|
|
|
/**
|
|
|
* Attempts to queue a single transaction request for a host channel
|
|
|
* associated with either a periodic or non-periodic transfer. This function
|
|
|
@@ -2298,7 +2435,7 @@ static int queue_transaction(dwc_otg_hcd_t *hcd,
|
|
|
/* Don't queue a request if the channel has been halted. */
|
|
|
retval = 0;
|
|
|
} else if (hc->halt_on_queue) {
|
|
|
- dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
|
|
|
+ dwc_otg_hc_halt(hcd, hc, hc->halt_status);
|
|
|
retval = 0;
|
|
|
} else if (hc->do_ping) {
|
|
|
if (!hc->xfer_started) {
|
|
|
@@ -2446,12 +2583,12 @@ static void process_periodic_channels(dwc_otg_hcd_t *hcd)
|
|
|
dwc_otg_host_global_regs_t *host_regs;
|
|
|
host_regs = hcd->core_if->host_if->host_global_regs;
|
|
|
|
|
|
- DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
|
|
|
+ DWC_DEBUGPL(DBG_HCD_FLOOD, "Queue periodic transactions\n");
|
|
|
#ifdef DEBUG
|
|
|
tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
|
|
|
- DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n",
|
|
|
+ DWC_DEBUGPL(DBG_HCD_FLOOD, " P Tx Req Queue Space Avail (before queue): %d\n",
|
|
|
tx_status.b.ptxqspcavail);
|
|
|
- DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
|
|
|
+ DWC_DEBUGPL(DBG_HCD_FLOOD, " P Tx FIFO Space Avail (before queue): %d\n",
|
|
|
tx_status.b.ptxfspcavail);
|
|
|
#endif
|
|
|
|
|
|
@@ -2586,7 +2723,12 @@ void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
|
|
|
*/
|
|
|
void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *hcd, struct urb *urb, int status)
|
|
|
{
|
|
|
+ unsigned long flags;
|
|
|
+
|
|
|
+ SPIN_LOCK_IRQSAVE(&hcd->lock, flags);
|
|
|
+
|
|
|
#ifdef DEBUG
|
|
|
+
|
|
|
if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
|
|
|
DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
|
|
|
__func__, urb, usb_pipedevice(urb->pipe),
|
|
|
@@ -2609,10 +2751,12 @@ void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *hcd, struct urb *urb, int status)
|
|
|
memcpy(urb->transfer_buffer,urb->aligned_transfer_buffer,urb->actual_length);
|
|
|
}
|
|
|
|
|
|
-
|
|
|
+ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
|
|
|
urb->status = status;
|
|
|
urb->hcpriv = NULL;
|
|
|
+ SPIN_UNLOCK_IRQRESTORE(&hcd->lock, flags);
|
|
|
usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status);
|
|
|
+
|
|
|
}
|
|
|
|
|
|
/*
|
|
|
@@ -2674,7 +2818,7 @@ void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
|
|
|
DWC_PRINT(" Num channels: %d\n", num_channels);
|
|
|
for (i = 0; i < num_channels; i++) {
|
|
|
dwc_hc_t *hc = hcd->hc_ptr_array[i];
|
|
|
- DWC_PRINT(" Channel %d:\n", i);
|
|
|
+ DWC_PRINT(" Channel %d: %p\n", i, hc);
|
|
|
DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
|
|
|
hc->dev_addr, hc->ep_num, hc->ep_is_in);
|
|
|
DWC_PRINT(" speed: %d\n", hc->speed);
|
|
|
@@ -2696,6 +2840,8 @@ void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
|
|
|
DWC_PRINT(" xact_pos: %d\n", hc->xact_pos);
|
|
|
DWC_PRINT(" requests: %d\n", hc->requests);
|
|
|
DWC_PRINT(" qh: %p\n", hc->qh);
|
|
|
+ if (hc->qh)
|
|
|
+ DWC_PRINT(" nak_frame: %x\n", hc->qh->nak_frame);
|
|
|
if (hc->xfer_started) {
|
|
|
hfnum_data_t hfnum;
|
|
|
hcchar_data_t hcchar;
|
|
|
@@ -2735,6 +2881,8 @@ void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
|
|
|
}
|
|
|
DWC_PRINT(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
|
|
|
DWC_PRINT(" periodic_channels: %d\n", hcd->periodic_channels);
|
|
|
+ DWC_PRINT(" nakking_channels: %d\n", hcd->nakking_channels);
|
|
|
+ DWC_PRINT(" last_channel_halted: %d\n", hcd->last_channel_halted);
|
|
|
DWC_PRINT(" periodic_usecs: %d\n", hcd->periodic_usecs);
|
|
|
np_tx_status.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts);
|
|
|
DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
|
Imre Kaloz