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@@ -0,0 +1,535 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+
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+/dts-v1/;
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+#include <dt-bindings/leds/common.h>
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/input/input.h>
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+
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+#include "mt7981b.dtsi"
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+
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+/ {
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+ model = "Teltonika RUTC50";
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+ compatible = "teltonika,rutc50", "mediatek,mt7981";
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+
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+ aliases {
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+ serial0 = &uart0;
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+ label-mac-device = &gmac0;
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+ led-boot = &power;
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+ led-failsafe = &power;
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+ led-running = &power;
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+ led-upgrade = &power;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ memory@40000000 {
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+ reg = <0 0x40000000 0 0x10000000>;
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+ device_type = "memory";
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+ };
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+
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+ reset {
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+ label = "reset";
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+ linux,code = <KEY_RESTART>;
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+ gpios = <&pio 6 GPIO_ACTIVE_LOW>;
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+ debounce-interval = <60>;
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+ };
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+ };
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+
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+ gpio-export {
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+ compatible = "gpio-export";
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+
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+ gpio_pcie_reset {
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+ gpio-export,name = "pcie_reset";
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+ gpio-export,output = <1>;
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+ gpios = <&pio 3 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ gpio_modem_power {
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+ gpio-export,name = "modem_power";
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+ gpio-export,output = <0>;
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+ gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ gpio_modem_reset {
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+ gpio-export,name = "modem_reset";
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+ gpio-export,output = <0>;
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+ gpios = <&pio 10 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ gpio_modem_status {
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+ gpio-export,name = "modem_status";
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+ gpio-export,input = <0>;
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+ gpios = <&pio 11 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ gpio_digital_input {
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+ gpio-export,name = "digital_input";
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+ gpio-export,input = <0>;
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+ gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ gpio_digital_output {
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+ gpio-export,name = "digital_output";
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+ gpio-export,output = <0>;
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+ gpios = <&pio 35 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ power: power {
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+ function = LED_FUNCTION_POWER;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&pio 15 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ wan_eth {
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+ function = "wan-eth";
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ wan_wifi {
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+ function = "wan-wifi";
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ wan_sim1 {
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+ function = "wan-sim1";
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio_hc595 0 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ wan_sim2 {
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+ function = "wan-sim2";
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio_hc595 7 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ wifi_2g {
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+ function = LED_FUNCTION_WLAN_2GHZ;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger = "phy0tpt";
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+ };
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+
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+ wifi_5g {
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+ function = LED_FUNCTION_WLAN_5GHZ;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&pio 5 GPIO_ACTIVE_LOW>;
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+ linux,default-trigger = "phy1tpt";
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+ };
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+
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+ 3G {
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+ function = "3G";
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio_hc595 6 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ 4G {
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+ function = "4G";
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio_hc595 5 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ 5G {
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+ function = "5G";
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio_hc595 4 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ rssi1 {
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+ function = "rssi-1";
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio_hc595 3 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ rssi2 {
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+ function = "rssi-2";
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio_hc595 2 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ rssi3 {
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+ function = "rssi-3";
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio_hc595 1 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+
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+ watchdog {
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+ compatible = "linux,wdt-gpio";
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+ gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
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+ hw_algo = "toggle";
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+ hw_margin_ms = <1000>;
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+ };
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+};
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+
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+ð {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gbe_led0_pins>, <&gbe_led1_pins>;
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+ status = "okay";
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+
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+ gmac0: mac@0 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <0>;
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+ phy-mode = "2500base-x";
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+ nvmem-cells = <&macaddr_config_0 0>;
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+ nvmem-cell-names = "mac-address";
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+
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+
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+ gmac1: mac@1 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <1>;
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+ label = "wan";
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+ phy-mode = "gmii";
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+ phy-handle = <&int_gbe_phy>;
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+ nvmem-cells = <&macaddr_config_0 1>;
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+ nvmem-cell-names = "mac-address";
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+ };
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+};
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+
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+&int_gbe_phy_led0{
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+ function = LED_FUNCTION_WAN;
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+ color = <LED_COLOR_ID_AMBER>;
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+ status = "okay";
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+};
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+
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+&int_gbe_phy_led1{
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+ function = LED_FUNCTION_WAN;
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+ color = <LED_COLOR_ID_GREEN>;
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+ status = "okay";
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+};
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+
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+&mdio_bus {
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+ switch: switch@1f {
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+ compatible = "mediatek,mt7531";
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+ reg = <31>;
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+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ phy-handle = <&swphy0>;
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+ label = "lan4";
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ phy-handle = <&swphy1>;
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+ label = "lan3";
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ phy-handle = <&swphy2>;
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+ label = "lan2";
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ phy-handle = <&swphy3>;
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+ label = "lan1";
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+ };
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+
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+ port@6 {
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+ reg = <6>;
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+ label = "cpu";
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+ ethernet = <&gmac0>;
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+ phy-mode = "2500base-x";
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+
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+ };
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ swphy0: phy@0 {
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+ reg = <0>;
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+
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+ mediatek,led-config = <
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+ 0x21 0x8009 /* BASIC_CTRL */
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+ 0x22 0x0c00 /* ON_DURATION */
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+ 0x23 0x1400 /* BLINK_DURATION */
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+ 0x24 0xc001 /* LED0_ON_CTRL */
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+ 0x25 0x0003 /* LED0_BLINK_CTRL */
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+ 0x26 0xc006 /* LED1_ON_CTRL */
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+ 0x27 0x003c /* LED1_BLINK_CTRL */
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+ >;
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+ };
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+
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+ swphy1: phy@1 {
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+ reg = <1>;
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+ };
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+
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+ swphy2: phy@2 {
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+ reg = <2>;
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+ };
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+
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+ swphy3: phy@3 {
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+ reg = <3>;
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+ };
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+ };
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+ };
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+};
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+
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+&spi0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi0_flash_pins>;
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+ status = "okay";
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+
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+ spi_nand@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "spi-nand";
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+ reg = <0>;
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+
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+ spi-max-frequency = <52000000>;
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+ spi-tx-buswidth = <4>;
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+ spi-rx-buswidth = <4>;
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+
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+ mediatek,nmbm;
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+ mediatek,bmt-max-ratio = <1>;
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+ mediatek,bmt-max-reserved-blocks = <64>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "rutos-a";
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+ reg = <0x00000000 0x10000000>;
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+ };
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+
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+ partition@10000000 {
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+ label = "rutos-b";
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+ reg = <0x10000000 0x10000000>;
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+ };
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|
|
|
|
+ };
|
|
|
|
|
+ };
|
|
|
|
|
+};
|
|
|
|
|
+
|
|
|
|
|
+&spi1 {
|
|
|
|
|
+ pinctrl-names = "default";
|
|
|
|
|
+ pinctrl-0 = <&spic_pins>;
|
|
|
|
|
+ status = "okay";
|
|
|
|
|
+
|
|
|
|
|
+ gpio_hc595: gpio_hc595@0 {
|
|
|
|
|
+ compatible = "fairchild,74hc595";
|
|
|
|
|
+ reg = <0>;
|
|
|
|
|
+ gpio-controller;
|
|
|
|
|
+ #gpio-cells = <2>;
|
|
|
|
|
+ registers-number = <1>;
|
|
|
|
|
+ spi-max-frequency = <10000000>;
|
|
|
|
|
+ enable-gpios = <&pio 4 GPIO_ACTIVE_LOW>;
|
|
|
|
|
+ };
|
|
|
|
|
+};
|
|
|
|
|
+
|
|
|
|
|
+&spi2 {
|
|
|
|
|
+ pinctrl-names = "default";
|
|
|
|
|
+ pinctrl-0 = <&spi2_flash_pins>;
|
|
|
|
|
+ status = "okay";
|
|
|
|
|
+
|
|
|
|
|
+ flash@0 {
|
|
|
|
|
+ #address-cells = <1>;
|
|
|
|
|
+ #size-cells = <1>;
|
|
|
|
|
+ compatible = "jedec,spi-nor";
|
|
|
|
|
+ reg = <0>;
|
|
|
|
|
+
|
|
|
|
|
+ spi-max-frequency = <4000000>;
|
|
|
|
|
+ spi-tx-buswidth = <4>;
|
|
|
|
|
+ spi-rx-buswidth = <4>;
|
|
|
|
|
+
|
|
|
|
|
+ partitions {
|
|
|
|
|
+ compatible = "fixed-partitions";
|
|
|
|
|
+ #address-cells = <1>;
|
|
|
|
|
+ #size-cells = <1>;
|
|
|
|
|
+
|
|
|
|
|
+ partition@00000 {
|
|
|
|
|
+ label = "bl2";
|
|
|
|
|
+ reg = <0x00000 0x0040000>;
|
|
|
|
|
+ read-only;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ partition@40000 {
|
|
|
|
|
+ label = "u-boot-env";
|
|
|
|
|
+ reg = <0x40000 0x0010000>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ factory: partition@50000 {
|
|
|
|
|
+ label = "factory";
|
|
|
|
|
+ reg = <0x50000 0x00A0000>;
|
|
|
|
|
+ read-only;
|
|
|
|
|
+
|
|
|
|
|
+ nvmem-layout {
|
|
|
|
|
+ compatible = "fixed-layout";
|
|
|
|
|
+ #address-cells = <1>;
|
|
|
|
|
+ #size-cells = <1>;
|
|
|
|
|
+
|
|
|
|
|
+ eeprom_factory_0: eeprom@0 {
|
|
|
|
|
+ reg = <0x0 0x1000>;
|
|
|
|
|
+ };
|
|
|
|
|
+ };
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ config: partition@f0000 {
|
|
|
|
|
+ compatible = "nvmem-cells";
|
|
|
|
|
+ #address-cells = <1>;
|
|
|
|
|
+ #size-cells = <1>;
|
|
|
|
|
+
|
|
|
|
|
+ label = "config";
|
|
|
|
|
+ reg = <0xF0000 0x0010000>;
|
|
|
|
|
+ read-only;
|
|
|
|
|
+
|
|
|
|
|
+ nvmem-layout {
|
|
|
|
|
+ compatible = "fixed-layout";
|
|
|
|
|
+ #address-cells = <1>;
|
|
|
|
|
+ #size-cells = <1>;
|
|
|
|
|
+
|
|
|
|
|
+ macaddr_config_0: macaddr@0 {
|
|
|
|
|
+ compatible = "mac-base";
|
|
|
|
|
+ reg = <0x0 0x6>;
|
|
|
|
|
+ #nvmem-cell-cells = <1>;
|
|
|
|
|
+ };
|
|
|
|
|
+ };
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ boot: partition@100000 {
|
|
|
|
|
+ label = "fip";
|
|
|
|
|
+ reg = <0x100000 0x0100000>;
|
|
|
|
|
+ read-only;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ partition@200000 {
|
|
|
|
|
+ label = "bootconfig-a";
|
|
|
|
|
+ reg = <0x200000 0x010000>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ partition@210000 {
|
|
|
|
|
+ label = "bootconfig-b";
|
|
|
|
|
+ reg = <0x210000 0x010000>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ partition@220000 {
|
|
|
|
|
+ label = "event-log";
|
|
|
|
|
+ reg = <0x220000 0x090000>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ partition@2B0000 {
|
|
|
|
|
+ label = "recovery";
|
|
|
|
|
+ reg = <0x2B0000 0xD50000>;
|
|
|
|
|
+ };
|
|
|
|
|
+ };
|
|
|
|
|
+ };
|
|
|
|
|
+};
|
|
|
|
|
+
|
|
|
|
|
+&pio {
|
|
|
|
|
+ spi0_flash_pins: spi0-pins {
|
|
|
|
|
+ mux {
|
|
|
|
|
+ function = "spi";
|
|
|
|
|
+ groups = "spi0", "spi0_wp_hold";
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ conf-pu {
|
|
|
|
|
+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
|
|
|
|
|
+ drive-strength = <MTK_DRIVE_4mA>;
|
|
|
|
|
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ conf-pd {
|
|
|
|
|
+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
|
|
|
|
|
+ drive-strength = <MTK_DRIVE_4mA>;
|
|
|
|
|
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
|
|
|
|
|
+ };
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ spic_pins: spi1-pins {
|
|
|
|
|
+ mux {
|
|
|
|
|
+ function = "spi";
|
|
|
|
|
+ groups = "spi1_1";
|
|
|
|
|
+ };
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ spi2_flash_pins: spi2-pins {
|
|
|
|
|
+ mux {
|
|
|
|
|
+ function = "spi";
|
|
|
|
|
+ groups = "spi2", "spi2_wp_hold";
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ conf-pu {
|
|
|
|
|
+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
|
|
|
|
|
+ drive-strength = <MTK_DRIVE_8mA>;
|
|
|
|
|
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ conf-pd {
|
|
|
|
|
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
|
|
|
|
|
+ drive-strength = <MTK_DRIVE_8mA>;
|
|
|
|
|
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
|
|
|
|
|
+ };
|
|
|
|
|
+ };
|
|
|
|
|
+};
|
|
|
|
|
+
|
|
|
|
|
+&uart0 {
|
|
|
|
|
+ status = "okay";
|
|
|
|
|
+};
|
|
|
|
|
+
|
|
|
|
|
+&watchdog {
|
|
|
|
|
+ status = "okay";
|
|
|
|
|
+};
|
|
|
|
|
+
|
|
|
|
|
+&usb_phy {
|
|
|
|
|
+ status = "okay";
|
|
|
|
|
+};
|
|
|
|
|
+
|
|
|
|
|
+&xhci {
|
|
|
|
|
+ status = "okay";
|
|
|
|
|
+};
|
|
|
|
|
+
|
|
|
|
|
+&wifi {
|
|
|
|
|
+ #address-cells = <1>;
|
|
|
|
|
+ #size-cells = <0>;
|
|
|
|
|
+
|
|
|
|
|
+ status = "okay";
|
|
|
|
|
+ nvmem-cells = <&eeprom_factory_0>;
|
|
|
|
|
+ nvmem-cell-names = "eeprom";
|
|
|
|
|
+
|
|
|
|
|
+ band@0 {
|
|
|
|
|
+ reg = <0>;
|
|
|
|
|
+ nvmem-cells = <&macaddr_config_0 2>;
|
|
|
|
|
+ nvmem-cell-names = "mac-address";
|
|
|
|
|
+ };
|
|
|
|
|
+
|
|
|
|
|
+ band@1 {
|
|
|
|
|
+ reg = <1>;
|
|
|
|
|
+ nvmem-cells = <&macaddr_config_0 3>;
|
|
|
|
|
+ nvmem-cell-names = "mac-address";
|
|
|
|
|
+ };
|
|
|
|
|
+};
|