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@@ -0,0 +1,14208 @@
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+From def88eb4d8365a4aa064d28405d03550a9d0a3be Mon Sep 17 00:00:00 2001
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+From: Dragan Simic <[email protected]>
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+Date: Sun, 9 Jun 2024 10:58:19 +0200
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+Subject: [PATCH] arm64: dts: rockchip: Prepare RK3588 SoC dtsi files for
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+ per-variant OPPs
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+
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+Rename the Rockchip RK3588 SoC dtsi files and, consequently, adjust their
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+contents appropriately, to prepare them for the ability to specify different
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+CPU and GPU OPPs for each of the supported RK3588 SoC variants.
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+
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+As already discussed, [1][2][3][4] some of the RK3588 SoC variants require
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+different OPPs, and it makes more sense to have the OPPs already defined when
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+a board dts(i) file includes one of the SoC variant dtsi files (rk3588.dtsi,
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+rk3588j.dtsi or rk3588s.dtsi), rather than requiring the board dts(i) file
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+to also include a separate rk3588*-opp.dtsi file. The choice of the SoC
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+variant is already made by the inclusion of the SoC dtsi file into the board
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+dts(i) file, and it doesn't make much sense to, effectively, allow the board
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+dts(i) file to include and use an incompatible set of OPPs for the already
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+selected RK3588 SoC variant.
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+
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+The new naming scheme for the RK3588 SoC dtsi files uses "-base" and "-extra"
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+suffixes to denote the DT data shared between all RK5588 SoC variants, and
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+the DT data shared between the unrestricted SoC variants, respectively.
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+For example, the DT data for the RK3588 includes both rk3588-base.dtsi and
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+rk3588-extra.dtsi, because it's an unrestricted SoC variant, while the DT
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+data for the RK3588S variant includes rk3588-base.dtsi only, because it's
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+a restricted SoC variant, feature- and interface-wise. This achieves a more
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+logical naming of the RK3588 SoC dtsi files, which reflects the way DT data
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+for the SoC variants is built by "stacking" the SoC variant features made
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+available through the "-base" and "-extra" SoC dtsi files. Additionally,
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+the SoC variant dtsi files (rk3588.dtsi, rk3588j.dtsi and rk3588s.dtsi) are
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+no longer parents to any other SoC variant dtsi files, which should help with
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+making the new "stacking" approach cleaner and easier to follow.
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+
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+The RK3588 pinctrl dtsi files are also renamed in the same way, for the sake
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+of consistency. This also keeps the "-base" and "-extra" groups of the dtsi
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+files together when looked at in a directory listing, which is helpful.
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+
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+The per-SoC-variant OPPs should go directly into the SoC dtsi files, if no
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+more than one SoC variant uses those OPPs, or be put into a separate "-opp"
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+dtsi file that's shared between and included from two or more SoC variant
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+dtsi files. An example for the former is the non-shared OPP data that should
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+go directly into the RK3588J SoC variant dtsi file (i.e. rk3588j.dtsi), and
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+an example for the latter is the shared OPP data that should be put into
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+rk3588-opp.dtsi and be included from the RK3588 and RK3588S SoC variant dtsi
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+files (i.e. rk3588.dtsi and rk3588s.dtsi, respectively). Consequently, if
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+the OPPs for the RK3588 and RK3588S SoC variants are ever made different,
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+the shared rk3588-opp.dtsi file should be deleted and the new OPPs should
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+be put directly into rk3588.dtsi and rk3588s.dtsi. [4]
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+
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+No functional changes are introduced, which was validated by decompiling and
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+comparing all affected dtb files before and after these changes.
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+
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+As a side note, due to the nature of introduced changes, this commit is best
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+viewed using the --break-rewrites option for git-log(1).
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+
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+[1] https://lore.kernel.org/linux-rockchip/[email protected]/
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+[2] https://lore.kernel.org/linux-rockchip/CABjd4Yxi=+3gkNnH3BysUzzYsji-=-yROtzEc8jM_g0roKB0-w@mail.gmail.com/
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+[3] https://lore.kernel.org/linux-rockchip/[email protected]/
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+[4] https://lore.kernel.org/linux-rockchip/673dcf47596e7bc8ba065034e339bb1bbf9cdcb0.1716948159.git.dsimic@manjaro.org/T/#u
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+
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+Signed-off-by: Dragan Simic <[email protected]>
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+Link: https://lore.kernel.org/r/9ffedc0e2ca7f167d9d795b2a8f43cb9f56a653b.1717923308.git.dsimic@manjaro.org
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+Signed-off-by: Heiko Stuebner <[email protected]>
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+---
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+ ...-pinctrl.dtsi => rk3588-base-pinctrl.dtsi} | 0
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+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2670 +++++++++++++++++
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+ ...pinctrl.dtsi => rk3588-extra-pinctrl.dtsi} | 0
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+ .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 413 +++
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+ arch/arm64/boot/dts/rockchip/rk3588.dtsi | 412 +--
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+ arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 2 +-
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+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2669 +---------------
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+ 7 files changed, 3090 insertions(+), 3076 deletions(-)
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+ rename arch/arm64/boot/dts/rockchip/{rk3588s-pinctrl.dtsi => rk3588-base-pinctrl.dtsi} (100%)
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+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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+ rename arch/arm64/boot/dts/rockchip/{rk3588-pinctrl.dtsi => rk3588-extra-pinctrl.dtsi} (100%)
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+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
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+
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+--- /dev/null
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++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
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+@@ -0,0 +1,2670 @@
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++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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++/*
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++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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++ */
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++
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++#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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++#include <dt-bindings/interrupt-controller/arm-gic.h>
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++#include <dt-bindings/interrupt-controller/irq.h>
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++#include <dt-bindings/power/rk3588-power.h>
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++#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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++#include <dt-bindings/phy/phy.h>
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++#include <dt-bindings/ata/ahci.h>
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++
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++/ {
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++ compatible = "rockchip,rk3588";
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++
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++ interrupt-parent = <&gic>;
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++ #address-cells = <2>;
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++ #size-cells = <2>;
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++
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++ aliases {
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++ gpio0 = &gpio0;
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++ gpio1 = &gpio1;
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++ gpio2 = &gpio2;
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++ gpio3 = &gpio3;
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++ gpio4 = &gpio4;
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++ i2c0 = &i2c0;
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++ i2c1 = &i2c1;
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++ i2c2 = &i2c2;
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++ i2c3 = &i2c3;
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++ i2c4 = &i2c4;
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++ i2c5 = &i2c5;
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++ i2c6 = &i2c6;
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++ i2c7 = &i2c7;
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++ i2c8 = &i2c8;
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++ serial0 = &uart0;
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++ serial1 = &uart1;
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++ serial2 = &uart2;
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++ serial3 = &uart3;
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++ serial4 = &uart4;
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++ serial5 = &uart5;
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++ serial6 = &uart6;
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++ serial7 = &uart7;
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++ serial8 = &uart8;
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++ serial9 = &uart9;
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++ spi0 = &spi0;
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++ spi1 = &spi1;
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++ spi2 = &spi2;
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++ spi3 = &spi3;
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++ spi4 = &spi4;
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++ };
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++
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++ cpus {
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ cpu-map {
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++ cluster0 {
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++ core0 {
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++ cpu = <&cpu_l0>;
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++ };
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++ core1 {
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++ cpu = <&cpu_l1>;
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++ };
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++ core2 {
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++ cpu = <&cpu_l2>;
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++ };
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++ core3 {
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++ cpu = <&cpu_l3>;
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++ };
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++ };
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++ cluster1 {
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++ core0 {
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++ cpu = <&cpu_b0>;
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++ };
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++ core1 {
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++ cpu = <&cpu_b1>;
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++ };
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++ };
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++ cluster2 {
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++ core0 {
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++ cpu = <&cpu_b2>;
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++ };
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++ core1 {
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++ cpu = <&cpu_b3>;
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++ };
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++ };
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++ };
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++
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++ cpu_l0: cpu@0 {
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++ device_type = "cpu";
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++ compatible = "arm,cortex-a55";
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++ reg = <0x0>;
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++ enable-method = "psci";
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++ capacity-dmips-mhz = <530>;
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++ clocks = <&scmi_clk SCMI_CLK_CPUL>;
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++ assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
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++ assigned-clock-rates = <816000000>;
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++ cpu-idle-states = <&CPU_SLEEP>;
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++ i-cache-size = <32768>;
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++ i-cache-line-size = <64>;
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++ i-cache-sets = <128>;
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++ d-cache-size = <32768>;
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++ d-cache-line-size = <64>;
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++ d-cache-sets = <128>;
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++ next-level-cache = <&l2_cache_l0>;
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++ dynamic-power-coefficient = <228>;
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++ #cooling-cells = <2>;
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++ };
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++
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++ cpu_l1: cpu@100 {
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++ device_type = "cpu";
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++ compatible = "arm,cortex-a55";
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++ reg = <0x100>;
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++ enable-method = "psci";
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++ capacity-dmips-mhz = <530>;
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++ clocks = <&scmi_clk SCMI_CLK_CPUL>;
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++ cpu-idle-states = <&CPU_SLEEP>;
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++ i-cache-size = <32768>;
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++ i-cache-line-size = <64>;
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++ i-cache-sets = <128>;
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++ d-cache-size = <32768>;
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++ d-cache-line-size = <64>;
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++ d-cache-sets = <128>;
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++ next-level-cache = <&l2_cache_l1>;
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++ dynamic-power-coefficient = <228>;
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++ #cooling-cells = <2>;
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++ };
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++
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++ cpu_l2: cpu@200 {
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++ device_type = "cpu";
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++ compatible = "arm,cortex-a55";
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++ reg = <0x200>;
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++ enable-method = "psci";
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++ capacity-dmips-mhz = <530>;
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++ clocks = <&scmi_clk SCMI_CLK_CPUL>;
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++ cpu-idle-states = <&CPU_SLEEP>;
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++ i-cache-size = <32768>;
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++ i-cache-line-size = <64>;
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++ i-cache-sets = <128>;
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++ d-cache-size = <32768>;
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++ d-cache-line-size = <64>;
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++ d-cache-sets = <128>;
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++ next-level-cache = <&l2_cache_l2>;
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++ dynamic-power-coefficient = <228>;
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++ #cooling-cells = <2>;
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++ };
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++
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++ cpu_l3: cpu@300 {
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++ device_type = "cpu";
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++ compatible = "arm,cortex-a55";
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++ reg = <0x300>;
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++ enable-method = "psci";
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++ capacity-dmips-mhz = <530>;
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++ clocks = <&scmi_clk SCMI_CLK_CPUL>;
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++ cpu-idle-states = <&CPU_SLEEP>;
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++ i-cache-size = <32768>;
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++ i-cache-line-size = <64>;
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++ i-cache-sets = <128>;
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++ d-cache-size = <32768>;
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++ d-cache-line-size = <64>;
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++ d-cache-sets = <128>;
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++ next-level-cache = <&l2_cache_l3>;
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++ dynamic-power-coefficient = <228>;
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++ #cooling-cells = <2>;
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++ };
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++
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++ cpu_b0: cpu@400 {
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++ device_type = "cpu";
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++ compatible = "arm,cortex-a76";
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++ reg = <0x400>;
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++ enable-method = "psci";
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++ capacity-dmips-mhz = <1024>;
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++ clocks = <&scmi_clk SCMI_CLK_CPUB01>;
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++ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
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++ assigned-clock-rates = <816000000>;
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++ cpu-idle-states = <&CPU_SLEEP>;
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++ i-cache-size = <65536>;
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++ i-cache-line-size = <64>;
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++ i-cache-sets = <256>;
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++ d-cache-size = <65536>;
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++ d-cache-line-size = <64>;
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++ d-cache-sets = <256>;
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++ next-level-cache = <&l2_cache_b0>;
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++ dynamic-power-coefficient = <416>;
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++ #cooling-cells = <2>;
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++ };
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++
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++ cpu_b1: cpu@500 {
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++ device_type = "cpu";
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++ compatible = "arm,cortex-a76";
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++ reg = <0x500>;
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++ enable-method = "psci";
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++ capacity-dmips-mhz = <1024>;
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++ clocks = <&scmi_clk SCMI_CLK_CPUB01>;
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++ cpu-idle-states = <&CPU_SLEEP>;
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++ i-cache-size = <65536>;
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++ i-cache-line-size = <64>;
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++ i-cache-sets = <256>;
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++ d-cache-size = <65536>;
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++ d-cache-line-size = <64>;
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++ d-cache-sets = <256>;
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++ next-level-cache = <&l2_cache_b1>;
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++ dynamic-power-coefficient = <416>;
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++ #cooling-cells = <2>;
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++ };
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++
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++ cpu_b2: cpu@600 {
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++ device_type = "cpu";
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++ compatible = "arm,cortex-a76";
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++ reg = <0x600>;
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++ enable-method = "psci";
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++ capacity-dmips-mhz = <1024>;
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++ clocks = <&scmi_clk SCMI_CLK_CPUB23>;
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++ assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
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++ assigned-clock-rates = <816000000>;
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++ cpu-idle-states = <&CPU_SLEEP>;
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++ i-cache-size = <65536>;
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++ i-cache-line-size = <64>;
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++ i-cache-sets = <256>;
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++ d-cache-size = <65536>;
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++ d-cache-line-size = <64>;
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++ d-cache-sets = <256>;
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++ next-level-cache = <&l2_cache_b2>;
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++ dynamic-power-coefficient = <416>;
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++ #cooling-cells = <2>;
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++ };
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++
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++ cpu_b3: cpu@700 {
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++ device_type = "cpu";
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++ compatible = "arm,cortex-a76";
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++ reg = <0x700>;
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++ enable-method = "psci";
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++ capacity-dmips-mhz = <1024>;
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++ clocks = <&scmi_clk SCMI_CLK_CPUB23>;
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++ cpu-idle-states = <&CPU_SLEEP>;
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++ i-cache-size = <65536>;
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++ i-cache-line-size = <64>;
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++ i-cache-sets = <256>;
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++ d-cache-size = <65536>;
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++ d-cache-line-size = <64>;
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++ d-cache-sets = <256>;
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++ next-level-cache = <&l2_cache_b3>;
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++ dynamic-power-coefficient = <416>;
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++ #cooling-cells = <2>;
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++ };
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++
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++ idle-states {
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++ entry-method = "psci";
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++ CPU_SLEEP: cpu-sleep {
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++ compatible = "arm,idle-state";
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++ local-timer-stop;
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++ arm,psci-suspend-param = <0x0010000>;
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++ entry-latency-us = <100>;
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++ exit-latency-us = <120>;
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++ min-residency-us = <1000>;
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++ };
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++ };
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++
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++ l2_cache_l0: l2-cache-l0 {
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++ compatible = "cache";
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++ cache-size = <131072>;
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++ cache-line-size = <64>;
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++ cache-sets = <512>;
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++ cache-level = <2>;
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++ cache-unified;
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++ next-level-cache = <&l3_cache>;
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++ };
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++
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++ l2_cache_l1: l2-cache-l1 {
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++ compatible = "cache";
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|
|
++ cache-size = <131072>;
|
|
|
++ cache-line-size = <64>;
|
|
|
++ cache-sets = <512>;
|
|
|
++ cache-level = <2>;
|
|
|
++ cache-unified;
|
|
|
++ next-level-cache = <&l3_cache>;
|
|
|
++ };
|
|
|
++
|
|
|
++ l2_cache_l2: l2-cache-l2 {
|
|
|
++ compatible = "cache";
|
|
|
++ cache-size = <131072>;
|
|
|
++ cache-line-size = <64>;
|
|
|
++ cache-sets = <512>;
|
|
|
++ cache-level = <2>;
|
|
|
++ cache-unified;
|
|
|
++ next-level-cache = <&l3_cache>;
|
|
|
++ };
|
|
|
++
|
|
|
++ l2_cache_l3: l2-cache-l3 {
|
|
|
++ compatible = "cache";
|
|
|
++ cache-size = <131072>;
|
|
|
++ cache-line-size = <64>;
|
|
|
++ cache-sets = <512>;
|
|
|
++ cache-level = <2>;
|
|
|
++ cache-unified;
|
|
|
++ next-level-cache = <&l3_cache>;
|
|
|
++ };
|
|
|
++
|
|
|
++ l2_cache_b0: l2-cache-b0 {
|
|
|
++ compatible = "cache";
|
|
|
++ cache-size = <524288>;
|
|
|
++ cache-line-size = <64>;
|
|
|
++ cache-sets = <1024>;
|
|
|
++ cache-level = <2>;
|
|
|
++ cache-unified;
|
|
|
++ next-level-cache = <&l3_cache>;
|
|
|
++ };
|
|
|
++
|
|
|
++ l2_cache_b1: l2-cache-b1 {
|
|
|
++ compatible = "cache";
|
|
|
++ cache-size = <524288>;
|
|
|
++ cache-line-size = <64>;
|
|
|
++ cache-sets = <1024>;
|
|
|
++ cache-level = <2>;
|
|
|
++ cache-unified;
|
|
|
++ next-level-cache = <&l3_cache>;
|
|
|
++ };
|
|
|
++
|
|
|
++ l2_cache_b2: l2-cache-b2 {
|
|
|
++ compatible = "cache";
|
|
|
++ cache-size = <524288>;
|
|
|
++ cache-line-size = <64>;
|
|
|
++ cache-sets = <1024>;
|
|
|
++ cache-level = <2>;
|
|
|
++ cache-unified;
|
|
|
++ next-level-cache = <&l3_cache>;
|
|
|
++ };
|
|
|
++
|
|
|
++ l2_cache_b3: l2-cache-b3 {
|
|
|
++ compatible = "cache";
|
|
|
++ cache-size = <524288>;
|
|
|
++ cache-line-size = <64>;
|
|
|
++ cache-sets = <1024>;
|
|
|
++ cache-level = <2>;
|
|
|
++ cache-unified;
|
|
|
++ next-level-cache = <&l3_cache>;
|
|
|
++ };
|
|
|
++
|
|
|
++ l3_cache: l3-cache {
|
|
|
++ compatible = "cache";
|
|
|
++ cache-size = <3145728>;
|
|
|
++ cache-line-size = <64>;
|
|
|
++ cache-sets = <4096>;
|
|
|
++ cache-level = <3>;
|
|
|
++ cache-unified;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ display_subsystem: display-subsystem {
|
|
|
++ compatible = "rockchip,display-subsystem";
|
|
|
++ ports = <&vop_out>;
|
|
|
++ };
|
|
|
++
|
|
|
++ firmware {
|
|
|
++ optee: optee {
|
|
|
++ compatible = "linaro,optee-tz";
|
|
|
++ method = "smc";
|
|
|
++ };
|
|
|
++
|
|
|
++ scmi: scmi {
|
|
|
++ compatible = "arm,scmi-smc";
|
|
|
++ arm,smc-id = <0x82000010>;
|
|
|
++ shmem = <&scmi_shmem>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++
|
|
|
++ scmi_clk: protocol@14 {
|
|
|
++ reg = <0x14>;
|
|
|
++ #clock-cells = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ scmi_reset: protocol@16 {
|
|
|
++ reg = <0x16>;
|
|
|
++ #reset-cells = <1>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pmu-a55 {
|
|
|
++ compatible = "arm,cortex-a55-pmu";
|
|
|
++ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
|
|
|
++ };
|
|
|
++
|
|
|
++ pmu-a76 {
|
|
|
++ compatible = "arm,cortex-a76-pmu";
|
|
|
++ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ psci {
|
|
|
++ compatible = "arm,psci-1.0";
|
|
|
++ method = "smc";
|
|
|
++ };
|
|
|
++
|
|
|
++ spll: clock-0 {
|
|
|
++ compatible = "fixed-clock";
|
|
|
++ clock-frequency = <702000000>;
|
|
|
++ clock-output-names = "spll";
|
|
|
++ #clock-cells = <0>;
|
|
|
++ };
|
|
|
++
|
|
|
++ timer {
|
|
|
++ compatible = "arm,armv8-timer";
|
|
|
++ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
|
|
|
++ };
|
|
|
++
|
|
|
++ xin24m: clock-1 {
|
|
|
++ compatible = "fixed-clock";
|
|
|
++ clock-frequency = <24000000>;
|
|
|
++ clock-output-names = "xin24m";
|
|
|
++ #clock-cells = <0>;
|
|
|
++ };
|
|
|
++
|
|
|
++ xin32k: clock-2 {
|
|
|
++ compatible = "fixed-clock";
|
|
|
++ clock-frequency = <32768>;
|
|
|
++ clock-output-names = "xin32k";
|
|
|
++ #clock-cells = <0>;
|
|
|
++ };
|
|
|
++
|
|
|
++ pmu_sram: sram@10f000 {
|
|
|
++ compatible = "mmio-sram";
|
|
|
++ reg = <0x0 0x0010f000 0x0 0x100>;
|
|
|
++ ranges = <0 0x0 0x0010f000 0x100>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <1>;
|
|
|
++
|
|
|
++ scmi_shmem: sram@0 {
|
|
|
++ compatible = "arm,scmi-shmem";
|
|
|
++ reg = <0x0 0x100>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ gpu: gpu@fb000000 {
|
|
|
++ compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
|
|
|
++ reg = <0x0 0xfb000000 0x0 0x200000>;
|
|
|
++ #cooling-cells = <2>;
|
|
|
++ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
|
|
|
++ assigned-clock-rates = <200000000>;
|
|
|
++ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
|
|
|
++ <&cru CLK_GPU_STACKS>;
|
|
|
++ clock-names = "core", "coregroup", "stacks";
|
|
|
++ dynamic-power-coefficient = <2982>;
|
|
|
++ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "job", "mmu", "gpu";
|
|
|
++ operating-points-v2 = <&gpu_opp_table>;
|
|
|
++ power-domains = <&power RK3588_PD_GPU>;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ gpu_opp_table: opp-table {
|
|
|
++ compatible = "operating-points-v2";
|
|
|
++
|
|
|
++ opp-300000000 {
|
|
|
++ opp-hz = /bits/ 64 <300000000>;
|
|
|
++ opp-microvolt = <675000 675000 850000>;
|
|
|
++ };
|
|
|
++ opp-400000000 {
|
|
|
++ opp-hz = /bits/ 64 <400000000>;
|
|
|
++ opp-microvolt = <675000 675000 850000>;
|
|
|
++ };
|
|
|
++ opp-500000000 {
|
|
|
++ opp-hz = /bits/ 64 <500000000>;
|
|
|
++ opp-microvolt = <675000 675000 850000>;
|
|
|
++ };
|
|
|
++ opp-600000000 {
|
|
|
++ opp-hz = /bits/ 64 <600000000>;
|
|
|
++ opp-microvolt = <675000 675000 850000>;
|
|
|
++ };
|
|
|
++ opp-700000000 {
|
|
|
++ opp-hz = /bits/ 64 <700000000>;
|
|
|
++ opp-microvolt = <700000 700000 850000>;
|
|
|
++ };
|
|
|
++ opp-800000000 {
|
|
|
++ opp-hz = /bits/ 64 <800000000>;
|
|
|
++ opp-microvolt = <750000 750000 850000>;
|
|
|
++ };
|
|
|
++ opp-900000000 {
|
|
|
++ opp-hz = /bits/ 64 <900000000>;
|
|
|
++ opp-microvolt = <800000 800000 850000>;
|
|
|
++ };
|
|
|
++ opp-1000000000 {
|
|
|
++ opp-hz = /bits/ 64 <1000000000>;
|
|
|
++ opp-microvolt = <850000 850000 850000>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ usb_host0_xhci: usb@fc000000 {
|
|
|
++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
|
|
++ reg = <0x0 0xfc000000 0x0 0x400000>;
|
|
|
++ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
|
|
|
++ <&cru ACLK_USB3OTG0>;
|
|
|
++ clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
|
|
++ dr_mode = "otg";
|
|
|
++ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
|
|
|
++ phy-names = "usb2-phy", "usb3-phy";
|
|
|
++ phy_type = "utmi_wide";
|
|
|
++ power-domains = <&power RK3588_PD_USB>;
|
|
|
++ resets = <&cru SRST_A_USB3OTG0>;
|
|
|
++ snps,dis_enblslpm_quirk;
|
|
|
++ snps,dis-u1-entry-quirk;
|
|
|
++ snps,dis-u2-entry-quirk;
|
|
|
++ snps,dis-u2-freeclk-exists-quirk;
|
|
|
++ snps,dis-del-phy-power-chg-quirk;
|
|
|
++ snps,dis-tx-ipgap-linecheck-quirk;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ usb_host0_ehci: usb@fc800000 {
|
|
|
++ compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
|
|
++ reg = <0x0 0xfc800000 0x0 0x40000>;
|
|
|
++ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
|
|
|
++ phys = <&u2phy2_host>;
|
|
|
++ phy-names = "usb";
|
|
|
++ power-domains = <&power RK3588_PD_USB>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ usb_host0_ohci: usb@fc840000 {
|
|
|
++ compatible = "rockchip,rk3588-ohci", "generic-ohci";
|
|
|
++ reg = <0x0 0xfc840000 0x0 0x40000>;
|
|
|
++ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
|
|
|
++ phys = <&u2phy2_host>;
|
|
|
++ phy-names = "usb";
|
|
|
++ power-domains = <&power RK3588_PD_USB>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ usb_host1_ehci: usb@fc880000 {
|
|
|
++ compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
|
|
++ reg = <0x0 0xfc880000 0x0 0x40000>;
|
|
|
++ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
|
|
|
++ phys = <&u2phy3_host>;
|
|
|
++ phy-names = "usb";
|
|
|
++ power-domains = <&power RK3588_PD_USB>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ usb_host1_ohci: usb@fc8c0000 {
|
|
|
++ compatible = "rockchip,rk3588-ohci", "generic-ohci";
|
|
|
++ reg = <0x0 0xfc8c0000 0x0 0x40000>;
|
|
|
++ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
|
|
|
++ phys = <&u2phy3_host>;
|
|
|
++ phy-names = "usb";
|
|
|
++ power-domains = <&power RK3588_PD_USB>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ usb_host2_xhci: usb@fcd00000 {
|
|
|
++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
|
|
++ reg = <0x0 0xfcd00000 0x0 0x400000>;
|
|
|
++ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
|
|
|
++ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
|
|
|
++ <&cru CLK_PIPEPHY2_PIPE_U3_G>;
|
|
|
++ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
|
|
|
++ dr_mode = "host";
|
|
|
++ phys = <&combphy2_psu PHY_TYPE_USB3>;
|
|
|
++ phy-names = "usb3-phy";
|
|
|
++ phy_type = "utmi_wide";
|
|
|
++ resets = <&cru SRST_A_USB3OTG2>;
|
|
|
++ snps,dis_enblslpm_quirk;
|
|
|
++ snps,dis-u2-freeclk-exists-quirk;
|
|
|
++ snps,dis-del-phy-power-chg-quirk;
|
|
|
++ snps,dis-tx-ipgap-linecheck-quirk;
|
|
|
++ snps,dis_rxdet_inp3_quirk;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ mmu600_pcie: iommu@fc900000 {
|
|
|
++ compatible = "arm,smmu-v3";
|
|
|
++ reg = <0x0 0xfc900000 0x0 0x200000>;
|
|
|
++ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
|
|
++ #iommu-cells = <1>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ mmu600_php: iommu@fcb00000 {
|
|
|
++ compatible = "arm,smmu-v3";
|
|
|
++ reg = <0x0 0xfcb00000 0x0 0x200000>;
|
|
|
++ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
|
|
++ #iommu-cells = <1>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pmu1grf: syscon@fd58a000 {
|
|
|
++ compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
|
|
|
++ reg = <0x0 0xfd58a000 0x0 0x10000>;
|
|
|
++ };
|
|
|
++
|
|
|
++ sys_grf: syscon@fd58c000 {
|
|
|
++ compatible = "rockchip,rk3588-sys-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd58c000 0x0 0x1000>;
|
|
|
++ };
|
|
|
++
|
|
|
++ vop_grf: syscon@fd5a4000 {
|
|
|
++ compatible = "rockchip,rk3588-vop-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5a4000 0x0 0x2000>;
|
|
|
++ };
|
|
|
++
|
|
|
++ vo0_grf: syscon@fd5a6000 {
|
|
|
++ compatible = "rockchip,rk3588-vo-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5a6000 0x0 0x2000>;
|
|
|
++ clocks = <&cru PCLK_VO0GRF>;
|
|
|
++ };
|
|
|
++
|
|
|
++ vo1_grf: syscon@fd5a8000 {
|
|
|
++ compatible = "rockchip,rk3588-vo-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5a8000 0x0 0x100>;
|
|
|
++ clocks = <&cru PCLK_VO1GRF>;
|
|
|
++ };
|
|
|
++
|
|
|
++ usb_grf: syscon@fd5ac000 {
|
|
|
++ compatible = "rockchip,rk3588-usb-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5ac000 0x0 0x4000>;
|
|
|
++ };
|
|
|
++
|
|
|
++ php_grf: syscon@fd5b0000 {
|
|
|
++ compatible = "rockchip,rk3588-php-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5b0000 0x0 0x1000>;
|
|
|
++ };
|
|
|
++
|
|
|
++ pipe_phy0_grf: syscon@fd5bc000 {
|
|
|
++ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5bc000 0x0 0x100>;
|
|
|
++ };
|
|
|
++
|
|
|
++ pipe_phy2_grf: syscon@fd5c4000 {
|
|
|
++ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5c4000 0x0 0x100>;
|
|
|
++ };
|
|
|
++
|
|
|
++ usbdpphy0_grf: syscon@fd5c8000 {
|
|
|
++ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5c8000 0x0 0x4000>;
|
|
|
++ };
|
|
|
++
|
|
|
++ usb2phy0_grf: syscon@fd5d0000 {
|
|
|
++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
|
|
++ reg = <0x0 0xfd5d0000 0x0 0x4000>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <1>;
|
|
|
++
|
|
|
++ u2phy0: usb2phy@0 {
|
|
|
++ compatible = "rockchip,rk3588-usb2phy";
|
|
|
++ reg = <0x0 0x10>;
|
|
|
++ #clock-cells = <0>;
|
|
|
++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
|
|
++ clock-names = "phyclk";
|
|
|
++ clock-output-names = "usb480m_phy0";
|
|
|
++ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
|
|
|
++ reset-names = "phy", "apb";
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ u2phy0_otg: otg-port {
|
|
|
++ #phy-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ usb2phy2_grf: syscon@fd5d8000 {
|
|
|
++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
|
|
++ reg = <0x0 0xfd5d8000 0x0 0x4000>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <1>;
|
|
|
++
|
|
|
++ u2phy2: usb2phy@8000 {
|
|
|
++ compatible = "rockchip,rk3588-usb2phy";
|
|
|
++ reg = <0x8000 0x10>;
|
|
|
++ #clock-cells = <0>;
|
|
|
++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
|
|
++ clock-names = "phyclk";
|
|
|
++ clock-output-names = "usb480m_phy2";
|
|
|
++ interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
|
|
++ reset-names = "phy", "apb";
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ u2phy2_host: host-port {
|
|
|
++ #phy-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ usb2phy3_grf: syscon@fd5dc000 {
|
|
|
++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
|
|
++ reg = <0x0 0xfd5dc000 0x0 0x4000>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <1>;
|
|
|
++
|
|
|
++ u2phy3: usb2phy@c000 {
|
|
|
++ compatible = "rockchip,rk3588-usb2phy";
|
|
|
++ reg = <0xc000 0x10>;
|
|
|
++ #clock-cells = <0>;
|
|
|
++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
|
|
++ clock-names = "phyclk";
|
|
|
++ clock-output-names = "usb480m_phy3";
|
|
|
++ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
|
|
++ reset-names = "phy", "apb";
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ u2phy3_host: host-port {
|
|
|
++ #phy-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ hdptxphy0_grf: syscon@fd5e0000 {
|
|
|
++ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5e0000 0x0 0x100>;
|
|
|
++ };
|
|
|
++
|
|
|
++ ioc: syscon@fd5f0000 {
|
|
|
++ compatible = "rockchip,rk3588-ioc", "syscon";
|
|
|
++ reg = <0x0 0xfd5f0000 0x0 0x10000>;
|
|
|
++ };
|
|
|
++
|
|
|
++ system_sram1: sram@fd600000 {
|
|
|
++ compatible = "mmio-sram";
|
|
|
++ reg = <0x0 0xfd600000 0x0 0x100000>;
|
|
|
++ ranges = <0x0 0x0 0xfd600000 0x100000>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ cru: clock-controller@fd7c0000 {
|
|
|
++ compatible = "rockchip,rk3588-cru";
|
|
|
++ reg = <0x0 0xfd7c0000 0x0 0x5c000>;
|
|
|
++ assigned-clocks =
|
|
|
++ <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
|
|
|
++ <&cru PLL_NPLL>, <&cru PLL_GPLL>,
|
|
|
++ <&cru ACLK_CENTER_ROOT>,
|
|
|
++ <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
|
|
|
++ <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
|
|
|
++ <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
|
|
|
++ <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
|
|
|
++ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
|
|
|
++ <&cru CLK_GPU>;
|
|
|
++ assigned-clock-rates =
|
|
|
++ <1100000000>, <786432000>,
|
|
|
++ <850000000>, <1188000000>,
|
|
|
++ <702000000>,
|
|
|
++ <400000000>, <500000000>,
|
|
|
++ <800000000>, <100000000>,
|
|
|
++ <400000000>, <100000000>,
|
|
|
++ <200000000>, <500000000>,
|
|
|
++ <375000000>, <150000000>,
|
|
|
++ <200000000>;
|
|
|
++ rockchip,grf = <&php_grf>;
|
|
|
++ #clock-cells = <1>;
|
|
|
++ #reset-cells = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c0: i2c@fd880000 {
|
|
|
++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
++ reg = <0x0 0xfd880000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
|
|
|
++ clock-names = "i2c", "pclk";
|
|
|
++ pinctrl-0 = <&i2c0m0_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ uart0: serial@fd890000 {
|
|
|
++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
++ reg = <0x0 0xfd890000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
|
|
++ clock-names = "baudclk", "apb_pclk";
|
|
|
++ dmas = <&dmac0 6>, <&dmac0 7>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ pinctrl-0 = <&uart0m1_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ reg-shift = <2>;
|
|
|
++ reg-io-width = <4>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm0: pwm@fd8b0000 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfd8b0000 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm0m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm1: pwm@fd8b0010 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfd8b0010 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm1m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm2: pwm@fd8b0020 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfd8b0020 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm2m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm3: pwm@fd8b0030 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfd8b0030 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm3m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pmu: power-management@fd8d8000 {
|
|
|
++ compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
|
|
|
++ reg = <0x0 0xfd8d8000 0x0 0x400>;
|
|
|
++
|
|
|
++ power: power-controller {
|
|
|
++ compatible = "rockchip,rk3588-power-controller";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #power-domain-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "okay";
|
|
|
++
|
|
|
++ /* These power domains are grouped by VD_NPU */
|
|
|
++ power-domain@RK3588_PD_NPU {
|
|
|
++ reg = <RK3588_PD_NPU>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++
|
|
|
++ power-domain@RK3588_PD_NPUTOP {
|
|
|
++ reg = <RK3588_PD_NPUTOP>;
|
|
|
++ clocks = <&cru HCLK_NPU_ROOT>,
|
|
|
++ <&cru PCLK_NPU_ROOT>,
|
|
|
++ <&cru CLK_NPU_DSU0>,
|
|
|
++ <&cru HCLK_NPU_CM0_ROOT>;
|
|
|
++ pm_qos = <&qos_npu0_mwr>,
|
|
|
++ <&qos_npu0_mro>,
|
|
|
++ <&qos_mcu_npu>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++
|
|
|
++ power-domain@RK3588_PD_NPU1 {
|
|
|
++ reg = <RK3588_PD_NPU1>;
|
|
|
++ clocks = <&cru HCLK_NPU_ROOT>,
|
|
|
++ <&cru PCLK_NPU_ROOT>,
|
|
|
++ <&cru CLK_NPU_DSU0>;
|
|
|
++ pm_qos = <&qos_npu1>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_NPU2 {
|
|
|
++ reg = <RK3588_PD_NPU2>;
|
|
|
++ clocks = <&cru HCLK_NPU_ROOT>,
|
|
|
++ <&cru PCLK_NPU_ROOT>,
|
|
|
++ <&cru CLK_NPU_DSU0>;
|
|
|
++ pm_qos = <&qos_npu2>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++ /* These power domains are grouped by VD_GPU */
|
|
|
++ power-domain@RK3588_PD_GPU {
|
|
|
++ reg = <RK3588_PD_GPU>;
|
|
|
++ clocks = <&cru CLK_GPU>,
|
|
|
++ <&cru CLK_GPU_COREGROUP>,
|
|
|
++ <&cru CLK_GPU_STACKS>;
|
|
|
++ pm_qos = <&qos_gpu_m0>,
|
|
|
++ <&qos_gpu_m1>,
|
|
|
++ <&qos_gpu_m2>,
|
|
|
++ <&qos_gpu_m3>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ /* These power domains are grouped by VD_VCODEC */
|
|
|
++ power-domain@RK3588_PD_VCODEC {
|
|
|
++ reg = <RK3588_PD_VCODEC>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++
|
|
|
++ power-domain@RK3588_PD_RKVDEC0 {
|
|
|
++ reg = <RK3588_PD_RKVDEC0>;
|
|
|
++ clocks = <&cru HCLK_RKVDEC0>,
|
|
|
++ <&cru HCLK_VDPU_ROOT>,
|
|
|
++ <&cru ACLK_VDPU_ROOT>,
|
|
|
++ <&cru ACLK_RKVDEC0>,
|
|
|
++ <&cru ACLK_RKVDEC_CCU>;
|
|
|
++ pm_qos = <&qos_rkvdec0>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_RKVDEC1 {
|
|
|
++ reg = <RK3588_PD_RKVDEC1>;
|
|
|
++ clocks = <&cru HCLK_RKVDEC1>,
|
|
|
++ <&cru HCLK_VDPU_ROOT>,
|
|
|
++ <&cru ACLK_VDPU_ROOT>,
|
|
|
++ <&cru ACLK_RKVDEC1>;
|
|
|
++ pm_qos = <&qos_rkvdec1>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_VENC0 {
|
|
|
++ reg = <RK3588_PD_VENC0>;
|
|
|
++ clocks = <&cru HCLK_RKVENC0>,
|
|
|
++ <&cru ACLK_RKVENC0>;
|
|
|
++ pm_qos = <&qos_rkvenc0_m0ro>,
|
|
|
++ <&qos_rkvenc0_m1ro>,
|
|
|
++ <&qos_rkvenc0_m2wo>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++
|
|
|
++ power-domain@RK3588_PD_VENC1 {
|
|
|
++ reg = <RK3588_PD_VENC1>;
|
|
|
++ clocks = <&cru HCLK_RKVENC1>,
|
|
|
++ <&cru HCLK_RKVENC0>,
|
|
|
++ <&cru ACLK_RKVENC0>,
|
|
|
++ <&cru ACLK_RKVENC1>;
|
|
|
++ pm_qos = <&qos_rkvenc1_m0ro>,
|
|
|
++ <&qos_rkvenc1_m1ro>,
|
|
|
++ <&qos_rkvenc1_m2wo>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++ /* These power domains are grouped by VD_LOGIC */
|
|
|
++ power-domain@RK3588_PD_VDPU {
|
|
|
++ reg = <RK3588_PD_VDPU>;
|
|
|
++ clocks = <&cru HCLK_VDPU_ROOT>,
|
|
|
++ <&cru ACLK_VDPU_LOW_ROOT>,
|
|
|
++ <&cru ACLK_VDPU_ROOT>,
|
|
|
++ <&cru ACLK_JPEG_DECODER_ROOT>,
|
|
|
++ <&cru ACLK_IEP2P0>,
|
|
|
++ <&cru HCLK_IEP2P0>,
|
|
|
++ <&cru ACLK_JPEG_ENCODER0>,
|
|
|
++ <&cru HCLK_JPEG_ENCODER0>,
|
|
|
++ <&cru ACLK_JPEG_ENCODER1>,
|
|
|
++ <&cru HCLK_JPEG_ENCODER1>,
|
|
|
++ <&cru ACLK_JPEG_ENCODER2>,
|
|
|
++ <&cru HCLK_JPEG_ENCODER2>,
|
|
|
++ <&cru ACLK_JPEG_ENCODER3>,
|
|
|
++ <&cru HCLK_JPEG_ENCODER3>,
|
|
|
++ <&cru ACLK_JPEG_DECODER>,
|
|
|
++ <&cru HCLK_JPEG_DECODER>,
|
|
|
++ <&cru ACLK_RGA2>,
|
|
|
++ <&cru HCLK_RGA2>;
|
|
|
++ pm_qos = <&qos_iep>,
|
|
|
++ <&qos_jpeg_dec>,
|
|
|
++ <&qos_jpeg_enc0>,
|
|
|
++ <&qos_jpeg_enc1>,
|
|
|
++ <&qos_jpeg_enc2>,
|
|
|
++ <&qos_jpeg_enc3>,
|
|
|
++ <&qos_rga2_mro>,
|
|
|
++ <&qos_rga2_mwo>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++
|
|
|
++
|
|
|
++ power-domain@RK3588_PD_AV1 {
|
|
|
++ reg = <RK3588_PD_AV1>;
|
|
|
++ clocks = <&cru PCLK_AV1>,
|
|
|
++ <&cru ACLK_AV1>,
|
|
|
++ <&cru HCLK_VDPU_ROOT>;
|
|
|
++ pm_qos = <&qos_av1>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_RKVDEC0 {
|
|
|
++ reg = <RK3588_PD_RKVDEC0>;
|
|
|
++ clocks = <&cru HCLK_RKVDEC0>,
|
|
|
++ <&cru HCLK_VDPU_ROOT>,
|
|
|
++ <&cru ACLK_VDPU_ROOT>,
|
|
|
++ <&cru ACLK_RKVDEC0>;
|
|
|
++ pm_qos = <&qos_rkvdec0>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_RKVDEC1 {
|
|
|
++ reg = <RK3588_PD_RKVDEC1>;
|
|
|
++ clocks = <&cru HCLK_RKVDEC1>,
|
|
|
++ <&cru HCLK_VDPU_ROOT>,
|
|
|
++ <&cru ACLK_VDPU_ROOT>;
|
|
|
++ pm_qos = <&qos_rkvdec1>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_RGA30 {
|
|
|
++ reg = <RK3588_PD_RGA30>;
|
|
|
++ clocks = <&cru ACLK_RGA3_0>,
|
|
|
++ <&cru HCLK_RGA3_0>;
|
|
|
++ pm_qos = <&qos_rga3_0>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_VOP {
|
|
|
++ reg = <RK3588_PD_VOP>;
|
|
|
++ clocks = <&cru PCLK_VOP_ROOT>,
|
|
|
++ <&cru HCLK_VOP_ROOT>,
|
|
|
++ <&cru ACLK_VOP>;
|
|
|
++ pm_qos = <&qos_vop_m0>,
|
|
|
++ <&qos_vop_m1>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++
|
|
|
++ power-domain@RK3588_PD_VO0 {
|
|
|
++ reg = <RK3588_PD_VO0>;
|
|
|
++ clocks = <&cru PCLK_VO0_ROOT>,
|
|
|
++ <&cru PCLK_VO0_S_ROOT>,
|
|
|
++ <&cru HCLK_VO0_S_ROOT>,
|
|
|
++ <&cru ACLK_VO0_ROOT>,
|
|
|
++ <&cru HCLK_HDCP0>,
|
|
|
++ <&cru ACLK_HDCP0>,
|
|
|
++ <&cru HCLK_VOP_ROOT>;
|
|
|
++ pm_qos = <&qos_hdcp0>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_VO1 {
|
|
|
++ reg = <RK3588_PD_VO1>;
|
|
|
++ clocks = <&cru PCLK_VO1_ROOT>,
|
|
|
++ <&cru PCLK_VO1_S_ROOT>,
|
|
|
++ <&cru HCLK_VO1_S_ROOT>,
|
|
|
++ <&cru HCLK_HDCP1>,
|
|
|
++ <&cru ACLK_HDCP1>,
|
|
|
++ <&cru ACLK_HDMIRX_ROOT>,
|
|
|
++ <&cru HCLK_VO1USB_TOP_ROOT>;
|
|
|
++ pm_qos = <&qos_hdcp1>,
|
|
|
++ <&qos_hdmirx>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_VI {
|
|
|
++ reg = <RK3588_PD_VI>;
|
|
|
++ clocks = <&cru HCLK_VI_ROOT>,
|
|
|
++ <&cru PCLK_VI_ROOT>,
|
|
|
++ <&cru HCLK_ISP0>,
|
|
|
++ <&cru ACLK_ISP0>,
|
|
|
++ <&cru HCLK_VICAP>,
|
|
|
++ <&cru ACLK_VICAP>;
|
|
|
++ pm_qos = <&qos_isp0_mro>,
|
|
|
++ <&qos_isp0_mwo>,
|
|
|
++ <&qos_vicap_m0>,
|
|
|
++ <&qos_vicap_m1>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++
|
|
|
++ power-domain@RK3588_PD_ISP1 {
|
|
|
++ reg = <RK3588_PD_ISP1>;
|
|
|
++ clocks = <&cru HCLK_ISP1>,
|
|
|
++ <&cru ACLK_ISP1>,
|
|
|
++ <&cru HCLK_VI_ROOT>,
|
|
|
++ <&cru PCLK_VI_ROOT>;
|
|
|
++ pm_qos = <&qos_isp1_mwo>,
|
|
|
++ <&qos_isp1_mro>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_FEC {
|
|
|
++ reg = <RK3588_PD_FEC>;
|
|
|
++ clocks = <&cru HCLK_FISHEYE0>,
|
|
|
++ <&cru ACLK_FISHEYE0>,
|
|
|
++ <&cru HCLK_FISHEYE1>,
|
|
|
++ <&cru ACLK_FISHEYE1>,
|
|
|
++ <&cru PCLK_VI_ROOT>;
|
|
|
++ pm_qos = <&qos_fisheye0>,
|
|
|
++ <&qos_fisheye1>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_RGA31 {
|
|
|
++ reg = <RK3588_PD_RGA31>;
|
|
|
++ clocks = <&cru HCLK_RGA3_1>,
|
|
|
++ <&cru ACLK_RGA3_1>;
|
|
|
++ pm_qos = <&qos_rga3_1>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_USB {
|
|
|
++ reg = <RK3588_PD_USB>;
|
|
|
++ clocks = <&cru PCLK_PHP_ROOT>,
|
|
|
++ <&cru ACLK_USB_ROOT>,
|
|
|
++ <&cru ACLK_USB>,
|
|
|
++ <&cru HCLK_USB_ROOT>,
|
|
|
++ <&cru HCLK_HOST0>,
|
|
|
++ <&cru HCLK_HOST_ARB0>,
|
|
|
++ <&cru HCLK_HOST1>,
|
|
|
++ <&cru HCLK_HOST_ARB1>;
|
|
|
++ pm_qos = <&qos_usb3_0>,
|
|
|
++ <&qos_usb3_1>,
|
|
|
++ <&qos_usb2host_0>,
|
|
|
++ <&qos_usb2host_1>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_GMAC {
|
|
|
++ reg = <RK3588_PD_GMAC>;
|
|
|
++ clocks = <&cru PCLK_PHP_ROOT>,
|
|
|
++ <&cru ACLK_PCIE_ROOT>,
|
|
|
++ <&cru ACLK_PHP_ROOT>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_PCIE {
|
|
|
++ reg = <RK3588_PD_PCIE>;
|
|
|
++ clocks = <&cru PCLK_PHP_ROOT>,
|
|
|
++ <&cru ACLK_PCIE_ROOT>,
|
|
|
++ <&cru ACLK_PHP_ROOT>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_SDIO {
|
|
|
++ reg = <RK3588_PD_SDIO>;
|
|
|
++ clocks = <&cru HCLK_SDIO>,
|
|
|
++ <&cru HCLK_NVM_ROOT>;
|
|
|
++ pm_qos = <&qos_sdio>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_AUDIO {
|
|
|
++ reg = <RK3588_PD_AUDIO>;
|
|
|
++ clocks = <&cru HCLK_AUDIO_ROOT>,
|
|
|
++ <&cru PCLK_AUDIO_ROOT>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ power-domain@RK3588_PD_SDMMC {
|
|
|
++ reg = <RK3588_PD_SDMMC>;
|
|
|
++ pm_qos = <&qos_sdmmc>;
|
|
|
++ #power-domain-cells = <0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ av1d: video-codec@fdc70000 {
|
|
|
++ compatible = "rockchip,rk3588-av1-vpu";
|
|
|
++ reg = <0x0 0xfdc70000 0x0 0x800>;
|
|
|
++ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "vdpu";
|
|
|
++ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
|
|
++ assigned-clock-rates = <400000000>, <400000000>;
|
|
|
++ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
|
|
++ clock-names = "aclk", "hclk";
|
|
|
++ power-domains = <&power RK3588_PD_AV1>;
|
|
|
++ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
|
|
|
++ };
|
|
|
++
|
|
|
++ vop: vop@fdd90000 {
|
|
|
++ compatible = "rockchip,rk3588-vop";
|
|
|
++ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
|
|
|
++ reg-names = "vop", "gamma-lut";
|
|
|
++ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru ACLK_VOP>,
|
|
|
++ <&cru HCLK_VOP>,
|
|
|
++ <&cru DCLK_VOP0>,
|
|
|
++ <&cru DCLK_VOP1>,
|
|
|
++ <&cru DCLK_VOP2>,
|
|
|
++ <&cru DCLK_VOP3>,
|
|
|
++ <&cru PCLK_VOP_ROOT>;
|
|
|
++ clock-names = "aclk",
|
|
|
++ "hclk",
|
|
|
++ "dclk_vp0",
|
|
|
++ "dclk_vp1",
|
|
|
++ "dclk_vp2",
|
|
|
++ "dclk_vp3",
|
|
|
++ "pclk_vop";
|
|
|
++ iommus = <&vop_mmu>;
|
|
|
++ power-domains = <&power RK3588_PD_VOP>;
|
|
|
++ rockchip,grf = <&sys_grf>;
|
|
|
++ rockchip,vop-grf = <&vop_grf>;
|
|
|
++ rockchip,vo1-grf = <&vo1_grf>;
|
|
|
++ rockchip,pmu = <&pmu>;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ vop_out: ports {
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++
|
|
|
++ vp0: port@0 {
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ reg = <0>;
|
|
|
++ };
|
|
|
++
|
|
|
++ vp1: port@1 {
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ reg = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ vp2: port@2 {
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ reg = <2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ vp3: port@3 {
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ reg = <3>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ vop_mmu: iommu@fdd97e00 {
|
|
|
++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
|
|
|
++ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
|
|
++ clock-names = "aclk", "iface";
|
|
|
++ #iommu-cells = <0>;
|
|
|
++ power-domains = <&power RK3588_PD_VOP>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s4_8ch: i2s@fddc0000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
++ reg = <0x0 0xfddc0000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
|
|
|
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
++ assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
|
|
|
++ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
++ dmas = <&dmac2 0>;
|
|
|
++ dma-names = "tx";
|
|
|
++ power-domains = <&power RK3588_PD_VO0>;
|
|
|
++ resets = <&cru SRST_M_I2S4_8CH_TX>;
|
|
|
++ reset-names = "tx-m";
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s5_8ch: i2s@fddf0000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
++ reg = <0x0 0xfddf0000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
|
|
|
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
++ assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
|
|
|
++ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
++ dmas = <&dmac2 2>;
|
|
|
++ dma-names = "tx";
|
|
|
++ power-domains = <&power RK3588_PD_VO1>;
|
|
|
++ resets = <&cru SRST_M_I2S5_8CH_TX>;
|
|
|
++ reset-names = "tx-m";
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s9_8ch: i2s@fddfc000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
++ reg = <0x0 0xfddfc000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
|
|
|
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
++ assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
|
|
|
++ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
++ dmas = <&dmac2 23>;
|
|
|
++ dma-names = "rx";
|
|
|
++ power-domains = <&power RK3588_PD_VO1>;
|
|
|
++ resets = <&cru SRST_M_I2S9_8CH_RX>;
|
|
|
++ reset-names = "rx-m";
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_gpu_m0: qos@fdf35000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf35000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_gpu_m1: qos@fdf35200 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf35200 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_gpu_m2: qos@fdf35400 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf35400 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_gpu_m3: qos@fdf35600 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf35600 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rga3_1: qos@fdf36000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf36000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_sdio: qos@fdf39000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf39000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_sdmmc: qos@fdf3d800 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf3d800 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_usb3_1: qos@fdf3e000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf3e000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_usb3_0: qos@fdf3e200 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf3e200 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_usb2host_0: qos@fdf3e400 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf3e400 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_usb2host_1: qos@fdf3e600 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf3e600 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_fisheye0: qos@fdf40000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf40000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_fisheye1: qos@fdf40200 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf40200 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_isp0_mro: qos@fdf40400 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf40400 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_isp0_mwo: qos@fdf40500 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf40500 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_vicap_m0: qos@fdf40600 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf40600 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_vicap_m1: qos@fdf40800 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf40800 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_isp1_mwo: qos@fdf41000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf41000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_isp1_mro: qos@fdf41100 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf41100 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rkvenc0_m0ro: qos@fdf60000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf60000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rkvenc0_m1ro: qos@fdf60200 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf60200 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rkvenc0_m2wo: qos@fdf60400 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf60400 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rkvenc1_m0ro: qos@fdf61000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf61000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rkvenc1_m1ro: qos@fdf61200 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf61200 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rkvenc1_m2wo: qos@fdf61400 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf61400 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rkvdec0: qos@fdf62000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf62000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rkvdec1: qos@fdf63000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf63000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_av1: qos@fdf64000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf64000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_iep: qos@fdf66000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf66000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_jpeg_dec: qos@fdf66200 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf66200 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_jpeg_enc0: qos@fdf66400 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf66400 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_jpeg_enc1: qos@fdf66600 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf66600 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_jpeg_enc2: qos@fdf66800 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf66800 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_jpeg_enc3: qos@fdf66a00 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf66a00 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rga2_mro: qos@fdf66c00 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf66c00 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rga2_mwo: qos@fdf66e00 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf66e00 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_rga3_0: qos@fdf67000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf67000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_vdpu: qos@fdf67200 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf67200 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_npu1: qos@fdf70000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf70000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_npu2: qos@fdf71000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf71000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_npu0_mwr: qos@fdf72000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf72000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_npu0_mro: qos@fdf72200 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf72200 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_mcu_npu: qos@fdf72400 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf72400 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_hdcp0: qos@fdf80000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf80000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_hdcp1: qos@fdf81000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf81000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_hdmirx: qos@fdf81200 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf81200 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_vop_m0: qos@fdf82000 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf82000 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ qos_vop_m1: qos@fdf82200 {
|
|
|
++ compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
++ reg = <0x0 0xfdf82200 0x0 0x20>;
|
|
|
++ };
|
|
|
++
|
|
|
++ dfi: dfi@fe060000 {
|
|
|
++ reg = <0x00 0xfe060000 0x00 0x10000>;
|
|
|
++ compatible = "rockchip,rk3588-dfi";
|
|
|
++ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ rockchip,pmu = <&pmu1grf>;
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie2x1l1: pcie@fe180000 {
|
|
|
++ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
|
++ bus-range = <0x30 0x3f>;
|
|
|
++ clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
|
|
|
++ <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
|
|
|
++ <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
|
|
|
++ clock-names = "aclk_mst", "aclk_slv",
|
|
|
++ "aclk_dbi", "pclk",
|
|
|
++ "aux", "pipe";
|
|
|
++ device_type = "pci";
|
|
|
++ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
|
++ #interrupt-cells = <1>;
|
|
|
++ interrupt-map-mask = <0 0 0 7>;
|
|
|
++ interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
|
|
|
++ <0 0 0 2 &pcie2x1l1_intc 1>,
|
|
|
++ <0 0 0 3 &pcie2x1l1_intc 2>,
|
|
|
++ <0 0 0 4 &pcie2x1l1_intc 3>;
|
|
|
++ linux,pci-domain = <3>;
|
|
|
++ max-link-speed = <2>;
|
|
|
++ msi-map = <0x3000 &its0 0x3000 0x1000>;
|
|
|
++ num-lanes = <1>;
|
|
|
++ phys = <&combphy2_psu PHY_TYPE_PCIE>;
|
|
|
++ phy-names = "pcie-phy";
|
|
|
++ power-domains = <&power RK3588_PD_PCIE>;
|
|
|
++ ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
|
|
|
++ <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
|
|
|
++ <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
|
|
|
++ reg = <0xa 0x40c00000 0x0 0x00400000>,
|
|
|
++ <0x0 0xfe180000 0x0 0x00010000>,
|
|
|
++ <0x0 0xf3000000 0x0 0x00100000>;
|
|
|
++ reg-names = "dbi", "apb", "config";
|
|
|
++ resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
|
|
|
++ reset-names = "pwr", "pipe";
|
|
|
++ #address-cells = <3>;
|
|
|
++ #size-cells = <2>;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ pcie2x1l1_intc: legacy-interrupt-controller {
|
|
|
++ interrupt-controller;
|
|
|
++ #address-cells = <0>;
|
|
|
++ #interrupt-cells = <1>;
|
|
|
++ interrupt-parent = <&gic>;
|
|
|
++ interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie2x1l2: pcie@fe190000 {
|
|
|
++ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
|
++ bus-range = <0x40 0x4f>;
|
|
|
++ clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
|
|
|
++ <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
|
|
|
++ <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
|
|
|
++ clock-names = "aclk_mst", "aclk_slv",
|
|
|
++ "aclk_dbi", "pclk",
|
|
|
++ "aux", "pipe";
|
|
|
++ device_type = "pci";
|
|
|
++ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
|
++ #interrupt-cells = <1>;
|
|
|
++ interrupt-map-mask = <0 0 0 7>;
|
|
|
++ interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
|
|
|
++ <0 0 0 2 &pcie2x1l2_intc 1>,
|
|
|
++ <0 0 0 3 &pcie2x1l2_intc 2>,
|
|
|
++ <0 0 0 4 &pcie2x1l2_intc 3>;
|
|
|
++ linux,pci-domain = <4>;
|
|
|
++ max-link-speed = <2>;
|
|
|
++ msi-map = <0x4000 &its0 0x4000 0x1000>;
|
|
|
++ num-lanes = <1>;
|
|
|
++ phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
|
|
++ phy-names = "pcie-phy";
|
|
|
++ power-domains = <&power RK3588_PD_PCIE>;
|
|
|
++ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
|
|
|
++ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
|
|
|
++ <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
|
|
|
++ reg = <0xa 0x41000000 0x0 0x00400000>,
|
|
|
++ <0x0 0xfe190000 0x0 0x00010000>,
|
|
|
++ <0x0 0xf4000000 0x0 0x00100000>;
|
|
|
++ reg-names = "dbi", "apb", "config";
|
|
|
++ resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
|
|
|
++ reset-names = "pwr", "pipe";
|
|
|
++ #address-cells = <3>;
|
|
|
++ #size-cells = <2>;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ pcie2x1l2_intc: legacy-interrupt-controller {
|
|
|
++ interrupt-controller;
|
|
|
++ #address-cells = <0>;
|
|
|
++ #interrupt-cells = <1>;
|
|
|
++ interrupt-parent = <&gic>;
|
|
|
++ interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ gmac1: ethernet@fe1c0000 {
|
|
|
++ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
|
|
++ reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
|
|
++ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "macirq", "eth_wake_irq";
|
|
|
++ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
|
|
|
++ <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
|
|
|
++ <&cru CLK_GMAC1_PTP_REF>;
|
|
|
++ clock-names = "stmmaceth", "clk_mac_ref",
|
|
|
++ "pclk_mac", "aclk_mac",
|
|
|
++ "ptp_ref";
|
|
|
++ power-domains = <&power RK3588_PD_GMAC>;
|
|
|
++ resets = <&cru SRST_A_GMAC1>;
|
|
|
++ reset-names = "stmmaceth";
|
|
|
++ rockchip,grf = <&sys_grf>;
|
|
|
++ rockchip,php-grf = <&php_grf>;
|
|
|
++ snps,axi-config = <&gmac1_stmmac_axi_setup>;
|
|
|
++ snps,mixed-burst;
|
|
|
++ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
|
|
|
++ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
|
|
|
++ snps,tso;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ mdio1: mdio {
|
|
|
++ compatible = "snps,dwmac-mdio";
|
|
|
++ #address-cells = <0x1>;
|
|
|
++ #size-cells = <0x0>;
|
|
|
++ };
|
|
|
++
|
|
|
++ gmac1_stmmac_axi_setup: stmmac-axi-config {
|
|
|
++ snps,blen = <0 0 0 0 16 8 4>;
|
|
|
++ snps,wr_osr_lmt = <4>;
|
|
|
++ snps,rd_osr_lmt = <8>;
|
|
|
++ };
|
|
|
++
|
|
|
++ gmac1_mtl_rx_setup: rx-queues-config {
|
|
|
++ snps,rx-queues-to-use = <2>;
|
|
|
++ queue0 {};
|
|
|
++ queue1 {};
|
|
|
++ };
|
|
|
++
|
|
|
++ gmac1_mtl_tx_setup: tx-queues-config {
|
|
|
++ snps,tx-queues-to-use = <2>;
|
|
|
++ queue0 {};
|
|
|
++ queue1 {};
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ sata0: sata@fe210000 {
|
|
|
++ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
|
|
++ reg = <0 0xfe210000 0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
|
|
|
++ <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
|
|
|
++ <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
|
|
|
++ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
|
|
++ ports-implemented = <0x1>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ sata-port@0 {
|
|
|
++ reg = <0>;
|
|
|
++ hba-port-cap = <HBA_PORT_FBSCP>;
|
|
|
++ phys = <&combphy0_ps PHY_TYPE_SATA>;
|
|
|
++ phy-names = "sata-phy";
|
|
|
++ snps,rx-ts-max = <32>;
|
|
|
++ snps,tx-ts-max = <32>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ sata2: sata@fe230000 {
|
|
|
++ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
|
|
++ reg = <0 0xfe230000 0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
|
|
|
++ <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
|
|
|
++ <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
|
|
|
++ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
|
|
++ ports-implemented = <0x1>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ sata-port@0 {
|
|
|
++ reg = <0>;
|
|
|
++ hba-port-cap = <HBA_PORT_FBSCP>;
|
|
|
++ phys = <&combphy2_psu PHY_TYPE_SATA>;
|
|
|
++ phy-names = "sata-phy";
|
|
|
++ snps,rx-ts-max = <32>;
|
|
|
++ snps,tx-ts-max = <32>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ sfc: spi@fe2b0000 {
|
|
|
++ compatible = "rockchip,sfc";
|
|
|
++ reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
|
|
++ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
|
|
++ clock-names = "clk_sfc", "hclk_sfc";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ sdmmc: mmc@fe2c0000 {
|
|
|
++ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
|
++ reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
|
|
++ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
|
|
|
++ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
|
|
++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
|
++ fifo-depth = <0x100>;
|
|
|
++ max-frequency = <200000000>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
|
|
|
++ power-domains = <&power RK3588_PD_SDMMC>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ sdio: mmc@fe2d0000 {
|
|
|
++ compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
|
++ reg = <0x00 0xfe2d0000 0x00 0x4000>;
|
|
|
++ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
|
|
|
++ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
|
|
++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
|
++ fifo-depth = <0x100>;
|
|
|
++ max-frequency = <200000000>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ pinctrl-0 = <&sdiom1_pins>;
|
|
|
++ power-domains = <&power RK3588_PD_SDIO>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ sdhci: mmc@fe2e0000 {
|
|
|
++ compatible = "rockchip,rk3588-dwcmshc";
|
|
|
++ reg = <0x0 0xfe2e0000 0x0 0x10000>;
|
|
|
++ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
|
|
|
++ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
|
|
|
++ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
|
|
|
++ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
|
|
++ <&cru TMCLK_EMMC>;
|
|
|
++ clock-names = "core", "bus", "axi", "block", "timer";
|
|
|
++ max-frequency = <200000000>;
|
|
|
++ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
|
|
|
++ <&emmc_cmd>, <&emmc_data_strobe>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
|
|
|
++ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
|
|
|
++ <&cru SRST_T_EMMC>;
|
|
|
++ reset-names = "core", "bus", "axi", "block", "timer";
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s0_8ch: i2s@fe470000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
++ reg = <0x0 0xfe470000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
|
|
|
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
++ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
|
|
|
++ assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
|
|
|
++ dmas = <&dmac0 0>, <&dmac0 1>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ power-domains = <&power RK3588_PD_AUDIO>;
|
|
|
++ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
|
|
|
++ reset-names = "tx-m", "rx-m";
|
|
|
++ rockchip,trcm-sync-tx-only;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ pinctrl-0 = <&i2s0_lrck
|
|
|
++ &i2s0_sclk
|
|
|
++ &i2s0_sdi0
|
|
|
++ &i2s0_sdi1
|
|
|
++ &i2s0_sdi2
|
|
|
++ &i2s0_sdi3
|
|
|
++ &i2s0_sdo0
|
|
|
++ &i2s0_sdo1
|
|
|
++ &i2s0_sdo2
|
|
|
++ &i2s0_sdo3>;
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s1_8ch: i2s@fe480000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
++ reg = <0x0 0xfe480000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
|
|
|
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
++ dmas = <&dmac0 2>, <&dmac0 3>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
|
|
|
++ reset-names = "tx-m", "rx-m";
|
|
|
++ rockchip,trcm-sync-tx-only;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ pinctrl-0 = <&i2s1m0_lrck
|
|
|
++ &i2s1m0_sclk
|
|
|
++ &i2s1m0_sdi0
|
|
|
++ &i2s1m0_sdi1
|
|
|
++ &i2s1m0_sdi2
|
|
|
++ &i2s1m0_sdi3
|
|
|
++ &i2s1m0_sdo0
|
|
|
++ &i2s1m0_sdo1
|
|
|
++ &i2s1m0_sdo2
|
|
|
++ &i2s1m0_sdo3>;
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s2_2ch: i2s@fe490000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
|
|
|
++ reg = <0x0 0xfe490000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
|
|
|
++ clock-names = "i2s_clk", "i2s_hclk";
|
|
|
++ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
|
|
|
++ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
++ dmas = <&dmac1 0>, <&dmac1 1>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ power-domains = <&power RK3588_PD_AUDIO>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ pinctrl-0 = <&i2s2m1_lrck
|
|
|
++ &i2s2m1_sclk
|
|
|
++ &i2s2m1_sdi
|
|
|
++ &i2s2m1_sdo>;
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s3_2ch: i2s@fe4a0000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
|
|
|
++ reg = <0x0 0xfe4a0000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
|
|
|
++ clock-names = "i2s_clk", "i2s_hclk";
|
|
|
++ assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
|
|
|
++ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
++ dmas = <&dmac1 2>, <&dmac1 3>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ power-domains = <&power RK3588_PD_AUDIO>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ pinctrl-0 = <&i2s3_lrck
|
|
|
++ &i2s3_sclk
|
|
|
++ &i2s3_sdi
|
|
|
++ &i2s3_sdo>;
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ gic: interrupt-controller@fe600000 {
|
|
|
++ compatible = "arm,gic-v3";
|
|
|
++ reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
|
|
|
++ <0x0 0xfe680000 0 0x100000>; /* GICR */
|
|
|
++ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-controller;
|
|
|
++ mbi-alias = <0x0 0xfe610000>;
|
|
|
++ mbi-ranges = <424 56>;
|
|
|
++ msi-controller;
|
|
|
++ ranges;
|
|
|
++ #address-cells = <2>;
|
|
|
++ #interrupt-cells = <4>;
|
|
|
++ #size-cells = <2>;
|
|
|
++
|
|
|
++ its0: msi-controller@fe640000 {
|
|
|
++ compatible = "arm,gic-v3-its";
|
|
|
++ reg = <0x0 0xfe640000 0x0 0x20000>;
|
|
|
++ msi-controller;
|
|
|
++ #msi-cells = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ its1: msi-controller@fe660000 {
|
|
|
++ compatible = "arm,gic-v3-its";
|
|
|
++ reg = <0x0 0xfe660000 0x0 0x20000>;
|
|
|
++ msi-controller;
|
|
|
++ #msi-cells = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ ppi-partitions {
|
|
|
++ ppi_partition0: interrupt-partition-0 {
|
|
|
++ affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
|
|
|
++ };
|
|
|
++
|
|
|
++ ppi_partition1: interrupt-partition-1 {
|
|
|
++ affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ dmac0: dma-controller@fea10000 {
|
|
|
++ compatible = "arm,pl330", "arm,primecell";
|
|
|
++ reg = <0x0 0xfea10000 0x0 0x4000>;
|
|
|
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ arm,pl330-periph-burst;
|
|
|
++ clocks = <&cru ACLK_DMAC0>;
|
|
|
++ clock-names = "apb_pclk";
|
|
|
++ #dma-cells = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ dmac1: dma-controller@fea30000 {
|
|
|
++ compatible = "arm,pl330", "arm,primecell";
|
|
|
++ reg = <0x0 0xfea30000 0x0 0x4000>;
|
|
|
++ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ arm,pl330-periph-burst;
|
|
|
++ clocks = <&cru ACLK_DMAC1>;
|
|
|
++ clock-names = "apb_pclk";
|
|
|
++ #dma-cells = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c1: i2c@fea90000 {
|
|
|
++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
++ reg = <0x0 0xfea90000 0x0 0x1000>;
|
|
|
++ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
|
|
++ clock-names = "i2c", "pclk";
|
|
|
++ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ pinctrl-0 = <&i2c1m0_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c2: i2c@feaa0000 {
|
|
|
++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
++ reg = <0x0 0xfeaa0000 0x0 0x1000>;
|
|
|
++ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
|
|
++ clock-names = "i2c", "pclk";
|
|
|
++ interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ pinctrl-0 = <&i2c2m0_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c3: i2c@feab0000 {
|
|
|
++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
++ reg = <0x0 0xfeab0000 0x0 0x1000>;
|
|
|
++ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
|
|
++ clock-names = "i2c", "pclk";
|
|
|
++ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ pinctrl-0 = <&i2c3m0_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c4: i2c@feac0000 {
|
|
|
++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
++ reg = <0x0 0xfeac0000 0x0 0x1000>;
|
|
|
++ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
|
|
++ clock-names = "i2c", "pclk";
|
|
|
++ interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ pinctrl-0 = <&i2c4m0_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c5: i2c@fead0000 {
|
|
|
++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
++ reg = <0x0 0xfead0000 0x0 0x1000>;
|
|
|
++ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
|
|
++ clock-names = "i2c", "pclk";
|
|
|
++ interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ pinctrl-0 = <&i2c5m0_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ timer0: timer@feae0000 {
|
|
|
++ compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
|
|
|
++ reg = <0x0 0xfeae0000 0x0 0x20>;
|
|
|
++ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
|
|
|
++ clock-names = "pclk", "timer";
|
|
|
++ };
|
|
|
++
|
|
|
++ wdt: watchdog@feaf0000 {
|
|
|
++ compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
|
|
|
++ reg = <0x0 0xfeaf0000 0x0 0x100>;
|
|
|
++ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
|
|
|
++ clock-names = "tclk", "pclk";
|
|
|
++ interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ };
|
|
|
++
|
|
|
++ spi0: spi@feb00000 {
|
|
|
++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
|
|
++ reg = <0x0 0xfeb00000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
|
|
|
++ clock-names = "spiclk", "apb_pclk";
|
|
|
++ dmas = <&dmac0 14>, <&dmac0 15>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ num-cs = <2>;
|
|
|
++ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ spi1: spi@feb10000 {
|
|
|
++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
|
|
++ reg = <0x0 0xfeb10000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
|
|
|
++ clock-names = "spiclk", "apb_pclk";
|
|
|
++ dmas = <&dmac0 16>, <&dmac0 17>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ num-cs = <2>;
|
|
|
++ pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ spi2: spi@feb20000 {
|
|
|
++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
|
|
++ reg = <0x0 0xfeb20000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
|
|
|
++ clock-names = "spiclk", "apb_pclk";
|
|
|
++ dmas = <&dmac1 15>, <&dmac1 16>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ num-cs = <2>;
|
|
|
++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ spi3: spi@feb30000 {
|
|
|
++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
|
|
++ reg = <0x0 0xfeb30000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
|
|
|
++ clock-names = "spiclk", "apb_pclk";
|
|
|
++ dmas = <&dmac1 17>, <&dmac1 18>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ num-cs = <2>;
|
|
|
++ pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ uart1: serial@feb40000 {
|
|
|
++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
++ reg = <0x0 0xfeb40000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
|
++ clock-names = "baudclk", "apb_pclk";
|
|
|
++ dmas = <&dmac0 8>, <&dmac0 9>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ pinctrl-0 = <&uart1m1_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ reg-io-width = <4>;
|
|
|
++ reg-shift = <2>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ uart2: serial@feb50000 {
|
|
|
++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
++ reg = <0x0 0xfeb50000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
|
++ clock-names = "baudclk", "apb_pclk";
|
|
|
++ dmas = <&dmac0 10>, <&dmac0 11>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ pinctrl-0 = <&uart2m1_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ reg-io-width = <4>;
|
|
|
++ reg-shift = <2>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ uart3: serial@feb60000 {
|
|
|
++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
++ reg = <0x0 0xfeb60000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
|
++ clock-names = "baudclk", "apb_pclk";
|
|
|
++ dmas = <&dmac0 12>, <&dmac0 13>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ pinctrl-0 = <&uart3m1_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ reg-io-width = <4>;
|
|
|
++ reg-shift = <2>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ uart4: serial@feb70000 {
|
|
|
++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
++ reg = <0x0 0xfeb70000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
|
++ clock-names = "baudclk", "apb_pclk";
|
|
|
++ dmas = <&dmac1 9>, <&dmac1 10>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ pinctrl-0 = <&uart4m1_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ reg-io-width = <4>;
|
|
|
++ reg-shift = <2>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ uart5: serial@feb80000 {
|
|
|
++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
++ reg = <0x0 0xfeb80000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
|
|
++ clock-names = "baudclk", "apb_pclk";
|
|
|
++ dmas = <&dmac1 11>, <&dmac1 12>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ pinctrl-0 = <&uart5m1_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ reg-io-width = <4>;
|
|
|
++ reg-shift = <2>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ uart6: serial@feb90000 {
|
|
|
++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
++ reg = <0x0 0xfeb90000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
|
|
++ clock-names = "baudclk", "apb_pclk";
|
|
|
++ dmas = <&dmac1 13>, <&dmac1 14>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ pinctrl-0 = <&uart6m1_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ reg-io-width = <4>;
|
|
|
++ reg-shift = <2>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ uart7: serial@feba0000 {
|
|
|
++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
++ reg = <0x0 0xfeba0000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
|
|
++ clock-names = "baudclk", "apb_pclk";
|
|
|
++ dmas = <&dmac2 7>, <&dmac2 8>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ pinctrl-0 = <&uart7m1_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ reg-io-width = <4>;
|
|
|
++ reg-shift = <2>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ uart8: serial@febb0000 {
|
|
|
++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
++ reg = <0x0 0xfebb0000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
|
|
++ clock-names = "baudclk", "apb_pclk";
|
|
|
++ dmas = <&dmac2 9>, <&dmac2 10>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ pinctrl-0 = <&uart8m1_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ reg-io-width = <4>;
|
|
|
++ reg-shift = <2>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ uart9: serial@febc0000 {
|
|
|
++ compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
++ reg = <0x0 0xfebc0000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
|
|
++ clock-names = "baudclk", "apb_pclk";
|
|
|
++ dmas = <&dmac2 11>, <&dmac2 12>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ pinctrl-0 = <&uart9m1_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ reg-io-width = <4>;
|
|
|
++ reg-shift = <2>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm4: pwm@febd0000 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebd0000 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm4m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm5: pwm@febd0010 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebd0010 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm5m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm6: pwm@febd0020 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebd0020 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm6m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm7: pwm@febd0030 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebd0030 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm7m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm8: pwm@febe0000 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebe0000 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm8m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm9: pwm@febe0010 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebe0010 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm9m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm10: pwm@febe0020 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebe0020 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm10m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm11: pwm@febe0030 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebe0030 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm11m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm12: pwm@febf0000 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebf0000 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm12m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm13: pwm@febf0010 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebf0010 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm13m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm14: pwm@febf0020 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebf0020 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm14m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm15: pwm@febf0030 {
|
|
|
++ compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
++ reg = <0x0 0xfebf0030 0x0 0x10>;
|
|
|
++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
|
++ clock-names = "pwm", "pclk";
|
|
|
++ pinctrl-0 = <&pwm15m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #pwm-cells = <3>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ tsadc: tsadc@fec00000 {
|
|
|
++ compatible = "rockchip,rk3588-tsadc";
|
|
|
++ reg = <0x0 0xfec00000 0x0 0x400>;
|
|
|
++ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
|
|
++ clock-names = "tsadc", "apb_pclk";
|
|
|
++ assigned-clocks = <&cru CLK_TSADC>;
|
|
|
++ assigned-clock-rates = <2000000>;
|
|
|
++ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
|
|
|
++ reset-names = "tsadc-apb", "tsadc";
|
|
|
++ rockchip,hw-tshut-temp = <120000>;
|
|
|
++ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
|
|
++ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
|
|
++ pinctrl-0 = <&tsadc_gpio_func>;
|
|
|
++ pinctrl-1 = <&tsadc_shut>;
|
|
|
++ pinctrl-names = "gpio", "otpout";
|
|
|
++ #thermal-sensor-cells = <1>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ saradc: adc@fec10000 {
|
|
|
++ compatible = "rockchip,rk3588-saradc";
|
|
|
++ reg = <0x0 0xfec10000 0x0 0x10000>;
|
|
|
++ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ #io-channel-cells = <1>;
|
|
|
++ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
|
|
|
++ clock-names = "saradc", "apb_pclk";
|
|
|
++ resets = <&cru SRST_P_SARADC>;
|
|
|
++ reset-names = "saradc-apb";
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c6: i2c@fec80000 {
|
|
|
++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
++ reg = <0x0 0xfec80000 0x0 0x1000>;
|
|
|
++ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
|
|
|
++ clock-names = "i2c", "pclk";
|
|
|
++ interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ pinctrl-0 = <&i2c6m0_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c7: i2c@fec90000 {
|
|
|
++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
++ reg = <0x0 0xfec90000 0x0 0x1000>;
|
|
|
++ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
|
|
|
++ clock-names = "i2c", "pclk";
|
|
|
++ interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ pinctrl-0 = <&i2c7m0_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c8: i2c@feca0000 {
|
|
|
++ compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
++ reg = <0x0 0xfeca0000 0x0 0x1000>;
|
|
|
++ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
|
|
|
++ clock-names = "i2c", "pclk";
|
|
|
++ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ pinctrl-0 = <&i2c8m0_xfer>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ spi4: spi@fecb0000 {
|
|
|
++ compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
|
|
++ reg = <0x0 0xfecb0000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
|
|
|
++ clock-names = "spiclk", "apb_pclk";
|
|
|
++ dmas = <&dmac2 13>, <&dmac2 14>;
|
|
|
++ dma-names = "tx", "rx";
|
|
|
++ num-cs = <2>;
|
|
|
++ pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
|
|
|
++ pinctrl-names = "default";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ otp: efuse@fecc0000 {
|
|
|
++ compatible = "rockchip,rk3588-otp";
|
|
|
++ reg = <0x0 0xfecc0000 0x0 0x400>;
|
|
|
++ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
|
|
|
++ <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
|
|
|
++ clock-names = "otp", "apb_pclk", "phy", "arb";
|
|
|
++ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
|
|
|
++ <&cru SRST_OTPC_ARB>;
|
|
|
++ reset-names = "otp", "apb", "arb";
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <1>;
|
|
|
++
|
|
|
++ cpu_code: cpu-code@2 {
|
|
|
++ reg = <0x02 0x2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ otp_id: id@7 {
|
|
|
++ reg = <0x07 0x10>;
|
|
|
++ };
|
|
|
++
|
|
|
++ cpub0_leakage: cpu-leakage@17 {
|
|
|
++ reg = <0x17 0x1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ cpub1_leakage: cpu-leakage@18 {
|
|
|
++ reg = <0x18 0x1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ cpul_leakage: cpu-leakage@19 {
|
|
|
++ reg = <0x19 0x1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ log_leakage: log-leakage@1a {
|
|
|
++ reg = <0x1a 0x1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ gpu_leakage: gpu-leakage@1b {
|
|
|
++ reg = <0x1b 0x1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ otp_cpu_version: cpu-version@1c {
|
|
|
++ reg = <0x1c 0x1>;
|
|
|
++ bits = <3 3>;
|
|
|
++ };
|
|
|
++
|
|
|
++ npu_leakage: npu-leakage@28 {
|
|
|
++ reg = <0x28 0x1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ codec_leakage: codec-leakage@29 {
|
|
|
++ reg = <0x29 0x1>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ dmac2: dma-controller@fed10000 {
|
|
|
++ compatible = "arm,pl330", "arm,primecell";
|
|
|
++ reg = <0x0 0xfed10000 0x0 0x4000>;
|
|
|
++ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ arm,pl330-periph-burst;
|
|
|
++ clocks = <&cru ACLK_DMAC2>;
|
|
|
++ clock-names = "apb_pclk";
|
|
|
++ #dma-cells = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ hdptxphy_hdmi0: phy@fed60000 {
|
|
|
++ compatible = "rockchip,rk3588-hdptx-phy";
|
|
|
++ reg = <0x0 0xfed60000 0x0 0x2000>;
|
|
|
++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
|
|
|
++ clock-names = "ref", "apb";
|
|
|
++ #phy-cells = <0>;
|
|
|
++ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
|
|
|
++ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
|
|
|
++ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
|
|
|
++ <&cru SRST_HDPTX0_LCPLL>;
|
|
|
++ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
|
|
|
++ "lcpll";
|
|
|
++ rockchip,grf = <&hdptxphy0_grf>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ usbdp_phy0: phy@fed80000 {
|
|
|
++ compatible = "rockchip,rk3588-usbdp-phy";
|
|
|
++ reg = <0x0 0xfed80000 0x0 0x10000>;
|
|
|
++ #phy-cells = <1>;
|
|
|
++ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
|
|
++ <&cru CLK_USBDP_PHY0_IMMORTAL>,
|
|
|
++ <&cru PCLK_USBDPPHY0>,
|
|
|
++ <&u2phy0>;
|
|
|
++ clock-names = "refclk", "immortal", "pclk", "utmi";
|
|
|
++ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
|
|
|
++ <&cru SRST_USBDP_COMBO_PHY0_CMN>,
|
|
|
++ <&cru SRST_USBDP_COMBO_PHY0_LANE>,
|
|
|
++ <&cru SRST_USBDP_COMBO_PHY0_PCS>,
|
|
|
++ <&cru SRST_P_USBDPPHY0>;
|
|
|
++ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
|
|
++ rockchip,u2phy-grf = <&usb2phy0_grf>;
|
|
|
++ rockchip,usb-grf = <&usb_grf>;
|
|
|
++ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
|
|
|
++ rockchip,vo-grf = <&vo0_grf>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ combphy0_ps: phy@fee00000 {
|
|
|
++ compatible = "rockchip,rk3588-naneng-combphy";
|
|
|
++ reg = <0x0 0xfee00000 0x0 0x100>;
|
|
|
++ clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
|
|
|
++ <&cru PCLK_PHP_ROOT>;
|
|
|
++ clock-names = "ref", "apb", "pipe";
|
|
|
++ assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
|
|
|
++ assigned-clock-rates = <100000000>;
|
|
|
++ #phy-cells = <1>;
|
|
|
++ resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
|
|
|
++ reset-names = "phy", "apb";
|
|
|
++ rockchip,pipe-grf = <&php_grf>;
|
|
|
++ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ combphy2_psu: phy@fee20000 {
|
|
|
++ compatible = "rockchip,rk3588-naneng-combphy";
|
|
|
++ reg = <0x0 0xfee20000 0x0 0x100>;
|
|
|
++ clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
|
|
|
++ <&cru PCLK_PHP_ROOT>;
|
|
|
++ clock-names = "ref", "apb", "pipe";
|
|
|
++ assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
|
|
|
++ assigned-clock-rates = <100000000>;
|
|
|
++ #phy-cells = <1>;
|
|
|
++ resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
|
|
|
++ reset-names = "phy", "apb";
|
|
|
++ rockchip,pipe-grf = <&php_grf>;
|
|
|
++ rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ system_sram2: sram@ff001000 {
|
|
|
++ compatible = "mmio-sram";
|
|
|
++ reg = <0x0 0xff001000 0x0 0xef000>;
|
|
|
++ ranges = <0x0 0x0 0xff001000 0xef000>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ pinctrl: pinctrl {
|
|
|
++ compatible = "rockchip,rk3588-pinctrl";
|
|
|
++ ranges;
|
|
|
++ rockchip,grf = <&ioc>;
|
|
|
++ #address-cells = <2>;
|
|
|
++ #size-cells = <2>;
|
|
|
++
|
|
|
++ gpio0: gpio@fd8a0000 {
|
|
|
++ compatible = "rockchip,gpio-bank";
|
|
|
++ reg = <0x0 0xfd8a0000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
|
|
|
++ gpio-controller;
|
|
|
++ gpio-ranges = <&pinctrl 0 0 32>;
|
|
|
++ interrupt-controller;
|
|
|
++ #gpio-cells = <2>;
|
|
|
++ #interrupt-cells = <2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ gpio1: gpio@fec20000 {
|
|
|
++ compatible = "rockchip,gpio-bank";
|
|
|
++ reg = <0x0 0xfec20000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
|
|
++ gpio-controller;
|
|
|
++ gpio-ranges = <&pinctrl 0 32 32>;
|
|
|
++ interrupt-controller;
|
|
|
++ #gpio-cells = <2>;
|
|
|
++ #interrupt-cells = <2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ gpio2: gpio@fec30000 {
|
|
|
++ compatible = "rockchip,gpio-bank";
|
|
|
++ reg = <0x0 0xfec30000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
|
|
++ gpio-controller;
|
|
|
++ gpio-ranges = <&pinctrl 0 64 32>;
|
|
|
++ interrupt-controller;
|
|
|
++ #gpio-cells = <2>;
|
|
|
++ #interrupt-cells = <2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ gpio3: gpio@fec40000 {
|
|
|
++ compatible = "rockchip,gpio-bank";
|
|
|
++ reg = <0x0 0xfec40000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
|
|
++ gpio-controller;
|
|
|
++ gpio-ranges = <&pinctrl 0 96 32>;
|
|
|
++ interrupt-controller;
|
|
|
++ #gpio-cells = <2>;
|
|
|
++ #interrupt-cells = <2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ gpio4: gpio@fec50000 {
|
|
|
++ compatible = "rockchip,gpio-bank";
|
|
|
++ reg = <0x0 0xfec50000 0x0 0x100>;
|
|
|
++ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
|
|
++ gpio-controller;
|
|
|
++ gpio-ranges = <&pinctrl 0 128 32>;
|
|
|
++ interrupt-controller;
|
|
|
++ #gpio-cells = <2>;
|
|
|
++ #interrupt-cells = <2>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++};
|
|
|
++
|
|
|
++#include "rk3588-base-pinctrl.dtsi"
|
|
|
+--- /dev/null
|
|
|
++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
|
|
|
+@@ -0,0 +1,413 @@
|
|
|
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
|
++/*
|
|
|
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
|
|
++ */
|
|
|
++
|
|
|
++#include "rk3588-base.dtsi"
|
|
|
++#include "rk3588-extra-pinctrl.dtsi"
|
|
|
++
|
|
|
++/ {
|
|
|
++ usb_host1_xhci: usb@fc400000 {
|
|
|
++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
|
|
++ reg = <0x0 0xfc400000 0x0 0x400000>;
|
|
|
++ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
|
|
|
++ <&cru ACLK_USB3OTG1>;
|
|
|
++ clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
|
|
++ dr_mode = "otg";
|
|
|
++ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
|
|
|
++ phy-names = "usb2-phy", "usb3-phy";
|
|
|
++ phy_type = "utmi_wide";
|
|
|
++ power-domains = <&power RK3588_PD_USB>;
|
|
|
++ resets = <&cru SRST_A_USB3OTG1>;
|
|
|
++ snps,dis_enblslpm_quirk;
|
|
|
++ snps,dis-u2-freeclk-exists-quirk;
|
|
|
++ snps,dis-del-phy-power-chg-quirk;
|
|
|
++ snps,dis-tx-ipgap-linecheck-quirk;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie30_phy_grf: syscon@fd5b8000 {
|
|
|
++ compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5b8000 0x0 0x10000>;
|
|
|
++ };
|
|
|
++
|
|
|
++ pipe_phy1_grf: syscon@fd5c0000 {
|
|
|
++ compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5c0000 0x0 0x100>;
|
|
|
++ };
|
|
|
++
|
|
|
++ usbdpphy1_grf: syscon@fd5cc000 {
|
|
|
++ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
|
|
++ reg = <0x0 0xfd5cc000 0x0 0x4000>;
|
|
|
++ };
|
|
|
++
|
|
|
++ usb2phy1_grf: syscon@fd5d4000 {
|
|
|
++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
|
|
++ reg = <0x0 0xfd5d4000 0x0 0x4000>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <1>;
|
|
|
++
|
|
|
++ u2phy1: usb2phy@4000 {
|
|
|
++ compatible = "rockchip,rk3588-usb2phy";
|
|
|
++ reg = <0x4000 0x10>;
|
|
|
++ #clock-cells = <0>;
|
|
|
++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
|
|
++ clock-names = "phyclk";
|
|
|
++ clock-output-names = "usb480m_phy1";
|
|
|
++ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
|
|
|
++ reset-names = "phy", "apb";
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ u2phy1_otg: otg-port {
|
|
|
++ #phy-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s8_8ch: i2s@fddc8000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
++ reg = <0x0 0xfddc8000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
|
|
|
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
++ assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
|
|
|
++ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
++ dmas = <&dmac2 22>;
|
|
|
++ dma-names = "tx";
|
|
|
++ power-domains = <&power RK3588_PD_VO0>;
|
|
|
++ resets = <&cru SRST_M_I2S8_8CH_TX>;
|
|
|
++ reset-names = "tx-m";
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s6_8ch: i2s@fddf4000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
++ reg = <0x0 0xfddf4000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
|
|
|
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
++ assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
|
|
|
++ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
++ dmas = <&dmac2 4>;
|
|
|
++ dma-names = "tx";
|
|
|
++ power-domains = <&power RK3588_PD_VO1>;
|
|
|
++ resets = <&cru SRST_M_I2S6_8CH_TX>;
|
|
|
++ reset-names = "tx-m";
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s7_8ch: i2s@fddf8000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
++ reg = <0x0 0xfddf8000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
|
|
|
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
++ assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
|
|
|
++ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
++ dmas = <&dmac2 21>;
|
|
|
++ dma-names = "rx";
|
|
|
++ power-domains = <&power RK3588_PD_VO1>;
|
|
|
++ resets = <&cru SRST_M_I2S7_8CH_RX>;
|
|
|
++ reset-names = "rx-m";
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s10_8ch: i2s@fde00000 {
|
|
|
++ compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
++ reg = <0x0 0xfde00000 0x0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
|
|
|
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
++ assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
|
|
|
++ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
++ dmas = <&dmac2 24>;
|
|
|
++ dma-names = "rx";
|
|
|
++ power-domains = <&power RK3588_PD_VO1>;
|
|
|
++ resets = <&cru SRST_M_I2S10_8CH_RX>;
|
|
|
++ reset-names = "rx-m";
|
|
|
++ #sound-dai-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie3x4: pcie@fe150000 {
|
|
|
++ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
|
++ #address-cells = <3>;
|
|
|
++ #size-cells = <2>;
|
|
|
++ bus-range = <0x00 0x0f>;
|
|
|
++ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
|
|
|
++ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
|
|
|
++ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
|
|
|
++ clock-names = "aclk_mst", "aclk_slv",
|
|
|
++ "aclk_dbi", "pclk",
|
|
|
++ "aux", "pipe";
|
|
|
++ device_type = "pci";
|
|
|
++ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
|
++ #interrupt-cells = <1>;
|
|
|
++ interrupt-map-mask = <0 0 0 7>;
|
|
|
++ interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
|
|
|
++ <0 0 0 2 &pcie3x4_intc 1>,
|
|
|
++ <0 0 0 3 &pcie3x4_intc 2>,
|
|
|
++ <0 0 0 4 &pcie3x4_intc 3>;
|
|
|
++ linux,pci-domain = <0>;
|
|
|
++ max-link-speed = <3>;
|
|
|
++ msi-map = <0x0000 &its1 0x0000 0x1000>;
|
|
|
++ num-lanes = <4>;
|
|
|
++ phys = <&pcie30phy>;
|
|
|
++ phy-names = "pcie-phy";
|
|
|
++ power-domains = <&power RK3588_PD_PCIE>;
|
|
|
++ ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
|
|
|
++ <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
|
|
|
++ <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
|
|
|
++ reg = <0xa 0x40000000 0x0 0x00400000>,
|
|
|
++ <0x0 0xfe150000 0x0 0x00010000>,
|
|
|
++ <0x0 0xf0000000 0x0 0x00100000>;
|
|
|
++ reg-names = "dbi", "apb", "config";
|
|
|
++ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
|
|
++ reset-names = "pwr", "pipe";
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ pcie3x4_intc: legacy-interrupt-controller {
|
|
|
++ interrupt-controller;
|
|
|
++ #address-cells = <0>;
|
|
|
++ #interrupt-cells = <1>;
|
|
|
++ interrupt-parent = <&gic>;
|
|
|
++ interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie3x2: pcie@fe160000 {
|
|
|
++ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
|
++ #address-cells = <3>;
|
|
|
++ #size-cells = <2>;
|
|
|
++ bus-range = <0x10 0x1f>;
|
|
|
++ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
|
|
|
++ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
|
|
|
++ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
|
|
|
++ clock-names = "aclk_mst", "aclk_slv",
|
|
|
++ "aclk_dbi", "pclk",
|
|
|
++ "aux", "pipe";
|
|
|
++ device_type = "pci";
|
|
|
++ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
|
++ #interrupt-cells = <1>;
|
|
|
++ interrupt-map-mask = <0 0 0 7>;
|
|
|
++ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
|
|
++ <0 0 0 2 &pcie3x2_intc 1>,
|
|
|
++ <0 0 0 3 &pcie3x2_intc 2>,
|
|
|
++ <0 0 0 4 &pcie3x2_intc 3>;
|
|
|
++ linux,pci-domain = <1>;
|
|
|
++ max-link-speed = <3>;
|
|
|
++ msi-map = <0x1000 &its1 0x1000 0x1000>;
|
|
|
++ num-lanes = <2>;
|
|
|
++ phys = <&pcie30phy>;
|
|
|
++ phy-names = "pcie-phy";
|
|
|
++ power-domains = <&power RK3588_PD_PCIE>;
|
|
|
++ ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
|
|
|
++ <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
|
|
|
++ <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
|
|
|
++ reg = <0xa 0x40400000 0x0 0x00400000>,
|
|
|
++ <0x0 0xfe160000 0x0 0x00010000>,
|
|
|
++ <0x0 0xf1000000 0x0 0x00100000>;
|
|
|
++ reg-names = "dbi", "apb", "config";
|
|
|
++ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
|
|
++ reset-names = "pwr", "pipe";
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ pcie3x2_intc: legacy-interrupt-controller {
|
|
|
++ interrupt-controller;
|
|
|
++ #address-cells = <0>;
|
|
|
++ #interrupt-cells = <1>;
|
|
|
++ interrupt-parent = <&gic>;
|
|
|
++ interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie2x1l0: pcie@fe170000 {
|
|
|
++ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
|
++ bus-range = <0x20 0x2f>;
|
|
|
++ clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
|
|
|
++ <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
|
|
|
++ <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
|
|
|
++ clock-names = "aclk_mst", "aclk_slv",
|
|
|
++ "aclk_dbi", "pclk",
|
|
|
++ "aux", "pipe";
|
|
|
++ device_type = "pci";
|
|
|
++ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
|
++ #interrupt-cells = <1>;
|
|
|
++ interrupt-map-mask = <0 0 0 7>;
|
|
|
++ interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
|
|
|
++ <0 0 0 2 &pcie2x1l0_intc 1>,
|
|
|
++ <0 0 0 3 &pcie2x1l0_intc 2>,
|
|
|
++ <0 0 0 4 &pcie2x1l0_intc 3>;
|
|
|
++ linux,pci-domain = <2>;
|
|
|
++ max-link-speed = <2>;
|
|
|
++ msi-map = <0x2000 &its0 0x2000 0x1000>;
|
|
|
++ num-lanes = <1>;
|
|
|
++ phys = <&combphy1_ps PHY_TYPE_PCIE>;
|
|
|
++ phy-names = "pcie-phy";
|
|
|
++ power-domains = <&power RK3588_PD_PCIE>;
|
|
|
++ ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
|
|
|
++ <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
|
|
|
++ <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
|
|
|
++ reg = <0xa 0x40800000 0x0 0x00400000>,
|
|
|
++ <0x0 0xfe170000 0x0 0x00010000>,
|
|
|
++ <0x0 0xf2000000 0x0 0x00100000>;
|
|
|
++ reg-names = "dbi", "apb", "config";
|
|
|
++ resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
|
|
|
++ reset-names = "pwr", "pipe";
|
|
|
++ #address-cells = <3>;
|
|
|
++ #size-cells = <2>;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ pcie2x1l0_intc: legacy-interrupt-controller {
|
|
|
++ interrupt-controller;
|
|
|
++ #address-cells = <0>;
|
|
|
++ #interrupt-cells = <1>;
|
|
|
++ interrupt-parent = <&gic>;
|
|
|
++ interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ gmac0: ethernet@fe1b0000 {
|
|
|
++ compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
|
|
++ reg = <0x0 0xfe1b0000 0x0 0x10000>;
|
|
|
++ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
++ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ interrupt-names = "macirq", "eth_wake_irq";
|
|
|
++ clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
|
|
|
++ <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
|
|
|
++ <&cru CLK_GMAC0_PTP_REF>;
|
|
|
++ clock-names = "stmmaceth", "clk_mac_ref",
|
|
|
++ "pclk_mac", "aclk_mac",
|
|
|
++ "ptp_ref";
|
|
|
++ power-domains = <&power RK3588_PD_GMAC>;
|
|
|
++ resets = <&cru SRST_A_GMAC0>;
|
|
|
++ reset-names = "stmmaceth";
|
|
|
++ rockchip,grf = <&sys_grf>;
|
|
|
++ rockchip,php-grf = <&php_grf>;
|
|
|
++ snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
|
|
++ snps,mixed-burst;
|
|
|
++ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
|
|
++ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
|
|
++ snps,tso;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ mdio0: mdio {
|
|
|
++ compatible = "snps,dwmac-mdio";
|
|
|
++ #address-cells = <0x1>;
|
|
|
++ #size-cells = <0x0>;
|
|
|
++ };
|
|
|
++
|
|
|
++ gmac0_stmmac_axi_setup: stmmac-axi-config {
|
|
|
++ snps,blen = <0 0 0 0 16 8 4>;
|
|
|
++ snps,wr_osr_lmt = <4>;
|
|
|
++ snps,rd_osr_lmt = <8>;
|
|
|
++ };
|
|
|
++
|
|
|
++ gmac0_mtl_rx_setup: rx-queues-config {
|
|
|
++ snps,rx-queues-to-use = <2>;
|
|
|
++ queue0 {};
|
|
|
++ queue1 {};
|
|
|
++ };
|
|
|
++
|
|
|
++ gmac0_mtl_tx_setup: tx-queues-config {
|
|
|
++ snps,tx-queues-to-use = <2>;
|
|
|
++ queue0 {};
|
|
|
++ queue1 {};
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ sata1: sata@fe220000 {
|
|
|
++ compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
|
|
++ reg = <0 0xfe220000 0 0x1000>;
|
|
|
++ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
++ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
|
|
|
++ <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
|
|
|
++ <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
|
|
|
++ clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
|
|
++ ports-implemented = <0x1>;
|
|
|
++ #address-cells = <1>;
|
|
|
++ #size-cells = <0>;
|
|
|
++ status = "disabled";
|
|
|
++
|
|
|
++ sata-port@0 {
|
|
|
++ reg = <0>;
|
|
|
++ hba-port-cap = <HBA_PORT_FBSCP>;
|
|
|
++ phys = <&combphy1_ps PHY_TYPE_SATA>;
|
|
|
++ phy-names = "sata-phy";
|
|
|
++ snps,rx-ts-max = <32>;
|
|
|
++ snps,tx-ts-max = <32>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ usbdp_phy1: phy@fed90000 {
|
|
|
++ compatible = "rockchip,rk3588-usbdp-phy";
|
|
|
++ reg = <0x0 0xfed90000 0x0 0x10000>;
|
|
|
++ #phy-cells = <1>;
|
|
|
++ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
|
|
++ <&cru CLK_USBDP_PHY1_IMMORTAL>,
|
|
|
++ <&cru PCLK_USBDPPHY1>,
|
|
|
++ <&u2phy1>;
|
|
|
++ clock-names = "refclk", "immortal", "pclk", "utmi";
|
|
|
++ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
|
|
|
++ <&cru SRST_USBDP_COMBO_PHY1_CMN>,
|
|
|
++ <&cru SRST_USBDP_COMBO_PHY1_LANE>,
|
|
|
++ <&cru SRST_USBDP_COMBO_PHY1_PCS>,
|
|
|
++ <&cru SRST_P_USBDPPHY1>;
|
|
|
++ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
|
|
++ rockchip,u2phy-grf = <&usb2phy1_grf>;
|
|
|
++ rockchip,usb-grf = <&usb_grf>;
|
|
|
++ rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
|
|
|
++ rockchip,vo-grf = <&vo0_grf>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ combphy1_ps: phy@fee10000 {
|
|
|
++ compatible = "rockchip,rk3588-naneng-combphy";
|
|
|
++ reg = <0x0 0xfee10000 0x0 0x100>;
|
|
|
++ clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
|
|
|
++ <&cru PCLK_PHP_ROOT>;
|
|
|
++ clock-names = "ref", "apb", "pipe";
|
|
|
++ assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
|
|
|
++ assigned-clock-rates = <100000000>;
|
|
|
++ #phy-cells = <1>;
|
|
|
++ resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
|
|
|
++ reset-names = "phy", "apb";
|
|
|
++ rockchip,pipe-grf = <&php_grf>;
|
|
|
++ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie30phy: phy@fee80000 {
|
|
|
++ compatible = "rockchip,rk3588-pcie3-phy";
|
|
|
++ reg = <0x0 0xfee80000 0x0 0x20000>;
|
|
|
++ #phy-cells = <0>;
|
|
|
++ clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
|
|
|
++ clock-names = "pclk";
|
|
|
++ resets = <&cru SRST_PCIE30_PHY>;
|
|
|
++ reset-names = "phy";
|
|
|
++ rockchip,pipe-grf = <&php_grf>;
|
|
|
++ rockchip,phy-grf = <&pcie30_phy_grf>;
|
|
|
++ status = "disabled";
|
|
|
++ };
|
|
|
++};
|
|
|
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
|
|
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
|
|
|
+@@ -1,413 +1,7 @@
|
|
|
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
|
+ /*
|
|
|
+- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
|
|
++ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
|
|
++ *
|
|
|
+ */
|
|
|
+
|
|
|
+-#include "rk3588s.dtsi"
|
|
|
+-#include "rk3588-pinctrl.dtsi"
|
|
|
+-
|
|
|
+-/ {
|
|
|
+- usb_host1_xhci: usb@fc400000 {
|
|
|
+- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
|
|
+- reg = <0x0 0xfc400000 0x0 0x400000>;
|
|
|
+- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
|
|
|
+- <&cru ACLK_USB3OTG1>;
|
|
|
+- clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
|
|
+- dr_mode = "otg";
|
|
|
+- phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
|
|
|
+- phy-names = "usb2-phy", "usb3-phy";
|
|
|
+- phy_type = "utmi_wide";
|
|
|
+- power-domains = <&power RK3588_PD_USB>;
|
|
|
+- resets = <&cru SRST_A_USB3OTG1>;
|
|
|
+- snps,dis_enblslpm_quirk;
|
|
|
+- snps,dis-u2-freeclk-exists-quirk;
|
|
|
+- snps,dis-del-phy-power-chg-quirk;
|
|
|
+- snps,dis-tx-ipgap-linecheck-quirk;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie30_phy_grf: syscon@fd5b8000 {
|
|
|
+- compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5b8000 0x0 0x10000>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- pipe_phy1_grf: syscon@fd5c0000 {
|
|
|
+- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5c0000 0x0 0x100>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- usbdpphy1_grf: syscon@fd5cc000 {
|
|
|
+- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5cc000 0x0 0x4000>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb2phy1_grf: syscon@fd5d4000 {
|
|
|
+- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
|
|
+- reg = <0x0 0xfd5d4000 0x0 0x4000>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <1>;
|
|
|
+-
|
|
|
+- u2phy1: usb2phy@4000 {
|
|
|
+- compatible = "rockchip,rk3588-usb2phy";
|
|
|
+- reg = <0x4000 0x10>;
|
|
|
+- #clock-cells = <0>;
|
|
|
+- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
|
|
+- clock-names = "phyclk";
|
|
|
+- clock-output-names = "usb480m_phy1";
|
|
|
+- interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
|
|
|
+- reset-names = "phy", "apb";
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- u2phy1_otg: otg-port {
|
|
|
+- #phy-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s8_8ch: i2s@fddc8000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
+- reg = <0x0 0xfddc8000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
|
|
|
+- clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
+- assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
|
|
|
+- assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
+- dmas = <&dmac2 22>;
|
|
|
+- dma-names = "tx";
|
|
|
+- power-domains = <&power RK3588_PD_VO0>;
|
|
|
+- resets = <&cru SRST_M_I2S8_8CH_TX>;
|
|
|
+- reset-names = "tx-m";
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s6_8ch: i2s@fddf4000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
+- reg = <0x0 0xfddf4000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
|
|
|
+- clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
+- assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
|
|
|
+- assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
+- dmas = <&dmac2 4>;
|
|
|
+- dma-names = "tx";
|
|
|
+- power-domains = <&power RK3588_PD_VO1>;
|
|
|
+- resets = <&cru SRST_M_I2S6_8CH_TX>;
|
|
|
+- reset-names = "tx-m";
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s7_8ch: i2s@fddf8000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
+- reg = <0x0 0xfddf8000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
|
|
|
+- clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
+- assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
|
|
|
+- assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
+- dmas = <&dmac2 21>;
|
|
|
+- dma-names = "rx";
|
|
|
+- power-domains = <&power RK3588_PD_VO1>;
|
|
|
+- resets = <&cru SRST_M_I2S7_8CH_RX>;
|
|
|
+- reset-names = "rx-m";
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s10_8ch: i2s@fde00000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
+- reg = <0x0 0xfde00000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
|
|
|
+- clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
+- assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
|
|
|
+- assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
+- dmas = <&dmac2 24>;
|
|
|
+- dma-names = "rx";
|
|
|
+- power-domains = <&power RK3588_PD_VO1>;
|
|
|
+- resets = <&cru SRST_M_I2S10_8CH_RX>;
|
|
|
+- reset-names = "rx-m";
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie3x4: pcie@fe150000 {
|
|
|
+- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
|
+- #address-cells = <3>;
|
|
|
+- #size-cells = <2>;
|
|
|
+- bus-range = <0x00 0x0f>;
|
|
|
+- clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
|
|
|
+- <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
|
|
|
+- <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
|
|
|
+- clock-names = "aclk_mst", "aclk_slv",
|
|
|
+- "aclk_dbi", "pclk",
|
|
|
+- "aux", "pipe";
|
|
|
+- device_type = "pci";
|
|
|
+- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
|
+- #interrupt-cells = <1>;
|
|
|
+- interrupt-map-mask = <0 0 0 7>;
|
|
|
+- interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
|
|
|
+- <0 0 0 2 &pcie3x4_intc 1>,
|
|
|
+- <0 0 0 3 &pcie3x4_intc 2>,
|
|
|
+- <0 0 0 4 &pcie3x4_intc 3>;
|
|
|
+- linux,pci-domain = <0>;
|
|
|
+- max-link-speed = <3>;
|
|
|
+- msi-map = <0x0000 &its1 0x0000 0x1000>;
|
|
|
+- num-lanes = <4>;
|
|
|
+- phys = <&pcie30phy>;
|
|
|
+- phy-names = "pcie-phy";
|
|
|
+- power-domains = <&power RK3588_PD_PCIE>;
|
|
|
+- ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
|
|
|
+- <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
|
|
|
+- <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
|
|
|
+- reg = <0xa 0x40000000 0x0 0x00400000>,
|
|
|
+- <0x0 0xfe150000 0x0 0x00010000>,
|
|
|
+- <0x0 0xf0000000 0x0 0x00100000>;
|
|
|
+- reg-names = "dbi", "apb", "config";
|
|
|
+- resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
|
|
+- reset-names = "pwr", "pipe";
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- pcie3x4_intc: legacy-interrupt-controller {
|
|
|
+- interrupt-controller;
|
|
|
+- #address-cells = <0>;
|
|
|
+- #interrupt-cells = <1>;
|
|
|
+- interrupt-parent = <&gic>;
|
|
|
+- interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie3x2: pcie@fe160000 {
|
|
|
+- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
|
+- #address-cells = <3>;
|
|
|
+- #size-cells = <2>;
|
|
|
+- bus-range = <0x10 0x1f>;
|
|
|
+- clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
|
|
|
+- <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
|
|
|
+- <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
|
|
|
+- clock-names = "aclk_mst", "aclk_slv",
|
|
|
+- "aclk_dbi", "pclk",
|
|
|
+- "aux", "pipe";
|
|
|
+- device_type = "pci";
|
|
|
+- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
|
+- #interrupt-cells = <1>;
|
|
|
+- interrupt-map-mask = <0 0 0 7>;
|
|
|
+- interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
|
|
+- <0 0 0 2 &pcie3x2_intc 1>,
|
|
|
+- <0 0 0 3 &pcie3x2_intc 2>,
|
|
|
+- <0 0 0 4 &pcie3x2_intc 3>;
|
|
|
+- linux,pci-domain = <1>;
|
|
|
+- max-link-speed = <3>;
|
|
|
+- msi-map = <0x1000 &its1 0x1000 0x1000>;
|
|
|
+- num-lanes = <2>;
|
|
|
+- phys = <&pcie30phy>;
|
|
|
+- phy-names = "pcie-phy";
|
|
|
+- power-domains = <&power RK3588_PD_PCIE>;
|
|
|
+- ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
|
|
|
+- <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
|
|
|
+- <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
|
|
|
+- reg = <0xa 0x40400000 0x0 0x00400000>,
|
|
|
+- <0x0 0xfe160000 0x0 0x00010000>,
|
|
|
+- <0x0 0xf1000000 0x0 0x00100000>;
|
|
|
+- reg-names = "dbi", "apb", "config";
|
|
|
+- resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
|
|
+- reset-names = "pwr", "pipe";
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- pcie3x2_intc: legacy-interrupt-controller {
|
|
|
+- interrupt-controller;
|
|
|
+- #address-cells = <0>;
|
|
|
+- #interrupt-cells = <1>;
|
|
|
+- interrupt-parent = <&gic>;
|
|
|
+- interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie2x1l0: pcie@fe170000 {
|
|
|
+- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
|
+- bus-range = <0x20 0x2f>;
|
|
|
+- clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
|
|
|
+- <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
|
|
|
+- <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
|
|
|
+- clock-names = "aclk_mst", "aclk_slv",
|
|
|
+- "aclk_dbi", "pclk",
|
|
|
+- "aux", "pipe";
|
|
|
+- device_type = "pci";
|
|
|
+- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
|
+- #interrupt-cells = <1>;
|
|
|
+- interrupt-map-mask = <0 0 0 7>;
|
|
|
+- interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
|
|
|
+- <0 0 0 2 &pcie2x1l0_intc 1>,
|
|
|
+- <0 0 0 3 &pcie2x1l0_intc 2>,
|
|
|
+- <0 0 0 4 &pcie2x1l0_intc 3>;
|
|
|
+- linux,pci-domain = <2>;
|
|
|
+- max-link-speed = <2>;
|
|
|
+- msi-map = <0x2000 &its0 0x2000 0x1000>;
|
|
|
+- num-lanes = <1>;
|
|
|
+- phys = <&combphy1_ps PHY_TYPE_PCIE>;
|
|
|
+- phy-names = "pcie-phy";
|
|
|
+- power-domains = <&power RK3588_PD_PCIE>;
|
|
|
+- ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
|
|
|
+- <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
|
|
|
+- <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
|
|
|
+- reg = <0xa 0x40800000 0x0 0x00400000>,
|
|
|
+- <0x0 0xfe170000 0x0 0x00010000>,
|
|
|
+- <0x0 0xf2000000 0x0 0x00100000>;
|
|
|
+- reg-names = "dbi", "apb", "config";
|
|
|
+- resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
|
|
|
+- reset-names = "pwr", "pipe";
|
|
|
+- #address-cells = <3>;
|
|
|
+- #size-cells = <2>;
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- pcie2x1l0_intc: legacy-interrupt-controller {
|
|
|
+- interrupt-controller;
|
|
|
+- #address-cells = <0>;
|
|
|
+- #interrupt-cells = <1>;
|
|
|
+- interrupt-parent = <&gic>;
|
|
|
+- interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- gmac0: ethernet@fe1b0000 {
|
|
|
+- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
|
|
+- reg = <0x0 0xfe1b0000 0x0 0x10000>;
|
|
|
+- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "macirq", "eth_wake_irq";
|
|
|
+- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
|
|
|
+- <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
|
|
|
+- <&cru CLK_GMAC0_PTP_REF>;
|
|
|
+- clock-names = "stmmaceth", "clk_mac_ref",
|
|
|
+- "pclk_mac", "aclk_mac",
|
|
|
+- "ptp_ref";
|
|
|
+- power-domains = <&power RK3588_PD_GMAC>;
|
|
|
+- resets = <&cru SRST_A_GMAC0>;
|
|
|
+- reset-names = "stmmaceth";
|
|
|
+- rockchip,grf = <&sys_grf>;
|
|
|
+- rockchip,php-grf = <&php_grf>;
|
|
|
+- snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
|
|
+- snps,mixed-burst;
|
|
|
+- snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
|
|
+- snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
|
|
+- snps,tso;
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- mdio0: mdio {
|
|
|
+- compatible = "snps,dwmac-mdio";
|
|
|
+- #address-cells = <0x1>;
|
|
|
+- #size-cells = <0x0>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- gmac0_stmmac_axi_setup: stmmac-axi-config {
|
|
|
+- snps,blen = <0 0 0 0 16 8 4>;
|
|
|
+- snps,wr_osr_lmt = <4>;
|
|
|
+- snps,rd_osr_lmt = <8>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- gmac0_mtl_rx_setup: rx-queues-config {
|
|
|
+- snps,rx-queues-to-use = <2>;
|
|
|
+- queue0 {};
|
|
|
+- queue1 {};
|
|
|
+- };
|
|
|
+-
|
|
|
+- gmac0_mtl_tx_setup: tx-queues-config {
|
|
|
+- snps,tx-queues-to-use = <2>;
|
|
|
+- queue0 {};
|
|
|
+- queue1 {};
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sata1: sata@fe220000 {
|
|
|
+- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
|
|
+- reg = <0 0xfe220000 0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
|
|
|
+- <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
|
|
|
+- <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
|
|
|
+- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
|
|
+- ports-implemented = <0x1>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- sata-port@0 {
|
|
|
+- reg = <0>;
|
|
|
+- hba-port-cap = <HBA_PORT_FBSCP>;
|
|
|
+- phys = <&combphy1_ps PHY_TYPE_SATA>;
|
|
|
+- phy-names = "sata-phy";
|
|
|
+- snps,rx-ts-max = <32>;
|
|
|
+- snps,tx-ts-max = <32>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- usbdp_phy1: phy@fed90000 {
|
|
|
+- compatible = "rockchip,rk3588-usbdp-phy";
|
|
|
+- reg = <0x0 0xfed90000 0x0 0x10000>;
|
|
|
+- #phy-cells = <1>;
|
|
|
+- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
|
|
+- <&cru CLK_USBDP_PHY1_IMMORTAL>,
|
|
|
+- <&cru PCLK_USBDPPHY1>,
|
|
|
+- <&u2phy1>;
|
|
|
+- clock-names = "refclk", "immortal", "pclk", "utmi";
|
|
|
+- resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
|
|
|
+- <&cru SRST_USBDP_COMBO_PHY1_CMN>,
|
|
|
+- <&cru SRST_USBDP_COMBO_PHY1_LANE>,
|
|
|
+- <&cru SRST_USBDP_COMBO_PHY1_PCS>,
|
|
|
+- <&cru SRST_P_USBDPPHY1>;
|
|
|
+- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
|
|
+- rockchip,u2phy-grf = <&usb2phy1_grf>;
|
|
|
+- rockchip,usb-grf = <&usb_grf>;
|
|
|
+- rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
|
|
|
+- rockchip,vo-grf = <&vo0_grf>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- combphy1_ps: phy@fee10000 {
|
|
|
+- compatible = "rockchip,rk3588-naneng-combphy";
|
|
|
+- reg = <0x0 0xfee10000 0x0 0x100>;
|
|
|
+- clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
|
|
|
+- <&cru PCLK_PHP_ROOT>;
|
|
|
+- clock-names = "ref", "apb", "pipe";
|
|
|
+- assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
|
|
|
+- assigned-clock-rates = <100000000>;
|
|
|
+- #phy-cells = <1>;
|
|
|
+- resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
|
|
|
+- reset-names = "phy", "apb";
|
|
|
+- rockchip,pipe-grf = <&php_grf>;
|
|
|
+- rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie30phy: phy@fee80000 {
|
|
|
+- compatible = "rockchip,rk3588-pcie3-phy";
|
|
|
+- reg = <0x0 0xfee80000 0x0 0x20000>;
|
|
|
+- #phy-cells = <0>;
|
|
|
+- clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
|
|
|
+- clock-names = "pclk";
|
|
|
+- resets = <&cru SRST_PCIE30_PHY>;
|
|
|
+- reset-names = "phy";
|
|
|
+- rockchip,pipe-grf = <&php_grf>;
|
|
|
+- rockchip,phy-grf = <&pcie30_phy_grf>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-};
|
|
|
++#include "rk3588-extra.dtsi"
|
|
|
+--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
|
|
|
++++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
|
|
|
+@@ -4,4 +4,4 @@
|
|
|
+ *
|
|
|
+ */
|
|
|
+
|
|
|
+-#include "rk3588.dtsi"
|
|
|
++#include "rk3588-extra.dtsi"
|
|
|
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
|
|
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
|
|
|
+@@ -1,2670 +1,7 @@
|
|
|
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
|
+ /*
|
|
|
+- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
|
|
++ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
|
|
++ *
|
|
|
+ */
|
|
|
+
|
|
|
+-#include <dt-bindings/clock/rockchip,rk3588-cru.h>
|
|
|
+-#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
+-#include <dt-bindings/interrupt-controller/irq.h>
|
|
|
+-#include <dt-bindings/power/rk3588-power.h>
|
|
|
+-#include <dt-bindings/reset/rockchip,rk3588-cru.h>
|
|
|
+-#include <dt-bindings/phy/phy.h>
|
|
|
+-#include <dt-bindings/ata/ahci.h>
|
|
|
+-
|
|
|
+-/ {
|
|
|
+- compatible = "rockchip,rk3588";
|
|
|
+-
|
|
|
+- interrupt-parent = <&gic>;
|
|
|
+- #address-cells = <2>;
|
|
|
+- #size-cells = <2>;
|
|
|
+-
|
|
|
+- aliases {
|
|
|
+- gpio0 = &gpio0;
|
|
|
+- gpio1 = &gpio1;
|
|
|
+- gpio2 = &gpio2;
|
|
|
+- gpio3 = &gpio3;
|
|
|
+- gpio4 = &gpio4;
|
|
|
+- i2c0 = &i2c0;
|
|
|
+- i2c1 = &i2c1;
|
|
|
+- i2c2 = &i2c2;
|
|
|
+- i2c3 = &i2c3;
|
|
|
+- i2c4 = &i2c4;
|
|
|
+- i2c5 = &i2c5;
|
|
|
+- i2c6 = &i2c6;
|
|
|
+- i2c7 = &i2c7;
|
|
|
+- i2c8 = &i2c8;
|
|
|
+- serial0 = &uart0;
|
|
|
+- serial1 = &uart1;
|
|
|
+- serial2 = &uart2;
|
|
|
+- serial3 = &uart3;
|
|
|
+- serial4 = &uart4;
|
|
|
+- serial5 = &uart5;
|
|
|
+- serial6 = &uart6;
|
|
|
+- serial7 = &uart7;
|
|
|
+- serial8 = &uart8;
|
|
|
+- serial9 = &uart9;
|
|
|
+- spi0 = &spi0;
|
|
|
+- spi1 = &spi1;
|
|
|
+- spi2 = &spi2;
|
|
|
+- spi3 = &spi3;
|
|
|
+- spi4 = &spi4;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpus {
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+-
|
|
|
+- cpu-map {
|
|
|
+- cluster0 {
|
|
|
+- core0 {
|
|
|
+- cpu = <&cpu_l0>;
|
|
|
+- };
|
|
|
+- core1 {
|
|
|
+- cpu = <&cpu_l1>;
|
|
|
+- };
|
|
|
+- core2 {
|
|
|
+- cpu = <&cpu_l2>;
|
|
|
+- };
|
|
|
+- core3 {
|
|
|
+- cpu = <&cpu_l3>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- cluster1 {
|
|
|
+- core0 {
|
|
|
+- cpu = <&cpu_b0>;
|
|
|
+- };
|
|
|
+- core1 {
|
|
|
+- cpu = <&cpu_b1>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- cluster2 {
|
|
|
+- core0 {
|
|
|
+- cpu = <&cpu_b2>;
|
|
|
+- };
|
|
|
+- core1 {
|
|
|
+- cpu = <&cpu_b3>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpu_l0: cpu@0 {
|
|
|
+- device_type = "cpu";
|
|
|
+- compatible = "arm,cortex-a55";
|
|
|
+- reg = <0x0>;
|
|
|
+- enable-method = "psci";
|
|
|
+- capacity-dmips-mhz = <530>;
|
|
|
+- clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
|
|
+- assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
|
|
+- assigned-clock-rates = <816000000>;
|
|
|
+- cpu-idle-states = <&CPU_SLEEP>;
|
|
|
+- i-cache-size = <32768>;
|
|
|
+- i-cache-line-size = <64>;
|
|
|
+- i-cache-sets = <128>;
|
|
|
+- d-cache-size = <32768>;
|
|
|
+- d-cache-line-size = <64>;
|
|
|
+- d-cache-sets = <128>;
|
|
|
+- next-level-cache = <&l2_cache_l0>;
|
|
|
+- dynamic-power-coefficient = <228>;
|
|
|
+- #cooling-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpu_l1: cpu@100 {
|
|
|
+- device_type = "cpu";
|
|
|
+- compatible = "arm,cortex-a55";
|
|
|
+- reg = <0x100>;
|
|
|
+- enable-method = "psci";
|
|
|
+- capacity-dmips-mhz = <530>;
|
|
|
+- clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
|
|
+- cpu-idle-states = <&CPU_SLEEP>;
|
|
|
+- i-cache-size = <32768>;
|
|
|
+- i-cache-line-size = <64>;
|
|
|
+- i-cache-sets = <128>;
|
|
|
+- d-cache-size = <32768>;
|
|
|
+- d-cache-line-size = <64>;
|
|
|
+- d-cache-sets = <128>;
|
|
|
+- next-level-cache = <&l2_cache_l1>;
|
|
|
+- dynamic-power-coefficient = <228>;
|
|
|
+- #cooling-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpu_l2: cpu@200 {
|
|
|
+- device_type = "cpu";
|
|
|
+- compatible = "arm,cortex-a55";
|
|
|
+- reg = <0x200>;
|
|
|
+- enable-method = "psci";
|
|
|
+- capacity-dmips-mhz = <530>;
|
|
|
+- clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
|
|
+- cpu-idle-states = <&CPU_SLEEP>;
|
|
|
+- i-cache-size = <32768>;
|
|
|
+- i-cache-line-size = <64>;
|
|
|
+- i-cache-sets = <128>;
|
|
|
+- d-cache-size = <32768>;
|
|
|
+- d-cache-line-size = <64>;
|
|
|
+- d-cache-sets = <128>;
|
|
|
+- next-level-cache = <&l2_cache_l2>;
|
|
|
+- dynamic-power-coefficient = <228>;
|
|
|
+- #cooling-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpu_l3: cpu@300 {
|
|
|
+- device_type = "cpu";
|
|
|
+- compatible = "arm,cortex-a55";
|
|
|
+- reg = <0x300>;
|
|
|
+- enable-method = "psci";
|
|
|
+- capacity-dmips-mhz = <530>;
|
|
|
+- clocks = <&scmi_clk SCMI_CLK_CPUL>;
|
|
|
+- cpu-idle-states = <&CPU_SLEEP>;
|
|
|
+- i-cache-size = <32768>;
|
|
|
+- i-cache-line-size = <64>;
|
|
|
+- i-cache-sets = <128>;
|
|
|
+- d-cache-size = <32768>;
|
|
|
+- d-cache-line-size = <64>;
|
|
|
+- d-cache-sets = <128>;
|
|
|
+- next-level-cache = <&l2_cache_l3>;
|
|
|
+- dynamic-power-coefficient = <228>;
|
|
|
+- #cooling-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpu_b0: cpu@400 {
|
|
|
+- device_type = "cpu";
|
|
|
+- compatible = "arm,cortex-a76";
|
|
|
+- reg = <0x400>;
|
|
|
+- enable-method = "psci";
|
|
|
+- capacity-dmips-mhz = <1024>;
|
|
|
+- clocks = <&scmi_clk SCMI_CLK_CPUB01>;
|
|
|
+- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
|
|
|
+- assigned-clock-rates = <816000000>;
|
|
|
+- cpu-idle-states = <&CPU_SLEEP>;
|
|
|
+- i-cache-size = <65536>;
|
|
|
+- i-cache-line-size = <64>;
|
|
|
+- i-cache-sets = <256>;
|
|
|
+- d-cache-size = <65536>;
|
|
|
+- d-cache-line-size = <64>;
|
|
|
+- d-cache-sets = <256>;
|
|
|
+- next-level-cache = <&l2_cache_b0>;
|
|
|
+- dynamic-power-coefficient = <416>;
|
|
|
+- #cooling-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpu_b1: cpu@500 {
|
|
|
+- device_type = "cpu";
|
|
|
+- compatible = "arm,cortex-a76";
|
|
|
+- reg = <0x500>;
|
|
|
+- enable-method = "psci";
|
|
|
+- capacity-dmips-mhz = <1024>;
|
|
|
+- clocks = <&scmi_clk SCMI_CLK_CPUB01>;
|
|
|
+- cpu-idle-states = <&CPU_SLEEP>;
|
|
|
+- i-cache-size = <65536>;
|
|
|
+- i-cache-line-size = <64>;
|
|
|
+- i-cache-sets = <256>;
|
|
|
+- d-cache-size = <65536>;
|
|
|
+- d-cache-line-size = <64>;
|
|
|
+- d-cache-sets = <256>;
|
|
|
+- next-level-cache = <&l2_cache_b1>;
|
|
|
+- dynamic-power-coefficient = <416>;
|
|
|
+- #cooling-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpu_b2: cpu@600 {
|
|
|
+- device_type = "cpu";
|
|
|
+- compatible = "arm,cortex-a76";
|
|
|
+- reg = <0x600>;
|
|
|
+- enable-method = "psci";
|
|
|
+- capacity-dmips-mhz = <1024>;
|
|
|
+- clocks = <&scmi_clk SCMI_CLK_CPUB23>;
|
|
|
+- assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
|
|
|
+- assigned-clock-rates = <816000000>;
|
|
|
+- cpu-idle-states = <&CPU_SLEEP>;
|
|
|
+- i-cache-size = <65536>;
|
|
|
+- i-cache-line-size = <64>;
|
|
|
+- i-cache-sets = <256>;
|
|
|
+- d-cache-size = <65536>;
|
|
|
+- d-cache-line-size = <64>;
|
|
|
+- d-cache-sets = <256>;
|
|
|
+- next-level-cache = <&l2_cache_b2>;
|
|
|
+- dynamic-power-coefficient = <416>;
|
|
|
+- #cooling-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpu_b3: cpu@700 {
|
|
|
+- device_type = "cpu";
|
|
|
+- compatible = "arm,cortex-a76";
|
|
|
+- reg = <0x700>;
|
|
|
+- enable-method = "psci";
|
|
|
+- capacity-dmips-mhz = <1024>;
|
|
|
+- clocks = <&scmi_clk SCMI_CLK_CPUB23>;
|
|
|
+- cpu-idle-states = <&CPU_SLEEP>;
|
|
|
+- i-cache-size = <65536>;
|
|
|
+- i-cache-line-size = <64>;
|
|
|
+- i-cache-sets = <256>;
|
|
|
+- d-cache-size = <65536>;
|
|
|
+- d-cache-line-size = <64>;
|
|
|
+- d-cache-sets = <256>;
|
|
|
+- next-level-cache = <&l2_cache_b3>;
|
|
|
+- dynamic-power-coefficient = <416>;
|
|
|
+- #cooling-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- idle-states {
|
|
|
+- entry-method = "psci";
|
|
|
+- CPU_SLEEP: cpu-sleep {
|
|
|
+- compatible = "arm,idle-state";
|
|
|
+- local-timer-stop;
|
|
|
+- arm,psci-suspend-param = <0x0010000>;
|
|
|
+- entry-latency-us = <100>;
|
|
|
+- exit-latency-us = <120>;
|
|
|
+- min-residency-us = <1000>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- l2_cache_l0: l2-cache-l0 {
|
|
|
+- compatible = "cache";
|
|
|
+- cache-size = <131072>;
|
|
|
+- cache-line-size = <64>;
|
|
|
+- cache-sets = <512>;
|
|
|
+- cache-level = <2>;
|
|
|
+- cache-unified;
|
|
|
+- next-level-cache = <&l3_cache>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- l2_cache_l1: l2-cache-l1 {
|
|
|
+- compatible = "cache";
|
|
|
+- cache-size = <131072>;
|
|
|
+- cache-line-size = <64>;
|
|
|
+- cache-sets = <512>;
|
|
|
+- cache-level = <2>;
|
|
|
+- cache-unified;
|
|
|
+- next-level-cache = <&l3_cache>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- l2_cache_l2: l2-cache-l2 {
|
|
|
+- compatible = "cache";
|
|
|
+- cache-size = <131072>;
|
|
|
+- cache-line-size = <64>;
|
|
|
+- cache-sets = <512>;
|
|
|
+- cache-level = <2>;
|
|
|
+- cache-unified;
|
|
|
+- next-level-cache = <&l3_cache>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- l2_cache_l3: l2-cache-l3 {
|
|
|
+- compatible = "cache";
|
|
|
+- cache-size = <131072>;
|
|
|
+- cache-line-size = <64>;
|
|
|
+- cache-sets = <512>;
|
|
|
+- cache-level = <2>;
|
|
|
+- cache-unified;
|
|
|
+- next-level-cache = <&l3_cache>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- l2_cache_b0: l2-cache-b0 {
|
|
|
+- compatible = "cache";
|
|
|
+- cache-size = <524288>;
|
|
|
+- cache-line-size = <64>;
|
|
|
+- cache-sets = <1024>;
|
|
|
+- cache-level = <2>;
|
|
|
+- cache-unified;
|
|
|
+- next-level-cache = <&l3_cache>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- l2_cache_b1: l2-cache-b1 {
|
|
|
+- compatible = "cache";
|
|
|
+- cache-size = <524288>;
|
|
|
+- cache-line-size = <64>;
|
|
|
+- cache-sets = <1024>;
|
|
|
+- cache-level = <2>;
|
|
|
+- cache-unified;
|
|
|
+- next-level-cache = <&l3_cache>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- l2_cache_b2: l2-cache-b2 {
|
|
|
+- compatible = "cache";
|
|
|
+- cache-size = <524288>;
|
|
|
+- cache-line-size = <64>;
|
|
|
+- cache-sets = <1024>;
|
|
|
+- cache-level = <2>;
|
|
|
+- cache-unified;
|
|
|
+- next-level-cache = <&l3_cache>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- l2_cache_b3: l2-cache-b3 {
|
|
|
+- compatible = "cache";
|
|
|
+- cache-size = <524288>;
|
|
|
+- cache-line-size = <64>;
|
|
|
+- cache-sets = <1024>;
|
|
|
+- cache-level = <2>;
|
|
|
+- cache-unified;
|
|
|
+- next-level-cache = <&l3_cache>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- l3_cache: l3-cache {
|
|
|
+- compatible = "cache";
|
|
|
+- cache-size = <3145728>;
|
|
|
+- cache-line-size = <64>;
|
|
|
+- cache-sets = <4096>;
|
|
|
+- cache-level = <3>;
|
|
|
+- cache-unified;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- display_subsystem: display-subsystem {
|
|
|
+- compatible = "rockchip,display-subsystem";
|
|
|
+- ports = <&vop_out>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- firmware {
|
|
|
+- optee: optee {
|
|
|
+- compatible = "linaro,optee-tz";
|
|
|
+- method = "smc";
|
|
|
+- };
|
|
|
+-
|
|
|
+- scmi: scmi {
|
|
|
+- compatible = "arm,scmi-smc";
|
|
|
+- arm,smc-id = <0x82000010>;
|
|
|
+- shmem = <&scmi_shmem>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+-
|
|
|
+- scmi_clk: protocol@14 {
|
|
|
+- reg = <0x14>;
|
|
|
+- #clock-cells = <1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- scmi_reset: protocol@16 {
|
|
|
+- reg = <0x16>;
|
|
|
+- #reset-cells = <1>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pmu-a55 {
|
|
|
+- compatible = "arm,cortex-a55-pmu";
|
|
|
+- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- pmu-a76 {
|
|
|
+- compatible = "arm,cortex-a76-pmu";
|
|
|
+- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- psci {
|
|
|
+- compatible = "arm,psci-1.0";
|
|
|
+- method = "smc";
|
|
|
+- };
|
|
|
+-
|
|
|
+- spll: clock-0 {
|
|
|
+- compatible = "fixed-clock";
|
|
|
+- clock-frequency = <702000000>;
|
|
|
+- clock-output-names = "spll";
|
|
|
+- #clock-cells = <0>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- timer {
|
|
|
+- compatible = "arm,armv8-timer";
|
|
|
+- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
|
|
|
+- };
|
|
|
+-
|
|
|
+- xin24m: clock-1 {
|
|
|
+- compatible = "fixed-clock";
|
|
|
+- clock-frequency = <24000000>;
|
|
|
+- clock-output-names = "xin24m";
|
|
|
+- #clock-cells = <0>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- xin32k: clock-2 {
|
|
|
+- compatible = "fixed-clock";
|
|
|
+- clock-frequency = <32768>;
|
|
|
+- clock-output-names = "xin32k";
|
|
|
+- #clock-cells = <0>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- pmu_sram: sram@10f000 {
|
|
|
+- compatible = "mmio-sram";
|
|
|
+- reg = <0x0 0x0010f000 0x0 0x100>;
|
|
|
+- ranges = <0 0x0 0x0010f000 0x100>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <1>;
|
|
|
+-
|
|
|
+- scmi_shmem: sram@0 {
|
|
|
+- compatible = "arm,scmi-shmem";
|
|
|
+- reg = <0x0 0x100>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- gpu: gpu@fb000000 {
|
|
|
+- compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
|
|
|
+- reg = <0x0 0xfb000000 0x0 0x200000>;
|
|
|
+- #cooling-cells = <2>;
|
|
|
+- assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
|
|
|
+- assigned-clock-rates = <200000000>;
|
|
|
+- clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>,
|
|
|
+- <&cru CLK_GPU_STACKS>;
|
|
|
+- clock-names = "core", "coregroup", "stacks";
|
|
|
+- dynamic-power-coefficient = <2982>;
|
|
|
+- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "job", "mmu", "gpu";
|
|
|
+- operating-points-v2 = <&gpu_opp_table>;
|
|
|
+- power-domains = <&power RK3588_PD_GPU>;
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- gpu_opp_table: opp-table {
|
|
|
+- compatible = "operating-points-v2";
|
|
|
+-
|
|
|
+- opp-300000000 {
|
|
|
+- opp-hz = /bits/ 64 <300000000>;
|
|
|
+- opp-microvolt = <675000 675000 850000>;
|
|
|
+- };
|
|
|
+- opp-400000000 {
|
|
|
+- opp-hz = /bits/ 64 <400000000>;
|
|
|
+- opp-microvolt = <675000 675000 850000>;
|
|
|
+- };
|
|
|
+- opp-500000000 {
|
|
|
+- opp-hz = /bits/ 64 <500000000>;
|
|
|
+- opp-microvolt = <675000 675000 850000>;
|
|
|
+- };
|
|
|
+- opp-600000000 {
|
|
|
+- opp-hz = /bits/ 64 <600000000>;
|
|
|
+- opp-microvolt = <675000 675000 850000>;
|
|
|
+- };
|
|
|
+- opp-700000000 {
|
|
|
+- opp-hz = /bits/ 64 <700000000>;
|
|
|
+- opp-microvolt = <700000 700000 850000>;
|
|
|
+- };
|
|
|
+- opp-800000000 {
|
|
|
+- opp-hz = /bits/ 64 <800000000>;
|
|
|
+- opp-microvolt = <750000 750000 850000>;
|
|
|
+- };
|
|
|
+- opp-900000000 {
|
|
|
+- opp-hz = /bits/ 64 <900000000>;
|
|
|
+- opp-microvolt = <800000 800000 850000>;
|
|
|
+- };
|
|
|
+- opp-1000000000 {
|
|
|
+- opp-hz = /bits/ 64 <1000000000>;
|
|
|
+- opp-microvolt = <850000 850000 850000>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb_host0_xhci: usb@fc000000 {
|
|
|
+- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
|
|
+- reg = <0x0 0xfc000000 0x0 0x400000>;
|
|
|
+- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
|
|
|
+- <&cru ACLK_USB3OTG0>;
|
|
|
+- clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
|
|
+- dr_mode = "otg";
|
|
|
+- phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
|
|
|
+- phy-names = "usb2-phy", "usb3-phy";
|
|
|
+- phy_type = "utmi_wide";
|
|
|
+- power-domains = <&power RK3588_PD_USB>;
|
|
|
+- resets = <&cru SRST_A_USB3OTG0>;
|
|
|
+- snps,dis_enblslpm_quirk;
|
|
|
+- snps,dis-u1-entry-quirk;
|
|
|
+- snps,dis-u2-entry-quirk;
|
|
|
+- snps,dis-u2-freeclk-exists-quirk;
|
|
|
+- snps,dis-del-phy-power-chg-quirk;
|
|
|
+- snps,dis-tx-ipgap-linecheck-quirk;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb_host0_ehci: usb@fc800000 {
|
|
|
+- compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
|
|
+- reg = <0x0 0xfc800000 0x0 0x40000>;
|
|
|
+- interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
|
|
|
+- phys = <&u2phy2_host>;
|
|
|
+- phy-names = "usb";
|
|
|
+- power-domains = <&power RK3588_PD_USB>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb_host0_ohci: usb@fc840000 {
|
|
|
+- compatible = "rockchip,rk3588-ohci", "generic-ohci";
|
|
|
+- reg = <0x0 0xfc840000 0x0 0x40000>;
|
|
|
+- interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
|
|
|
+- phys = <&u2phy2_host>;
|
|
|
+- phy-names = "usb";
|
|
|
+- power-domains = <&power RK3588_PD_USB>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb_host1_ehci: usb@fc880000 {
|
|
|
+- compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
|
|
+- reg = <0x0 0xfc880000 0x0 0x40000>;
|
|
|
+- interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
|
|
|
+- phys = <&u2phy3_host>;
|
|
|
+- phy-names = "usb";
|
|
|
+- power-domains = <&power RK3588_PD_USB>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb_host1_ohci: usb@fc8c0000 {
|
|
|
+- compatible = "rockchip,rk3588-ohci", "generic-ohci";
|
|
|
+- reg = <0x0 0xfc8c0000 0x0 0x40000>;
|
|
|
+- interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
|
|
|
+- phys = <&u2phy3_host>;
|
|
|
+- phy-names = "usb";
|
|
|
+- power-domains = <&power RK3588_PD_USB>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb_host2_xhci: usb@fcd00000 {
|
|
|
+- compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
|
|
+- reg = <0x0 0xfcd00000 0x0 0x400000>;
|
|
|
+- interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
|
|
|
+- <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
|
|
|
+- <&cru CLK_PIPEPHY2_PIPE_U3_G>;
|
|
|
+- clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
|
|
|
+- dr_mode = "host";
|
|
|
+- phys = <&combphy2_psu PHY_TYPE_USB3>;
|
|
|
+- phy-names = "usb3-phy";
|
|
|
+- phy_type = "utmi_wide";
|
|
|
+- resets = <&cru SRST_A_USB3OTG2>;
|
|
|
+- snps,dis_enblslpm_quirk;
|
|
|
+- snps,dis-u2-freeclk-exists-quirk;
|
|
|
+- snps,dis-del-phy-power-chg-quirk;
|
|
|
+- snps,dis-tx-ipgap-linecheck-quirk;
|
|
|
+- snps,dis_rxdet_inp3_quirk;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- mmu600_pcie: iommu@fc900000 {
|
|
|
+- compatible = "arm,smmu-v3";
|
|
|
+- reg = <0x0 0xfc900000 0x0 0x200000>;
|
|
|
+- interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
|
|
+- #iommu-cells = <1>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- mmu600_php: iommu@fcb00000 {
|
|
|
+- compatible = "arm,smmu-v3";
|
|
|
+- reg = <0x0 0xfcb00000 0x0 0x200000>;
|
|
|
+- interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
|
|
|
+- #iommu-cells = <1>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pmu1grf: syscon@fd58a000 {
|
|
|
+- compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
|
|
|
+- reg = <0x0 0xfd58a000 0x0 0x10000>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- sys_grf: syscon@fd58c000 {
|
|
|
+- compatible = "rockchip,rk3588-sys-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd58c000 0x0 0x1000>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- vop_grf: syscon@fd5a4000 {
|
|
|
+- compatible = "rockchip,rk3588-vop-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5a4000 0x0 0x2000>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- vo0_grf: syscon@fd5a6000 {
|
|
|
+- compatible = "rockchip,rk3588-vo-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5a6000 0x0 0x2000>;
|
|
|
+- clocks = <&cru PCLK_VO0GRF>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- vo1_grf: syscon@fd5a8000 {
|
|
|
+- compatible = "rockchip,rk3588-vo-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5a8000 0x0 0x100>;
|
|
|
+- clocks = <&cru PCLK_VO1GRF>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb_grf: syscon@fd5ac000 {
|
|
|
+- compatible = "rockchip,rk3588-usb-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5ac000 0x0 0x4000>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- php_grf: syscon@fd5b0000 {
|
|
|
+- compatible = "rockchip,rk3588-php-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5b0000 0x0 0x1000>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- pipe_phy0_grf: syscon@fd5bc000 {
|
|
|
+- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5bc000 0x0 0x100>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- pipe_phy2_grf: syscon@fd5c4000 {
|
|
|
+- compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5c4000 0x0 0x100>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- usbdpphy0_grf: syscon@fd5c8000 {
|
|
|
+- compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5c8000 0x0 0x4000>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb2phy0_grf: syscon@fd5d0000 {
|
|
|
+- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
|
|
+- reg = <0x0 0xfd5d0000 0x0 0x4000>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <1>;
|
|
|
+-
|
|
|
+- u2phy0: usb2phy@0 {
|
|
|
+- compatible = "rockchip,rk3588-usb2phy";
|
|
|
+- reg = <0x0 0x10>;
|
|
|
+- #clock-cells = <0>;
|
|
|
+- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
|
|
+- clock-names = "phyclk";
|
|
|
+- clock-output-names = "usb480m_phy0";
|
|
|
+- interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
|
|
|
+- reset-names = "phy", "apb";
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- u2phy0_otg: otg-port {
|
|
|
+- #phy-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb2phy2_grf: syscon@fd5d8000 {
|
|
|
+- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
|
|
+- reg = <0x0 0xfd5d8000 0x0 0x4000>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <1>;
|
|
|
+-
|
|
|
+- u2phy2: usb2phy@8000 {
|
|
|
+- compatible = "rockchip,rk3588-usb2phy";
|
|
|
+- reg = <0x8000 0x10>;
|
|
|
+- #clock-cells = <0>;
|
|
|
+- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
|
|
+- clock-names = "phyclk";
|
|
|
+- clock-output-names = "usb480m_phy2";
|
|
|
+- interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
|
|
+- reset-names = "phy", "apb";
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- u2phy2_host: host-port {
|
|
|
+- #phy-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- usb2phy3_grf: syscon@fd5dc000 {
|
|
|
+- compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
|
|
+- reg = <0x0 0xfd5dc000 0x0 0x4000>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <1>;
|
|
|
+-
|
|
|
+- u2phy3: usb2phy@c000 {
|
|
|
+- compatible = "rockchip,rk3588-usb2phy";
|
|
|
+- reg = <0xc000 0x10>;
|
|
|
+- #clock-cells = <0>;
|
|
|
+- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
|
|
+- clock-names = "phyclk";
|
|
|
+- clock-output-names = "usb480m_phy3";
|
|
|
+- interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
|
|
+- reset-names = "phy", "apb";
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- u2phy3_host: host-port {
|
|
|
+- #phy-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- hdptxphy0_grf: syscon@fd5e0000 {
|
|
|
+- compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
|
|
|
+- reg = <0x0 0xfd5e0000 0x0 0x100>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- ioc: syscon@fd5f0000 {
|
|
|
+- compatible = "rockchip,rk3588-ioc", "syscon";
|
|
|
+- reg = <0x0 0xfd5f0000 0x0 0x10000>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- system_sram1: sram@fd600000 {
|
|
|
+- compatible = "mmio-sram";
|
|
|
+- reg = <0x0 0xfd600000 0x0 0x100000>;
|
|
|
+- ranges = <0x0 0x0 0xfd600000 0x100000>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cru: clock-controller@fd7c0000 {
|
|
|
+- compatible = "rockchip,rk3588-cru";
|
|
|
+- reg = <0x0 0xfd7c0000 0x0 0x5c000>;
|
|
|
+- assigned-clocks =
|
|
|
+- <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
|
|
|
+- <&cru PLL_NPLL>, <&cru PLL_GPLL>,
|
|
|
+- <&cru ACLK_CENTER_ROOT>,
|
|
|
+- <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
|
|
|
+- <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
|
|
|
+- <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
|
|
|
+- <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
|
|
|
+- <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
|
|
|
+- <&cru CLK_GPU>;
|
|
|
+- assigned-clock-rates =
|
|
|
+- <1100000000>, <786432000>,
|
|
|
+- <850000000>, <1188000000>,
|
|
|
+- <702000000>,
|
|
|
+- <400000000>, <500000000>,
|
|
|
+- <800000000>, <100000000>,
|
|
|
+- <400000000>, <100000000>,
|
|
|
+- <200000000>, <500000000>,
|
|
|
+- <375000000>, <150000000>,
|
|
|
+- <200000000>;
|
|
|
+- rockchip,grf = <&php_grf>;
|
|
|
+- #clock-cells = <1>;
|
|
|
+- #reset-cells = <1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c0: i2c@fd880000 {
|
|
|
+- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
+- reg = <0x0 0xfd880000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
|
|
|
+- clock-names = "i2c", "pclk";
|
|
|
+- pinctrl-0 = <&i2c0m0_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart0: serial@fd890000 {
|
|
|
+- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
+- reg = <0x0 0xfd890000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
|
|
+- clock-names = "baudclk", "apb_pclk";
|
|
|
+- dmas = <&dmac0 6>, <&dmac0 7>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- pinctrl-0 = <&uart0m1_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- reg-shift = <2>;
|
|
|
+- reg-io-width = <4>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm0: pwm@fd8b0000 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfd8b0000 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm0m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm1: pwm@fd8b0010 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfd8b0010 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm1m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm2: pwm@fd8b0020 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfd8b0020 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm2m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm3: pwm@fd8b0030 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfd8b0030 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm3m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pmu: power-management@fd8d8000 {
|
|
|
+- compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
|
|
|
+- reg = <0x0 0xfd8d8000 0x0 0x400>;
|
|
|
+-
|
|
|
+- power: power-controller {
|
|
|
+- compatible = "rockchip,rk3588-power-controller";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #power-domain-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "okay";
|
|
|
+-
|
|
|
+- /* These power domains are grouped by VD_NPU */
|
|
|
+- power-domain@RK3588_PD_NPU {
|
|
|
+- reg = <RK3588_PD_NPU>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+-
|
|
|
+- power-domain@RK3588_PD_NPUTOP {
|
|
|
+- reg = <RK3588_PD_NPUTOP>;
|
|
|
+- clocks = <&cru HCLK_NPU_ROOT>,
|
|
|
+- <&cru PCLK_NPU_ROOT>,
|
|
|
+- <&cru CLK_NPU_DSU0>,
|
|
|
+- <&cru HCLK_NPU_CM0_ROOT>;
|
|
|
+- pm_qos = <&qos_npu0_mwr>,
|
|
|
+- <&qos_npu0_mro>,
|
|
|
+- <&qos_mcu_npu>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+-
|
|
|
+- power-domain@RK3588_PD_NPU1 {
|
|
|
+- reg = <RK3588_PD_NPU1>;
|
|
|
+- clocks = <&cru HCLK_NPU_ROOT>,
|
|
|
+- <&cru PCLK_NPU_ROOT>,
|
|
|
+- <&cru CLK_NPU_DSU0>;
|
|
|
+- pm_qos = <&qos_npu1>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_NPU2 {
|
|
|
+- reg = <RK3588_PD_NPU2>;
|
|
|
+- clocks = <&cru HCLK_NPU_ROOT>,
|
|
|
+- <&cru PCLK_NPU_ROOT>,
|
|
|
+- <&cru CLK_NPU_DSU0>;
|
|
|
+- pm_qos = <&qos_npu2>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+- /* These power domains are grouped by VD_GPU */
|
|
|
+- power-domain@RK3588_PD_GPU {
|
|
|
+- reg = <RK3588_PD_GPU>;
|
|
|
+- clocks = <&cru CLK_GPU>,
|
|
|
+- <&cru CLK_GPU_COREGROUP>,
|
|
|
+- <&cru CLK_GPU_STACKS>;
|
|
|
+- pm_qos = <&qos_gpu_m0>,
|
|
|
+- <&qos_gpu_m1>,
|
|
|
+- <&qos_gpu_m2>,
|
|
|
+- <&qos_gpu_m3>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- /* These power domains are grouped by VD_VCODEC */
|
|
|
+- power-domain@RK3588_PD_VCODEC {
|
|
|
+- reg = <RK3588_PD_VCODEC>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+-
|
|
|
+- power-domain@RK3588_PD_RKVDEC0 {
|
|
|
+- reg = <RK3588_PD_RKVDEC0>;
|
|
|
+- clocks = <&cru HCLK_RKVDEC0>,
|
|
|
+- <&cru HCLK_VDPU_ROOT>,
|
|
|
+- <&cru ACLK_VDPU_ROOT>,
|
|
|
+- <&cru ACLK_RKVDEC0>,
|
|
|
+- <&cru ACLK_RKVDEC_CCU>;
|
|
|
+- pm_qos = <&qos_rkvdec0>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_RKVDEC1 {
|
|
|
+- reg = <RK3588_PD_RKVDEC1>;
|
|
|
+- clocks = <&cru HCLK_RKVDEC1>,
|
|
|
+- <&cru HCLK_VDPU_ROOT>,
|
|
|
+- <&cru ACLK_VDPU_ROOT>,
|
|
|
+- <&cru ACLK_RKVDEC1>;
|
|
|
+- pm_qos = <&qos_rkvdec1>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_VENC0 {
|
|
|
+- reg = <RK3588_PD_VENC0>;
|
|
|
+- clocks = <&cru HCLK_RKVENC0>,
|
|
|
+- <&cru ACLK_RKVENC0>;
|
|
|
+- pm_qos = <&qos_rkvenc0_m0ro>,
|
|
|
+- <&qos_rkvenc0_m1ro>,
|
|
|
+- <&qos_rkvenc0_m2wo>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+-
|
|
|
+- power-domain@RK3588_PD_VENC1 {
|
|
|
+- reg = <RK3588_PD_VENC1>;
|
|
|
+- clocks = <&cru HCLK_RKVENC1>,
|
|
|
+- <&cru HCLK_RKVENC0>,
|
|
|
+- <&cru ACLK_RKVENC0>,
|
|
|
+- <&cru ACLK_RKVENC1>;
|
|
|
+- pm_qos = <&qos_rkvenc1_m0ro>,
|
|
|
+- <&qos_rkvenc1_m1ro>,
|
|
|
+- <&qos_rkvenc1_m2wo>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+- /* These power domains are grouped by VD_LOGIC */
|
|
|
+- power-domain@RK3588_PD_VDPU {
|
|
|
+- reg = <RK3588_PD_VDPU>;
|
|
|
+- clocks = <&cru HCLK_VDPU_ROOT>,
|
|
|
+- <&cru ACLK_VDPU_LOW_ROOT>,
|
|
|
+- <&cru ACLK_VDPU_ROOT>,
|
|
|
+- <&cru ACLK_JPEG_DECODER_ROOT>,
|
|
|
+- <&cru ACLK_IEP2P0>,
|
|
|
+- <&cru HCLK_IEP2P0>,
|
|
|
+- <&cru ACLK_JPEG_ENCODER0>,
|
|
|
+- <&cru HCLK_JPEG_ENCODER0>,
|
|
|
+- <&cru ACLK_JPEG_ENCODER1>,
|
|
|
+- <&cru HCLK_JPEG_ENCODER1>,
|
|
|
+- <&cru ACLK_JPEG_ENCODER2>,
|
|
|
+- <&cru HCLK_JPEG_ENCODER2>,
|
|
|
+- <&cru ACLK_JPEG_ENCODER3>,
|
|
|
+- <&cru HCLK_JPEG_ENCODER3>,
|
|
|
+- <&cru ACLK_JPEG_DECODER>,
|
|
|
+- <&cru HCLK_JPEG_DECODER>,
|
|
|
+- <&cru ACLK_RGA2>,
|
|
|
+- <&cru HCLK_RGA2>;
|
|
|
+- pm_qos = <&qos_iep>,
|
|
|
+- <&qos_jpeg_dec>,
|
|
|
+- <&qos_jpeg_enc0>,
|
|
|
+- <&qos_jpeg_enc1>,
|
|
|
+- <&qos_jpeg_enc2>,
|
|
|
+- <&qos_jpeg_enc3>,
|
|
|
+- <&qos_rga2_mro>,
|
|
|
+- <&qos_rga2_mwo>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+-
|
|
|
+-
|
|
|
+- power-domain@RK3588_PD_AV1 {
|
|
|
+- reg = <RK3588_PD_AV1>;
|
|
|
+- clocks = <&cru PCLK_AV1>,
|
|
|
+- <&cru ACLK_AV1>,
|
|
|
+- <&cru HCLK_VDPU_ROOT>;
|
|
|
+- pm_qos = <&qos_av1>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_RKVDEC0 {
|
|
|
+- reg = <RK3588_PD_RKVDEC0>;
|
|
|
+- clocks = <&cru HCLK_RKVDEC0>,
|
|
|
+- <&cru HCLK_VDPU_ROOT>,
|
|
|
+- <&cru ACLK_VDPU_ROOT>,
|
|
|
+- <&cru ACLK_RKVDEC0>;
|
|
|
+- pm_qos = <&qos_rkvdec0>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_RKVDEC1 {
|
|
|
+- reg = <RK3588_PD_RKVDEC1>;
|
|
|
+- clocks = <&cru HCLK_RKVDEC1>,
|
|
|
+- <&cru HCLK_VDPU_ROOT>,
|
|
|
+- <&cru ACLK_VDPU_ROOT>;
|
|
|
+- pm_qos = <&qos_rkvdec1>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_RGA30 {
|
|
|
+- reg = <RK3588_PD_RGA30>;
|
|
|
+- clocks = <&cru ACLK_RGA3_0>,
|
|
|
+- <&cru HCLK_RGA3_0>;
|
|
|
+- pm_qos = <&qos_rga3_0>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_VOP {
|
|
|
+- reg = <RK3588_PD_VOP>;
|
|
|
+- clocks = <&cru PCLK_VOP_ROOT>,
|
|
|
+- <&cru HCLK_VOP_ROOT>,
|
|
|
+- <&cru ACLK_VOP>;
|
|
|
+- pm_qos = <&qos_vop_m0>,
|
|
|
+- <&qos_vop_m1>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+-
|
|
|
+- power-domain@RK3588_PD_VO0 {
|
|
|
+- reg = <RK3588_PD_VO0>;
|
|
|
+- clocks = <&cru PCLK_VO0_ROOT>,
|
|
|
+- <&cru PCLK_VO0_S_ROOT>,
|
|
|
+- <&cru HCLK_VO0_S_ROOT>,
|
|
|
+- <&cru ACLK_VO0_ROOT>,
|
|
|
+- <&cru HCLK_HDCP0>,
|
|
|
+- <&cru ACLK_HDCP0>,
|
|
|
+- <&cru HCLK_VOP_ROOT>;
|
|
|
+- pm_qos = <&qos_hdcp0>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_VO1 {
|
|
|
+- reg = <RK3588_PD_VO1>;
|
|
|
+- clocks = <&cru PCLK_VO1_ROOT>,
|
|
|
+- <&cru PCLK_VO1_S_ROOT>,
|
|
|
+- <&cru HCLK_VO1_S_ROOT>,
|
|
|
+- <&cru HCLK_HDCP1>,
|
|
|
+- <&cru ACLK_HDCP1>,
|
|
|
+- <&cru ACLK_HDMIRX_ROOT>,
|
|
|
+- <&cru HCLK_VO1USB_TOP_ROOT>;
|
|
|
+- pm_qos = <&qos_hdcp1>,
|
|
|
+- <&qos_hdmirx>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_VI {
|
|
|
+- reg = <RK3588_PD_VI>;
|
|
|
+- clocks = <&cru HCLK_VI_ROOT>,
|
|
|
+- <&cru PCLK_VI_ROOT>,
|
|
|
+- <&cru HCLK_ISP0>,
|
|
|
+- <&cru ACLK_ISP0>,
|
|
|
+- <&cru HCLK_VICAP>,
|
|
|
+- <&cru ACLK_VICAP>;
|
|
|
+- pm_qos = <&qos_isp0_mro>,
|
|
|
+- <&qos_isp0_mwo>,
|
|
|
+- <&qos_vicap_m0>,
|
|
|
+- <&qos_vicap_m1>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+-
|
|
|
+- power-domain@RK3588_PD_ISP1 {
|
|
|
+- reg = <RK3588_PD_ISP1>;
|
|
|
+- clocks = <&cru HCLK_ISP1>,
|
|
|
+- <&cru ACLK_ISP1>,
|
|
|
+- <&cru HCLK_VI_ROOT>,
|
|
|
+- <&cru PCLK_VI_ROOT>;
|
|
|
+- pm_qos = <&qos_isp1_mwo>,
|
|
|
+- <&qos_isp1_mro>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_FEC {
|
|
|
+- reg = <RK3588_PD_FEC>;
|
|
|
+- clocks = <&cru HCLK_FISHEYE0>,
|
|
|
+- <&cru ACLK_FISHEYE0>,
|
|
|
+- <&cru HCLK_FISHEYE1>,
|
|
|
+- <&cru ACLK_FISHEYE1>,
|
|
|
+- <&cru PCLK_VI_ROOT>;
|
|
|
+- pm_qos = <&qos_fisheye0>,
|
|
|
+- <&qos_fisheye1>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_RGA31 {
|
|
|
+- reg = <RK3588_PD_RGA31>;
|
|
|
+- clocks = <&cru HCLK_RGA3_1>,
|
|
|
+- <&cru ACLK_RGA3_1>;
|
|
|
+- pm_qos = <&qos_rga3_1>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_USB {
|
|
|
+- reg = <RK3588_PD_USB>;
|
|
|
+- clocks = <&cru PCLK_PHP_ROOT>,
|
|
|
+- <&cru ACLK_USB_ROOT>,
|
|
|
+- <&cru ACLK_USB>,
|
|
|
+- <&cru HCLK_USB_ROOT>,
|
|
|
+- <&cru HCLK_HOST0>,
|
|
|
+- <&cru HCLK_HOST_ARB0>,
|
|
|
+- <&cru HCLK_HOST1>,
|
|
|
+- <&cru HCLK_HOST_ARB1>;
|
|
|
+- pm_qos = <&qos_usb3_0>,
|
|
|
+- <&qos_usb3_1>,
|
|
|
+- <&qos_usb2host_0>,
|
|
|
+- <&qos_usb2host_1>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_GMAC {
|
|
|
+- reg = <RK3588_PD_GMAC>;
|
|
|
+- clocks = <&cru PCLK_PHP_ROOT>,
|
|
|
+- <&cru ACLK_PCIE_ROOT>,
|
|
|
+- <&cru ACLK_PHP_ROOT>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_PCIE {
|
|
|
+- reg = <RK3588_PD_PCIE>;
|
|
|
+- clocks = <&cru PCLK_PHP_ROOT>,
|
|
|
+- <&cru ACLK_PCIE_ROOT>,
|
|
|
+- <&cru ACLK_PHP_ROOT>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_SDIO {
|
|
|
+- reg = <RK3588_PD_SDIO>;
|
|
|
+- clocks = <&cru HCLK_SDIO>,
|
|
|
+- <&cru HCLK_NVM_ROOT>;
|
|
|
+- pm_qos = <&qos_sdio>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_AUDIO {
|
|
|
+- reg = <RK3588_PD_AUDIO>;
|
|
|
+- clocks = <&cru HCLK_AUDIO_ROOT>,
|
|
|
+- <&cru PCLK_AUDIO_ROOT>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- power-domain@RK3588_PD_SDMMC {
|
|
|
+- reg = <RK3588_PD_SDMMC>;
|
|
|
+- pm_qos = <&qos_sdmmc>;
|
|
|
+- #power-domain-cells = <0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- av1d: video-codec@fdc70000 {
|
|
|
+- compatible = "rockchip,rk3588-av1-vpu";
|
|
|
+- reg = <0x0 0xfdc70000 0x0 0x800>;
|
|
|
+- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "vdpu";
|
|
|
+- assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
|
|
+- assigned-clock-rates = <400000000>, <400000000>;
|
|
|
+- clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
|
|
|
+- clock-names = "aclk", "hclk";
|
|
|
+- power-domains = <&power RK3588_PD_AV1>;
|
|
|
+- resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- vop: vop@fdd90000 {
|
|
|
+- compatible = "rockchip,rk3588-vop";
|
|
|
+- reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
|
|
|
+- reg-names = "vop", "gamma-lut";
|
|
|
+- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru ACLK_VOP>,
|
|
|
+- <&cru HCLK_VOP>,
|
|
|
+- <&cru DCLK_VOP0>,
|
|
|
+- <&cru DCLK_VOP1>,
|
|
|
+- <&cru DCLK_VOP2>,
|
|
|
+- <&cru DCLK_VOP3>,
|
|
|
+- <&cru PCLK_VOP_ROOT>;
|
|
|
+- clock-names = "aclk",
|
|
|
+- "hclk",
|
|
|
+- "dclk_vp0",
|
|
|
+- "dclk_vp1",
|
|
|
+- "dclk_vp2",
|
|
|
+- "dclk_vp3",
|
|
|
+- "pclk_vop";
|
|
|
+- iommus = <&vop_mmu>;
|
|
|
+- power-domains = <&power RK3588_PD_VOP>;
|
|
|
+- rockchip,grf = <&sys_grf>;
|
|
|
+- rockchip,vop-grf = <&vop_grf>;
|
|
|
+- rockchip,vo1-grf = <&vo1_grf>;
|
|
|
+- rockchip,pmu = <&pmu>;
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- vop_out: ports {
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+-
|
|
|
+- vp0: port@0 {
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- reg = <0>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- vp1: port@1 {
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- reg = <1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- vp2: port@2 {
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- reg = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- vp3: port@3 {
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- reg = <3>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- vop_mmu: iommu@fdd97e00 {
|
|
|
+- compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
|
|
|
+- reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
|
|
+- clock-names = "aclk", "iface";
|
|
|
+- #iommu-cells = <0>;
|
|
|
+- power-domains = <&power RK3588_PD_VOP>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s4_8ch: i2s@fddc0000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
+- reg = <0x0 0xfddc0000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
|
|
|
+- clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
+- assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
|
|
|
+- assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
+- dmas = <&dmac2 0>;
|
|
|
+- dma-names = "tx";
|
|
|
+- power-domains = <&power RK3588_PD_VO0>;
|
|
|
+- resets = <&cru SRST_M_I2S4_8CH_TX>;
|
|
|
+- reset-names = "tx-m";
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s5_8ch: i2s@fddf0000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
+- reg = <0x0 0xfddf0000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
|
|
|
+- clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
+- assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
|
|
|
+- assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
+- dmas = <&dmac2 2>;
|
|
|
+- dma-names = "tx";
|
|
|
+- power-domains = <&power RK3588_PD_VO1>;
|
|
|
+- resets = <&cru SRST_M_I2S5_8CH_TX>;
|
|
|
+- reset-names = "tx-m";
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s9_8ch: i2s@fddfc000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
+- reg = <0x0 0xfddfc000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
|
|
|
+- clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
+- assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
|
|
|
+- assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
+- dmas = <&dmac2 23>;
|
|
|
+- dma-names = "rx";
|
|
|
+- power-domains = <&power RK3588_PD_VO1>;
|
|
|
+- resets = <&cru SRST_M_I2S9_8CH_RX>;
|
|
|
+- reset-names = "rx-m";
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_gpu_m0: qos@fdf35000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf35000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_gpu_m1: qos@fdf35200 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf35200 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_gpu_m2: qos@fdf35400 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf35400 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_gpu_m3: qos@fdf35600 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf35600 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rga3_1: qos@fdf36000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf36000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_sdio: qos@fdf39000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf39000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_sdmmc: qos@fdf3d800 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf3d800 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_usb3_1: qos@fdf3e000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf3e000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_usb3_0: qos@fdf3e200 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf3e200 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_usb2host_0: qos@fdf3e400 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf3e400 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_usb2host_1: qos@fdf3e600 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf3e600 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_fisheye0: qos@fdf40000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf40000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_fisheye1: qos@fdf40200 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf40200 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_isp0_mro: qos@fdf40400 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf40400 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_isp0_mwo: qos@fdf40500 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf40500 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_vicap_m0: qos@fdf40600 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf40600 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_vicap_m1: qos@fdf40800 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf40800 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_isp1_mwo: qos@fdf41000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf41000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_isp1_mro: qos@fdf41100 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf41100 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rkvenc0_m0ro: qos@fdf60000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf60000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rkvenc0_m1ro: qos@fdf60200 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf60200 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rkvenc0_m2wo: qos@fdf60400 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf60400 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rkvenc1_m0ro: qos@fdf61000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf61000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rkvenc1_m1ro: qos@fdf61200 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf61200 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rkvenc1_m2wo: qos@fdf61400 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf61400 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rkvdec0: qos@fdf62000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf62000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rkvdec1: qos@fdf63000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf63000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_av1: qos@fdf64000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf64000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_iep: qos@fdf66000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf66000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_jpeg_dec: qos@fdf66200 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf66200 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_jpeg_enc0: qos@fdf66400 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf66400 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_jpeg_enc1: qos@fdf66600 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf66600 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_jpeg_enc2: qos@fdf66800 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf66800 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_jpeg_enc3: qos@fdf66a00 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf66a00 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rga2_mro: qos@fdf66c00 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf66c00 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rga2_mwo: qos@fdf66e00 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf66e00 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_rga3_0: qos@fdf67000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf67000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_vdpu: qos@fdf67200 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf67200 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_npu1: qos@fdf70000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf70000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_npu2: qos@fdf71000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf71000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_npu0_mwr: qos@fdf72000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf72000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_npu0_mro: qos@fdf72200 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf72200 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_mcu_npu: qos@fdf72400 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf72400 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_hdcp0: qos@fdf80000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf80000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_hdcp1: qos@fdf81000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf81000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_hdmirx: qos@fdf81200 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf81200 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_vop_m0: qos@fdf82000 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf82000 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- qos_vop_m1: qos@fdf82200 {
|
|
|
+- compatible = "rockchip,rk3588-qos", "syscon";
|
|
|
+- reg = <0x0 0xfdf82200 0x0 0x20>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- dfi: dfi@fe060000 {
|
|
|
+- reg = <0x00 0xfe060000 0x00 0x10000>;
|
|
|
+- compatible = "rockchip,rk3588-dfi";
|
|
|
+- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- rockchip,pmu = <&pmu1grf>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie2x1l1: pcie@fe180000 {
|
|
|
+- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
|
+- bus-range = <0x30 0x3f>;
|
|
|
+- clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
|
|
|
+- <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
|
|
|
+- <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
|
|
|
+- clock-names = "aclk_mst", "aclk_slv",
|
|
|
+- "aclk_dbi", "pclk",
|
|
|
+- "aux", "pipe";
|
|
|
+- device_type = "pci";
|
|
|
+- interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
|
+- #interrupt-cells = <1>;
|
|
|
+- interrupt-map-mask = <0 0 0 7>;
|
|
|
+- interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
|
|
|
+- <0 0 0 2 &pcie2x1l1_intc 1>,
|
|
|
+- <0 0 0 3 &pcie2x1l1_intc 2>,
|
|
|
+- <0 0 0 4 &pcie2x1l1_intc 3>;
|
|
|
+- linux,pci-domain = <3>;
|
|
|
+- max-link-speed = <2>;
|
|
|
+- msi-map = <0x3000 &its0 0x3000 0x1000>;
|
|
|
+- num-lanes = <1>;
|
|
|
+- phys = <&combphy2_psu PHY_TYPE_PCIE>;
|
|
|
+- phy-names = "pcie-phy";
|
|
|
+- power-domains = <&power RK3588_PD_PCIE>;
|
|
|
+- ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
|
|
|
+- <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
|
|
|
+- <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
|
|
|
+- reg = <0xa 0x40c00000 0x0 0x00400000>,
|
|
|
+- <0x0 0xfe180000 0x0 0x00010000>,
|
|
|
+- <0x0 0xf3000000 0x0 0x00100000>;
|
|
|
+- reg-names = "dbi", "apb", "config";
|
|
|
+- resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
|
|
|
+- reset-names = "pwr", "pipe";
|
|
|
+- #address-cells = <3>;
|
|
|
+- #size-cells = <2>;
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- pcie2x1l1_intc: legacy-interrupt-controller {
|
|
|
+- interrupt-controller;
|
|
|
+- #address-cells = <0>;
|
|
|
+- #interrupt-cells = <1>;
|
|
|
+- interrupt-parent = <&gic>;
|
|
|
+- interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie2x1l2: pcie@fe190000 {
|
|
|
+- compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
|
+- bus-range = <0x40 0x4f>;
|
|
|
+- clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
|
|
|
+- <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
|
|
|
+- <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
|
|
|
+- clock-names = "aclk_mst", "aclk_slv",
|
|
|
+- "aclk_dbi", "pclk",
|
|
|
+- "aux", "pipe";
|
|
|
+- device_type = "pci";
|
|
|
+- interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
|
+- #interrupt-cells = <1>;
|
|
|
+- interrupt-map-mask = <0 0 0 7>;
|
|
|
+- interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
|
|
|
+- <0 0 0 2 &pcie2x1l2_intc 1>,
|
|
|
+- <0 0 0 3 &pcie2x1l2_intc 2>,
|
|
|
+- <0 0 0 4 &pcie2x1l2_intc 3>;
|
|
|
+- linux,pci-domain = <4>;
|
|
|
+- max-link-speed = <2>;
|
|
|
+- msi-map = <0x4000 &its0 0x4000 0x1000>;
|
|
|
+- num-lanes = <1>;
|
|
|
+- phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
|
|
+- phy-names = "pcie-phy";
|
|
|
+- power-domains = <&power RK3588_PD_PCIE>;
|
|
|
+- ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
|
|
|
+- <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
|
|
|
+- <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
|
|
|
+- reg = <0xa 0x41000000 0x0 0x00400000>,
|
|
|
+- <0x0 0xfe190000 0x0 0x00010000>,
|
|
|
+- <0x0 0xf4000000 0x0 0x00100000>;
|
|
|
+- reg-names = "dbi", "apb", "config";
|
|
|
+- resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
|
|
|
+- reset-names = "pwr", "pipe";
|
|
|
+- #address-cells = <3>;
|
|
|
+- #size-cells = <2>;
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- pcie2x1l2_intc: legacy-interrupt-controller {
|
|
|
+- interrupt-controller;
|
|
|
+- #address-cells = <0>;
|
|
|
+- #interrupt-cells = <1>;
|
|
|
+- interrupt-parent = <&gic>;
|
|
|
+- interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- gmac1: ethernet@fe1c0000 {
|
|
|
+- compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
|
|
+- reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
|
|
+- interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-names = "macirq", "eth_wake_irq";
|
|
|
+- clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
|
|
|
+- <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
|
|
|
+- <&cru CLK_GMAC1_PTP_REF>;
|
|
|
+- clock-names = "stmmaceth", "clk_mac_ref",
|
|
|
+- "pclk_mac", "aclk_mac",
|
|
|
+- "ptp_ref";
|
|
|
+- power-domains = <&power RK3588_PD_GMAC>;
|
|
|
+- resets = <&cru SRST_A_GMAC1>;
|
|
|
+- reset-names = "stmmaceth";
|
|
|
+- rockchip,grf = <&sys_grf>;
|
|
|
+- rockchip,php-grf = <&php_grf>;
|
|
|
+- snps,axi-config = <&gmac1_stmmac_axi_setup>;
|
|
|
+- snps,mixed-burst;
|
|
|
+- snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
|
|
|
+- snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
|
|
|
+- snps,tso;
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- mdio1: mdio {
|
|
|
+- compatible = "snps,dwmac-mdio";
|
|
|
+- #address-cells = <0x1>;
|
|
|
+- #size-cells = <0x0>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- gmac1_stmmac_axi_setup: stmmac-axi-config {
|
|
|
+- snps,blen = <0 0 0 0 16 8 4>;
|
|
|
+- snps,wr_osr_lmt = <4>;
|
|
|
+- snps,rd_osr_lmt = <8>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- gmac1_mtl_rx_setup: rx-queues-config {
|
|
|
+- snps,rx-queues-to-use = <2>;
|
|
|
+- queue0 {};
|
|
|
+- queue1 {};
|
|
|
+- };
|
|
|
+-
|
|
|
+- gmac1_mtl_tx_setup: tx-queues-config {
|
|
|
+- snps,tx-queues-to-use = <2>;
|
|
|
+- queue0 {};
|
|
|
+- queue1 {};
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sata0: sata@fe210000 {
|
|
|
+- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
|
|
+- reg = <0 0xfe210000 0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
|
|
|
+- <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
|
|
|
+- <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
|
|
|
+- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
|
|
+- ports-implemented = <0x1>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- sata-port@0 {
|
|
|
+- reg = <0>;
|
|
|
+- hba-port-cap = <HBA_PORT_FBSCP>;
|
|
|
+- phys = <&combphy0_ps PHY_TYPE_SATA>;
|
|
|
+- phy-names = "sata-phy";
|
|
|
+- snps,rx-ts-max = <32>;
|
|
|
+- snps,tx-ts-max = <32>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sata2: sata@fe230000 {
|
|
|
+- compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
|
|
+- reg = <0 0xfe230000 0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
|
|
|
+- <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
|
|
|
+- <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
|
|
|
+- clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
|
|
+- ports-implemented = <0x1>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+-
|
|
|
+- sata-port@0 {
|
|
|
+- reg = <0>;
|
|
|
+- hba-port-cap = <HBA_PORT_FBSCP>;
|
|
|
+- phys = <&combphy2_psu PHY_TYPE_SATA>;
|
|
|
+- phy-names = "sata-phy";
|
|
|
+- snps,rx-ts-max = <32>;
|
|
|
+- snps,tx-ts-max = <32>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sfc: spi@fe2b0000 {
|
|
|
+- compatible = "rockchip,sfc";
|
|
|
+- reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
|
|
+- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
|
|
+- clock-names = "clk_sfc", "hclk_sfc";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- sdmmc: mmc@fe2c0000 {
|
|
|
+- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
|
+- reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
|
|
+- interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
|
|
|
+- <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
|
|
+- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
|
+- fifo-depth = <0x100>;
|
|
|
+- max-frequency = <200000000>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
|
|
|
+- power-domains = <&power RK3588_PD_SDMMC>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- sdio: mmc@fe2d0000 {
|
|
|
+- compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
|
+- reg = <0x00 0xfe2d0000 0x00 0x4000>;
|
|
|
+- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
|
|
|
+- <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
|
|
+- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
|
+- fifo-depth = <0x100>;
|
|
|
+- max-frequency = <200000000>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- pinctrl-0 = <&sdiom1_pins>;
|
|
|
+- power-domains = <&power RK3588_PD_SDIO>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- sdhci: mmc@fe2e0000 {
|
|
|
+- compatible = "rockchip,rk3588-dwcmshc";
|
|
|
+- reg = <0x0 0xfe2e0000 0x0 0x10000>;
|
|
|
+- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
|
|
|
+- assigned-clock-rates = <200000000>, <24000000>, <200000000>;
|
|
|
+- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
|
|
|
+- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
|
|
+- <&cru TMCLK_EMMC>;
|
|
|
+- clock-names = "core", "bus", "axi", "block", "timer";
|
|
|
+- max-frequency = <200000000>;
|
|
|
+- pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
|
|
|
+- <&emmc_cmd>, <&emmc_data_strobe>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
|
|
|
+- <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
|
|
|
+- <&cru SRST_T_EMMC>;
|
|
|
+- reset-names = "core", "bus", "axi", "block", "timer";
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s0_8ch: i2s@fe470000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
+- reg = <0x0 0xfe470000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
|
|
|
+- clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
+- assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
|
|
|
+- assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
|
|
|
+- dmas = <&dmac0 0>, <&dmac0 1>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- power-domains = <&power RK3588_PD_AUDIO>;
|
|
|
+- resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
|
|
|
+- reset-names = "tx-m", "rx-m";
|
|
|
+- rockchip,trcm-sync-tx-only;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- pinctrl-0 = <&i2s0_lrck
|
|
|
+- &i2s0_sclk
|
|
|
+- &i2s0_sdi0
|
|
|
+- &i2s0_sdi1
|
|
|
+- &i2s0_sdi2
|
|
|
+- &i2s0_sdi3
|
|
|
+- &i2s0_sdo0
|
|
|
+- &i2s0_sdo1
|
|
|
+- &i2s0_sdo2
|
|
|
+- &i2s0_sdo3>;
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s1_8ch: i2s@fe480000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s-tdm";
|
|
|
+- reg = <0x0 0xfe480000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
|
|
|
+- clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
|
+- dmas = <&dmac0 2>, <&dmac0 3>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
|
|
|
+- reset-names = "tx-m", "rx-m";
|
|
|
+- rockchip,trcm-sync-tx-only;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- pinctrl-0 = <&i2s1m0_lrck
|
|
|
+- &i2s1m0_sclk
|
|
|
+- &i2s1m0_sdi0
|
|
|
+- &i2s1m0_sdi1
|
|
|
+- &i2s1m0_sdi2
|
|
|
+- &i2s1m0_sdi3
|
|
|
+- &i2s1m0_sdo0
|
|
|
+- &i2s1m0_sdo1
|
|
|
+- &i2s1m0_sdo2
|
|
|
+- &i2s1m0_sdo3>;
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s2_2ch: i2s@fe490000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
|
|
|
+- reg = <0x0 0xfe490000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
|
|
|
+- clock-names = "i2s_clk", "i2s_hclk";
|
|
|
+- assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
|
|
|
+- assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
+- dmas = <&dmac1 0>, <&dmac1 1>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- power-domains = <&power RK3588_PD_AUDIO>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- pinctrl-0 = <&i2s2m1_lrck
|
|
|
+- &i2s2m1_sclk
|
|
|
+- &i2s2m1_sdi
|
|
|
+- &i2s2m1_sdo>;
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s3_2ch: i2s@fe4a0000 {
|
|
|
+- compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
|
|
|
+- reg = <0x0 0xfe4a0000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
|
|
|
+- clock-names = "i2s_clk", "i2s_hclk";
|
|
|
+- assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
|
|
|
+- assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
|
+- dmas = <&dmac1 2>, <&dmac1 3>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- power-domains = <&power RK3588_PD_AUDIO>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- pinctrl-0 = <&i2s3_lrck
|
|
|
+- &i2s3_sclk
|
|
|
+- &i2s3_sdi
|
|
|
+- &i2s3_sdo>;
|
|
|
+- #sound-dai-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- gic: interrupt-controller@fe600000 {
|
|
|
+- compatible = "arm,gic-v3";
|
|
|
+- reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
|
|
|
+- <0x0 0xfe680000 0 0x100000>; /* GICR */
|
|
|
+- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- interrupt-controller;
|
|
|
+- mbi-alias = <0x0 0xfe610000>;
|
|
|
+- mbi-ranges = <424 56>;
|
|
|
+- msi-controller;
|
|
|
+- ranges;
|
|
|
+- #address-cells = <2>;
|
|
|
+- #interrupt-cells = <4>;
|
|
|
+- #size-cells = <2>;
|
|
|
+-
|
|
|
+- its0: msi-controller@fe640000 {
|
|
|
+- compatible = "arm,gic-v3-its";
|
|
|
+- reg = <0x0 0xfe640000 0x0 0x20000>;
|
|
|
+- msi-controller;
|
|
|
+- #msi-cells = <1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- its1: msi-controller@fe660000 {
|
|
|
+- compatible = "arm,gic-v3-its";
|
|
|
+- reg = <0x0 0xfe660000 0x0 0x20000>;
|
|
|
+- msi-controller;
|
|
|
+- #msi-cells = <1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- ppi-partitions {
|
|
|
+- ppi_partition0: interrupt-partition-0 {
|
|
|
+- affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- ppi_partition1: interrupt-partition-1 {
|
|
|
+- affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- dmac0: dma-controller@fea10000 {
|
|
|
+- compatible = "arm,pl330", "arm,primecell";
|
|
|
+- reg = <0x0 0xfea10000 0x0 0x4000>;
|
|
|
+- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- arm,pl330-periph-burst;
|
|
|
+- clocks = <&cru ACLK_DMAC0>;
|
|
|
+- clock-names = "apb_pclk";
|
|
|
+- #dma-cells = <1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- dmac1: dma-controller@fea30000 {
|
|
|
+- compatible = "arm,pl330", "arm,primecell";
|
|
|
+- reg = <0x0 0xfea30000 0x0 0x4000>;
|
|
|
+- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- arm,pl330-periph-burst;
|
|
|
+- clocks = <&cru ACLK_DMAC1>;
|
|
|
+- clock-names = "apb_pclk";
|
|
|
+- #dma-cells = <1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c1: i2c@fea90000 {
|
|
|
+- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
+- reg = <0x0 0xfea90000 0x0 0x1000>;
|
|
|
+- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
|
|
+- clock-names = "i2c", "pclk";
|
|
|
+- interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- pinctrl-0 = <&i2c1m0_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c2: i2c@feaa0000 {
|
|
|
+- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
+- reg = <0x0 0xfeaa0000 0x0 0x1000>;
|
|
|
+- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
|
|
+- clock-names = "i2c", "pclk";
|
|
|
+- interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- pinctrl-0 = <&i2c2m0_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c3: i2c@feab0000 {
|
|
|
+- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
+- reg = <0x0 0xfeab0000 0x0 0x1000>;
|
|
|
+- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
|
|
+- clock-names = "i2c", "pclk";
|
|
|
+- interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- pinctrl-0 = <&i2c3m0_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c4: i2c@feac0000 {
|
|
|
+- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
+- reg = <0x0 0xfeac0000 0x0 0x1000>;
|
|
|
+- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
|
|
+- clock-names = "i2c", "pclk";
|
|
|
+- interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- pinctrl-0 = <&i2c4m0_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c5: i2c@fead0000 {
|
|
|
+- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
+- reg = <0x0 0xfead0000 0x0 0x1000>;
|
|
|
+- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
|
|
+- clock-names = "i2c", "pclk";
|
|
|
+- interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- pinctrl-0 = <&i2c5m0_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- timer0: timer@feae0000 {
|
|
|
+- compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
|
|
|
+- reg = <0x0 0xfeae0000 0x0 0x20>;
|
|
|
+- interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
|
|
|
+- clock-names = "pclk", "timer";
|
|
|
+- };
|
|
|
+-
|
|
|
+- wdt: watchdog@feaf0000 {
|
|
|
+- compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
|
|
|
+- reg = <0x0 0xfeaf0000 0x0 0x100>;
|
|
|
+- clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
|
|
|
+- clock-names = "tclk", "pclk";
|
|
|
+- interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi0: spi@feb00000 {
|
|
|
+- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
|
|
+- reg = <0x0 0xfeb00000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
|
|
|
+- clock-names = "spiclk", "apb_pclk";
|
|
|
+- dmas = <&dmac0 14>, <&dmac0 15>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- num-cs = <2>;
|
|
|
+- pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi1: spi@feb10000 {
|
|
|
+- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
|
|
+- reg = <0x0 0xfeb10000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
|
|
|
+- clock-names = "spiclk", "apb_pclk";
|
|
|
+- dmas = <&dmac0 16>, <&dmac0 17>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- num-cs = <2>;
|
|
|
+- pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi2: spi@feb20000 {
|
|
|
+- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
|
|
+- reg = <0x0 0xfeb20000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
|
|
|
+- clock-names = "spiclk", "apb_pclk";
|
|
|
+- dmas = <&dmac1 15>, <&dmac1 16>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- num-cs = <2>;
|
|
|
+- pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi3: spi@feb30000 {
|
|
|
+- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
|
|
+- reg = <0x0 0xfeb30000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
|
|
|
+- clock-names = "spiclk", "apb_pclk";
|
|
|
+- dmas = <&dmac1 17>, <&dmac1 18>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- num-cs = <2>;
|
|
|
+- pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart1: serial@feb40000 {
|
|
|
+- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
+- reg = <0x0 0xfeb40000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
|
+- clock-names = "baudclk", "apb_pclk";
|
|
|
+- dmas = <&dmac0 8>, <&dmac0 9>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- pinctrl-0 = <&uart1m1_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- reg-io-width = <4>;
|
|
|
+- reg-shift = <2>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart2: serial@feb50000 {
|
|
|
+- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
+- reg = <0x0 0xfeb50000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
|
+- clock-names = "baudclk", "apb_pclk";
|
|
|
+- dmas = <&dmac0 10>, <&dmac0 11>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- pinctrl-0 = <&uart2m1_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- reg-io-width = <4>;
|
|
|
+- reg-shift = <2>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart3: serial@feb60000 {
|
|
|
+- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
+- reg = <0x0 0xfeb60000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
|
+- clock-names = "baudclk", "apb_pclk";
|
|
|
+- dmas = <&dmac0 12>, <&dmac0 13>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- pinctrl-0 = <&uart3m1_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- reg-io-width = <4>;
|
|
|
+- reg-shift = <2>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart4: serial@feb70000 {
|
|
|
+- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
+- reg = <0x0 0xfeb70000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
|
+- clock-names = "baudclk", "apb_pclk";
|
|
|
+- dmas = <&dmac1 9>, <&dmac1 10>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- pinctrl-0 = <&uart4m1_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- reg-io-width = <4>;
|
|
|
+- reg-shift = <2>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart5: serial@feb80000 {
|
|
|
+- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
+- reg = <0x0 0xfeb80000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
|
|
+- clock-names = "baudclk", "apb_pclk";
|
|
|
+- dmas = <&dmac1 11>, <&dmac1 12>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- pinctrl-0 = <&uart5m1_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- reg-io-width = <4>;
|
|
|
+- reg-shift = <2>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart6: serial@feb90000 {
|
|
|
+- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
+- reg = <0x0 0xfeb90000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
|
|
+- clock-names = "baudclk", "apb_pclk";
|
|
|
+- dmas = <&dmac1 13>, <&dmac1 14>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- pinctrl-0 = <&uart6m1_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- reg-io-width = <4>;
|
|
|
+- reg-shift = <2>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart7: serial@feba0000 {
|
|
|
+- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
+- reg = <0x0 0xfeba0000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
|
|
+- clock-names = "baudclk", "apb_pclk";
|
|
|
+- dmas = <&dmac2 7>, <&dmac2 8>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- pinctrl-0 = <&uart7m1_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- reg-io-width = <4>;
|
|
|
+- reg-shift = <2>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart8: serial@febb0000 {
|
|
|
+- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
+- reg = <0x0 0xfebb0000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
|
|
+- clock-names = "baudclk", "apb_pclk";
|
|
|
+- dmas = <&dmac2 9>, <&dmac2 10>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- pinctrl-0 = <&uart8m1_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- reg-io-width = <4>;
|
|
|
+- reg-shift = <2>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart9: serial@febc0000 {
|
|
|
+- compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
|
+- reg = <0x0 0xfebc0000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
|
|
+- clock-names = "baudclk", "apb_pclk";
|
|
|
+- dmas = <&dmac2 11>, <&dmac2 12>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- pinctrl-0 = <&uart9m1_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- reg-io-width = <4>;
|
|
|
+- reg-shift = <2>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm4: pwm@febd0000 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebd0000 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm4m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm5: pwm@febd0010 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebd0010 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm5m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm6: pwm@febd0020 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebd0020 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm6m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm7: pwm@febd0030 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebd0030 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm7m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm8: pwm@febe0000 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebe0000 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm8m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm9: pwm@febe0010 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebe0010 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm9m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm10: pwm@febe0020 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebe0020 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm10m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm11: pwm@febe0030 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebe0030 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm11m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm12: pwm@febf0000 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebf0000 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm12m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm13: pwm@febf0010 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebf0010 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm13m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm14: pwm@febf0020 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebf0020 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm14m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm15: pwm@febf0030 {
|
|
|
+- compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
|
+- reg = <0x0 0xfebf0030 0x0 0x10>;
|
|
|
+- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
|
+- clock-names = "pwm", "pclk";
|
|
|
+- pinctrl-0 = <&pwm15m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #pwm-cells = <3>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- tsadc: tsadc@fec00000 {
|
|
|
+- compatible = "rockchip,rk3588-tsadc";
|
|
|
+- reg = <0x0 0xfec00000 0x0 0x400>;
|
|
|
+- interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
|
|
+- clock-names = "tsadc", "apb_pclk";
|
|
|
+- assigned-clocks = <&cru CLK_TSADC>;
|
|
|
+- assigned-clock-rates = <2000000>;
|
|
|
+- resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
|
|
|
+- reset-names = "tsadc-apb", "tsadc";
|
|
|
+- rockchip,hw-tshut-temp = <120000>;
|
|
|
+- rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
|
|
+- rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
|
|
+- pinctrl-0 = <&tsadc_gpio_func>;
|
|
|
+- pinctrl-1 = <&tsadc_shut>;
|
|
|
+- pinctrl-names = "gpio", "otpout";
|
|
|
+- #thermal-sensor-cells = <1>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- saradc: adc@fec10000 {
|
|
|
+- compatible = "rockchip,rk3588-saradc";
|
|
|
+- reg = <0x0 0xfec10000 0x0 0x10000>;
|
|
|
+- interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- #io-channel-cells = <1>;
|
|
|
+- clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
|
|
|
+- clock-names = "saradc", "apb_pclk";
|
|
|
+- resets = <&cru SRST_P_SARADC>;
|
|
|
+- reset-names = "saradc-apb";
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c6: i2c@fec80000 {
|
|
|
+- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
+- reg = <0x0 0xfec80000 0x0 0x1000>;
|
|
|
+- clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
|
|
|
+- clock-names = "i2c", "pclk";
|
|
|
+- interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- pinctrl-0 = <&i2c6m0_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c7: i2c@fec90000 {
|
|
|
+- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
+- reg = <0x0 0xfec90000 0x0 0x1000>;
|
|
|
+- clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
|
|
|
+- clock-names = "i2c", "pclk";
|
|
|
+- interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- pinctrl-0 = <&i2c7m0_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c8: i2c@feca0000 {
|
|
|
+- compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
|
+- reg = <0x0 0xfeca0000 0x0 0x1000>;
|
|
|
+- clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
|
|
|
+- clock-names = "i2c", "pclk";
|
|
|
+- interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- pinctrl-0 = <&i2c8m0_xfer>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi4: spi@fecb0000 {
|
|
|
+- compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
|
|
|
+- reg = <0x0 0xfecb0000 0x0 0x1000>;
|
|
|
+- interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
|
|
|
+- clock-names = "spiclk", "apb_pclk";
|
|
|
+- dmas = <&dmac2 13>, <&dmac2 14>;
|
|
|
+- dma-names = "tx", "rx";
|
|
|
+- num-cs = <2>;
|
|
|
+- pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
|
|
|
+- pinctrl-names = "default";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <0>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- otp: efuse@fecc0000 {
|
|
|
+- compatible = "rockchip,rk3588-otp";
|
|
|
+- reg = <0x0 0xfecc0000 0x0 0x400>;
|
|
|
+- clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
|
|
|
+- <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
|
|
|
+- clock-names = "otp", "apb_pclk", "phy", "arb";
|
|
|
+- resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
|
|
|
+- <&cru SRST_OTPC_ARB>;
|
|
|
+- reset-names = "otp", "apb", "arb";
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <1>;
|
|
|
+-
|
|
|
+- cpu_code: cpu-code@2 {
|
|
|
+- reg = <0x02 0x2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- otp_id: id@7 {
|
|
|
+- reg = <0x07 0x10>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpub0_leakage: cpu-leakage@17 {
|
|
|
+- reg = <0x17 0x1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpub1_leakage: cpu-leakage@18 {
|
|
|
+- reg = <0x18 0x1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpul_leakage: cpu-leakage@19 {
|
|
|
+- reg = <0x19 0x1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- log_leakage: log-leakage@1a {
|
|
|
+- reg = <0x1a 0x1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- gpu_leakage: gpu-leakage@1b {
|
|
|
+- reg = <0x1b 0x1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- otp_cpu_version: cpu-version@1c {
|
|
|
+- reg = <0x1c 0x1>;
|
|
|
+- bits = <3 3>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- npu_leakage: npu-leakage@28 {
|
|
|
+- reg = <0x28 0x1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- codec_leakage: codec-leakage@29 {
|
|
|
+- reg = <0x29 0x1>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- dmac2: dma-controller@fed10000 {
|
|
|
+- compatible = "arm,pl330", "arm,primecell";
|
|
|
+- reg = <0x0 0xfed10000 0x0 0x4000>;
|
|
|
+- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
|
+- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- arm,pl330-periph-burst;
|
|
|
+- clocks = <&cru ACLK_DMAC2>;
|
|
|
+- clock-names = "apb_pclk";
|
|
|
+- #dma-cells = <1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- hdptxphy_hdmi0: phy@fed60000 {
|
|
|
+- compatible = "rockchip,rk3588-hdptx-phy";
|
|
|
+- reg = <0x0 0xfed60000 0x0 0x2000>;
|
|
|
+- clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
|
|
|
+- clock-names = "ref", "apb";
|
|
|
+- #phy-cells = <0>;
|
|
|
+- resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
|
|
|
+- <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
|
|
|
+- <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
|
|
|
+- <&cru SRST_HDPTX0_LCPLL>;
|
|
|
+- reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
|
|
|
+- "lcpll";
|
|
|
+- rockchip,grf = <&hdptxphy0_grf>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- usbdp_phy0: phy@fed80000 {
|
|
|
+- compatible = "rockchip,rk3588-usbdp-phy";
|
|
|
+- reg = <0x0 0xfed80000 0x0 0x10000>;
|
|
|
+- #phy-cells = <1>;
|
|
|
+- clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
|
|
+- <&cru CLK_USBDP_PHY0_IMMORTAL>,
|
|
|
+- <&cru PCLK_USBDPPHY0>,
|
|
|
+- <&u2phy0>;
|
|
|
+- clock-names = "refclk", "immortal", "pclk", "utmi";
|
|
|
+- resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
|
|
|
+- <&cru SRST_USBDP_COMBO_PHY0_CMN>,
|
|
|
+- <&cru SRST_USBDP_COMBO_PHY0_LANE>,
|
|
|
+- <&cru SRST_USBDP_COMBO_PHY0_PCS>,
|
|
|
+- <&cru SRST_P_USBDPPHY0>;
|
|
|
+- reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
|
|
+- rockchip,u2phy-grf = <&usb2phy0_grf>;
|
|
|
+- rockchip,usb-grf = <&usb_grf>;
|
|
|
+- rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
|
|
|
+- rockchip,vo-grf = <&vo0_grf>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- combphy0_ps: phy@fee00000 {
|
|
|
+- compatible = "rockchip,rk3588-naneng-combphy";
|
|
|
+- reg = <0x0 0xfee00000 0x0 0x100>;
|
|
|
+- clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
|
|
|
+- <&cru PCLK_PHP_ROOT>;
|
|
|
+- clock-names = "ref", "apb", "pipe";
|
|
|
+- assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
|
|
|
+- assigned-clock-rates = <100000000>;
|
|
|
+- #phy-cells = <1>;
|
|
|
+- resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
|
|
|
+- reset-names = "phy", "apb";
|
|
|
+- rockchip,pipe-grf = <&php_grf>;
|
|
|
+- rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- combphy2_psu: phy@fee20000 {
|
|
|
+- compatible = "rockchip,rk3588-naneng-combphy";
|
|
|
+- reg = <0x0 0xfee20000 0x0 0x100>;
|
|
|
+- clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
|
|
|
+- <&cru PCLK_PHP_ROOT>;
|
|
|
+- clock-names = "ref", "apb", "pipe";
|
|
|
+- assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
|
|
|
+- assigned-clock-rates = <100000000>;
|
|
|
+- #phy-cells = <1>;
|
|
|
+- resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
|
|
|
+- reset-names = "phy", "apb";
|
|
|
+- rockchip,pipe-grf = <&php_grf>;
|
|
|
+- rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
|
|
|
+- status = "disabled";
|
|
|
+- };
|
|
|
+-
|
|
|
+- system_sram2: sram@ff001000 {
|
|
|
+- compatible = "mmio-sram";
|
|
|
+- reg = <0x0 0xff001000 0x0 0xef000>;
|
|
|
+- ranges = <0x0 0x0 0xff001000 0xef000>;
|
|
|
+- #address-cells = <1>;
|
|
|
+- #size-cells = <1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- pinctrl: pinctrl {
|
|
|
+- compatible = "rockchip,rk3588-pinctrl";
|
|
|
+- ranges;
|
|
|
+- rockchip,grf = <&ioc>;
|
|
|
+- #address-cells = <2>;
|
|
|
+- #size-cells = <2>;
|
|
|
+-
|
|
|
+- gpio0: gpio@fd8a0000 {
|
|
|
+- compatible = "rockchip,gpio-bank";
|
|
|
+- reg = <0x0 0xfd8a0000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
|
|
|
+- gpio-controller;
|
|
|
+- gpio-ranges = <&pinctrl 0 0 32>;
|
|
|
+- interrupt-controller;
|
|
|
+- #gpio-cells = <2>;
|
|
|
+- #interrupt-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- gpio1: gpio@fec20000 {
|
|
|
+- compatible = "rockchip,gpio-bank";
|
|
|
+- reg = <0x0 0xfec20000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
|
|
+- gpio-controller;
|
|
|
+- gpio-ranges = <&pinctrl 0 32 32>;
|
|
|
+- interrupt-controller;
|
|
|
+- #gpio-cells = <2>;
|
|
|
+- #interrupt-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- gpio2: gpio@fec30000 {
|
|
|
+- compatible = "rockchip,gpio-bank";
|
|
|
+- reg = <0x0 0xfec30000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
|
|
+- gpio-controller;
|
|
|
+- gpio-ranges = <&pinctrl 0 64 32>;
|
|
|
+- interrupt-controller;
|
|
|
+- #gpio-cells = <2>;
|
|
|
+- #interrupt-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- gpio3: gpio@fec40000 {
|
|
|
+- compatible = "rockchip,gpio-bank";
|
|
|
+- reg = <0x0 0xfec40000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
|
|
+- gpio-controller;
|
|
|
+- gpio-ranges = <&pinctrl 0 96 32>;
|
|
|
+- interrupt-controller;
|
|
|
+- #gpio-cells = <2>;
|
|
|
+- #interrupt-cells = <2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- gpio4: gpio@fec50000 {
|
|
|
+- compatible = "rockchip,gpio-bank";
|
|
|
+- reg = <0x0 0xfec50000 0x0 0x100>;
|
|
|
+- interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
|
+- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
|
|
+- gpio-controller;
|
|
|
+- gpio-ranges = <&pinctrl 0 128 32>;
|
|
|
+- interrupt-controller;
|
|
|
+- #gpio-cells = <2>;
|
|
|
+- #interrupt-cells = <2>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-};
|
|
|
+-
|
|
|
+-#include "rk3588s-pinctrl.dtsi"
|
|
|
++#include "rk3588-base.dtsi"
|
|
|
+--- /dev/null
|
|
|
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
|
|
|
+@@ -0,0 +1,3447 @@
|
|
|
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
|
++/*
|
|
|
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
|
|
++ */
|
|
|
++
|
|
|
++#include <dt-bindings/pinctrl/rockchip.h>
|
|
|
++#include "rockchip-pinconf.dtsi"
|
|
|
++
|
|
|
++/*
|
|
|
++ * This file is auto generated by pin2dts tool, please keep these code
|
|
|
++ * by adding changes at end of this file.
|
|
|
++ */
|
|
|
++&pinctrl {
|
|
|
++ auddsm {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ auddsm_pins: auddsm-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* auddsm_ln */
|
|
|
++ <3 RK_PA1 4 &pcfg_pull_none>,
|
|
|
++ /* auddsm_lp */
|
|
|
++ <3 RK_PA2 4 &pcfg_pull_none>,
|
|
|
++ /* auddsm_rn */
|
|
|
++ <3 RK_PA3 4 &pcfg_pull_none>,
|
|
|
++ /* auddsm_rp */
|
|
|
++ <3 RK_PA4 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ bt1120 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ bt1120_pins: bt1120-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* bt1120_clkout */
|
|
|
++ <4 RK_PB0 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d0 */
|
|
|
++ <4 RK_PA0 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d1 */
|
|
|
++ <4 RK_PA1 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d2 */
|
|
|
++ <4 RK_PA2 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d3 */
|
|
|
++ <4 RK_PA3 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d4 */
|
|
|
++ <4 RK_PA4 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d5 */
|
|
|
++ <4 RK_PA5 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d6 */
|
|
|
++ <4 RK_PA6 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d7 */
|
|
|
++ <4 RK_PA7 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d8 */
|
|
|
++ <4 RK_PB2 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d9 */
|
|
|
++ <4 RK_PB3 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d10 */
|
|
|
++ <4 RK_PB4 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d11 */
|
|
|
++ <4 RK_PB5 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d12 */
|
|
|
++ <4 RK_PB6 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d13 */
|
|
|
++ <4 RK_PB7 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d14 */
|
|
|
++ <4 RK_PC0 2 &pcfg_pull_none>,
|
|
|
++ /* bt1120_d15 */
|
|
|
++ <4 RK_PC1 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ can0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ can0m0_pins: can0m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* can0_rx_m0 */
|
|
|
++ <0 RK_PC0 11 &pcfg_pull_none>,
|
|
|
++ /* can0_tx_m0 */
|
|
|
++ <0 RK_PB7 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ can0m1_pins: can0m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* can0_rx_m1 */
|
|
|
++ <4 RK_PD5 9 &pcfg_pull_none>,
|
|
|
++ /* can0_tx_m1 */
|
|
|
++ <4 RK_PD4 9 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ can1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ can1m0_pins: can1m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* can1_rx_m0 */
|
|
|
++ <3 RK_PB5 9 &pcfg_pull_none>,
|
|
|
++ /* can1_tx_m0 */
|
|
|
++ <3 RK_PB6 9 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ can1m1_pins: can1m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* can1_rx_m1 */
|
|
|
++ <4 RK_PB2 12 &pcfg_pull_none>,
|
|
|
++ /* can1_tx_m1 */
|
|
|
++ <4 RK_PB3 12 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ can2 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ can2m0_pins: can2m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* can2_rx_m0 */
|
|
|
++ <3 RK_PC4 9 &pcfg_pull_none>,
|
|
|
++ /* can2_tx_m0 */
|
|
|
++ <3 RK_PC5 9 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ can2m1_pins: can2m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* can2_rx_m1 */
|
|
|
++ <0 RK_PD4 10 &pcfg_pull_none>,
|
|
|
++ /* can2_tx_m1 */
|
|
|
++ <0 RK_PD5 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ cif {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ cif_clk: cif-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* cif_clkout */
|
|
|
++ <4 RK_PB4 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ cif_dvp_clk: cif-dvp-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* cif_clkin */
|
|
|
++ <4 RK_PB0 1 &pcfg_pull_none>,
|
|
|
++ /* cif_href */
|
|
|
++ <4 RK_PB2 1 &pcfg_pull_none>,
|
|
|
++ /* cif_vsync */
|
|
|
++ <4 RK_PB3 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ cif_dvp_bus16: cif-dvp-bus16 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* cif_d8 */
|
|
|
++ <3 RK_PC4 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d9 */
|
|
|
++ <3 RK_PC5 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d10 */
|
|
|
++ <3 RK_PC6 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d11 */
|
|
|
++ <3 RK_PC7 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d12 */
|
|
|
++ <3 RK_PD0 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d13 */
|
|
|
++ <3 RK_PD1 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d14 */
|
|
|
++ <3 RK_PD2 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d15 */
|
|
|
++ <3 RK_PD3 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ cif_dvp_bus8: cif-dvp-bus8 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* cif_d0 */
|
|
|
++ <4 RK_PA0 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d1 */
|
|
|
++ <4 RK_PA1 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d2 */
|
|
|
++ <4 RK_PA2 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d3 */
|
|
|
++ <4 RK_PA3 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d4 */
|
|
|
++ <4 RK_PA4 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d5 */
|
|
|
++ <4 RK_PA5 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d6 */
|
|
|
++ <4 RK_PA6 1 &pcfg_pull_none>,
|
|
|
++ /* cif_d7 */
|
|
|
++ <4 RK_PA7 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ clk32k {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ clk32k_in: clk32k-in {
|
|
|
++ rockchip,pins =
|
|
|
++ /* clk32k_in */
|
|
|
++ <0 RK_PB2 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ clk32k_out0: clk32k-out0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* clk32k_out0 */
|
|
|
++ <0 RK_PB2 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ cpu {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ cpu_pins: cpu-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* cpu_big0_avs */
|
|
|
++ <0 RK_PD1 2 &pcfg_pull_none>,
|
|
|
++ /* cpu_big1_avs */
|
|
|
++ <0 RK_PD5 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ ddrphych0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ ddrphych0_pins: ddrphych0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* ddrphych0_dtb0 */
|
|
|
++ <4 RK_PA0 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych0_dtb1 */
|
|
|
++ <4 RK_PA1 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych0_dtb2 */
|
|
|
++ <4 RK_PA2 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych0_dtb3 */
|
|
|
++ <4 RK_PA3 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ ddrphych1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ ddrphych1_pins: ddrphych1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* ddrphych1_dtb0 */
|
|
|
++ <4 RK_PA4 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych1_dtb1 */
|
|
|
++ <4 RK_PA5 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych1_dtb2 */
|
|
|
++ <4 RK_PA6 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych1_dtb3 */
|
|
|
++ <4 RK_PA7 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ ddrphych2 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ ddrphych2_pins: ddrphych2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* ddrphych2_dtb0 */
|
|
|
++ <4 RK_PB0 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych2_dtb1 */
|
|
|
++ <4 RK_PB1 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych2_dtb2 */
|
|
|
++ <4 RK_PB2 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych2_dtb3 */
|
|
|
++ <4 RK_PB3 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ ddrphych3 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ ddrphych3_pins: ddrphych3-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* ddrphych3_dtb0 */
|
|
|
++ <4 RK_PB4 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych3_dtb1 */
|
|
|
++ <4 RK_PB5 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych3_dtb2 */
|
|
|
++ <4 RK_PB6 7 &pcfg_pull_none>,
|
|
|
++ /* ddrphych3_dtb3 */
|
|
|
++ <4 RK_PB7 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ dp0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ dp0m0_pins: dp0m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* dp0_hpdin_m0 */
|
|
|
++ <4 RK_PB4 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ dp0m1_pins: dp0m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* dp0_hpdin_m1 */
|
|
|
++ <0 RK_PC4 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ dp0m2_pins: dp0m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* dp0_hpdin_m2 */
|
|
|
++ <1 RK_PA0 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ dp1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ dp1m0_pins: dp1m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* dp1_hpdin_m0 */
|
|
|
++ <3 RK_PD5 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ dp1m1_pins: dp1m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* dp1_hpdin_m1 */
|
|
|
++ <0 RK_PC5 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ dp1m2_pins: dp1m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* dp1_hpdin_m2 */
|
|
|
++ <1 RK_PA1 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ emmc {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ emmc_rstnout: emmc-rstnout {
|
|
|
++ rockchip,pins =
|
|
|
++ /* emmc_rstn */
|
|
|
++ <2 RK_PA3 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ emmc_bus8: emmc-bus8 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* emmc_d0 */
|
|
|
++ <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* emmc_d1 */
|
|
|
++ <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* emmc_d2 */
|
|
|
++ <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* emmc_d3 */
|
|
|
++ <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* emmc_d4 */
|
|
|
++ <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* emmc_d5 */
|
|
|
++ <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* emmc_d6 */
|
|
|
++ <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* emmc_d7 */
|
|
|
++ <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ emmc_clk: emmc-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* emmc_clkout */
|
|
|
++ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ emmc_cmd: emmc-cmd {
|
|
|
++ rockchip,pins =
|
|
|
++ /* emmc_cmd */
|
|
|
++ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ emmc_data_strobe: emmc-data-strobe {
|
|
|
++ rockchip,pins =
|
|
|
++ /* emmc_data_strobe */
|
|
|
++ <2 RK_PA2 1 &pcfg_pull_down>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ eth1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ eth1_pins: eth1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* eth1_refclko_25m */
|
|
|
++ <3 RK_PA6 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ fspi {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ fspim0_pins: fspim0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* fspi_clk_m0 */
|
|
|
++ <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* fspi_cs0n_m0 */
|
|
|
++ <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* fspi_d0_m0 */
|
|
|
++ <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* fspi_d1_m0 */
|
|
|
++ <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* fspi_d2_m0 */
|
|
|
++ <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* fspi_d3_m0 */
|
|
|
++ <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ fspim0_cs1: fspim0-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* fspi_cs1n_m0 */
|
|
|
++ <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ fspim2_pins: fspim2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* fspi_clk_m2 */
|
|
|
++ <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* fspi_cs0n_m2 */
|
|
|
++ <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* fspi_d0_m2 */
|
|
|
++ <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* fspi_d1_m2 */
|
|
|
++ <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* fspi_d2_m2 */
|
|
|
++ <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* fspi_d3_m2 */
|
|
|
++ <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ fspim2_cs1: fspim2-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* fspi_cs1n_m2 */
|
|
|
++ <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ gmac1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gmac1_miim: gmac1-miim {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gmac1_mdc */
|
|
|
++ <3 RK_PC2 1 &pcfg_pull_none>,
|
|
|
++ /* gmac1_mdio */
|
|
|
++ <3 RK_PC3 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gmac1_clkinout: gmac1-clkinout {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gmac1_mclkinout */
|
|
|
++ <3 RK_PB6 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gmac1_rx_bus2: gmac1-rx-bus2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gmac1_rxd0 */
|
|
|
++ <3 RK_PA7 1 &pcfg_pull_none>,
|
|
|
++ /* gmac1_rxd1 */
|
|
|
++ <3 RK_PB0 1 &pcfg_pull_none>,
|
|
|
++ /* gmac1_rxdv_crs */
|
|
|
++ <3 RK_PB1 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gmac1_tx_bus2: gmac1-tx-bus2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gmac1_txd0 */
|
|
|
++ <3 RK_PB3 1 &pcfg_pull_none>,
|
|
|
++ /* gmac1_txd1 */
|
|
|
++ <3 RK_PB4 1 &pcfg_pull_none>,
|
|
|
++ /* gmac1_txen */
|
|
|
++ <3 RK_PB5 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gmac1_rgmii_clk: gmac1-rgmii-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gmac1_rxclk */
|
|
|
++ <3 RK_PA5 1 &pcfg_pull_none>,
|
|
|
++ /* gmac1_txclk */
|
|
|
++ <3 RK_PA4 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gmac1_rgmii_bus: gmac1-rgmii-bus {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gmac1_rxd2 */
|
|
|
++ <3 RK_PA2 1 &pcfg_pull_none>,
|
|
|
++ /* gmac1_rxd3 */
|
|
|
++ <3 RK_PA3 1 &pcfg_pull_none>,
|
|
|
++ /* gmac1_txd2 */
|
|
|
++ <3 RK_PA0 1 &pcfg_pull_none>,
|
|
|
++ /* gmac1_txd3 */
|
|
|
++ <3 RK_PA1 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gmac1_ppsclk: gmac1-ppsclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gmac1_ppsclk */
|
|
|
++ <3 RK_PC1 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gmac1_ppstrig: gmac1-ppstrig {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gmac1_ppstrig */
|
|
|
++ <3 RK_PC0 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gmac1_ptp_ref_clk */
|
|
|
++ <3 RK_PB7 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gmac1_txer: gmac1-txer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gmac1_txer */
|
|
|
++ <3 RK_PB2 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ gpu {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ gpu_pins: gpu-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* gpu_avs */
|
|
|
++ <0 RK_PC5 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ hdmi {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim0_rx_cec: hdmim0-rx-cec {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim0_rx_cec */
|
|
|
++ <4 RK_PB5 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim0_rx_hpdin: hdmim0-rx-hpdin {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim0_rx_hpdin */
|
|
|
++ <4 RK_PB6 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim0_rx_scl: hdmim0-rx-scl {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim0_rx_scl */
|
|
|
++ <0 RK_PD2 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim0_rx_sda: hdmim0-rx-sda {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim0_rx_sda */
|
|
|
++ <0 RK_PD1 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim0_tx0_cec: hdmim0-tx0-cec {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim0_tx0_cec */
|
|
|
++ <4 RK_PC1 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim0_tx0_hpd: hdmim0-tx0-hpd {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim0_tx0_hpd */
|
|
|
++ <1 RK_PA5 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim0_tx0_scl: hdmim0-tx0-scl {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim0_tx0_scl */
|
|
|
++ <4 RK_PB7 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim0_tx0_sda: hdmim0-tx0-sda {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim0_tx0_sda */
|
|
|
++ <4 RK_PC0 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim0_tx1_hpd: hdmim0-tx1-hpd {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim0_tx1_hpd */
|
|
|
++ <1 RK_PA6 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_rx_cec: hdmim1-rx-cec {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_rx_cec */
|
|
|
++ <3 RK_PD1 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_rx_hpdin: hdmim1-rx-hpdin {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_rx_hpdin */
|
|
|
++ <3 RK_PD4 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_rx_scl: hdmim1-rx-scl {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_rx_scl */
|
|
|
++ <3 RK_PD2 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_rx_sda: hdmim1-rx-sda {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_rx_sda */
|
|
|
++ <3 RK_PD3 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_tx0_cec: hdmim1-tx0-cec {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_tx0_cec */
|
|
|
++ <0 RK_PD1 13 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_tx0_hpd: hdmim1-tx0-hpd {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_tx0_hpd */
|
|
|
++ <3 RK_PD4 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_tx0_scl: hdmim1-tx0-scl {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_tx0_scl */
|
|
|
++ <0 RK_PD5 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_tx0_sda: hdmim1-tx0-sda {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_tx0_sda */
|
|
|
++ <0 RK_PD4 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_tx1_cec: hdmim1-tx1-cec {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_tx1_cec */
|
|
|
++ <0 RK_PD2 13 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_tx1_hpd: hdmim1-tx1-hpd {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_tx1_hpd */
|
|
|
++ <3 RK_PB7 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_tx1_scl: hdmim1-tx1-scl {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_tx1_scl */
|
|
|
++ <3 RK_PC6 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim1_tx1_sda: hdmim1-tx1-sda {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim1_tx1_sda */
|
|
|
++ <3 RK_PC5 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim2_rx_cec: hdmim2-rx-cec {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim2_rx_cec */
|
|
|
++ <1 RK_PB7 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim2_rx_hpdin: hdmim2-rx-hpdin {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim2_rx_hpdin */
|
|
|
++ <1 RK_PB6 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim2_rx_scl: hdmim2-rx-scl {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim2_rx_scl */
|
|
|
++ <1 RK_PD6 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim2_rx_sda: hdmim2-rx-sda {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim2_rx_sda */
|
|
|
++ <1 RK_PD7 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim2_tx0_scl: hdmim2-tx0-scl {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim2_tx0_scl */
|
|
|
++ <3 RK_PC7 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim2_tx0_sda: hdmim2-tx0-sda {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim2_tx0_sda */
|
|
|
++ <3 RK_PD0 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim2_tx1_cec: hdmim2-tx1-cec {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim2_tx1_cec */
|
|
|
++ <3 RK_PC4 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim2_tx1_scl: hdmim2-tx1-scl {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim2_tx1_scl */
|
|
|
++ <1 RK_PA4 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmim2_tx1_sda: hdmim2-tx1-sda {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmim2_tx1_sda */
|
|
|
++ <1 RK_PA3 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmi_debug0: hdmi-debug0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmi_debug0 */
|
|
|
++ <1 RK_PA7 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmi_debug1: hdmi-debug1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmi_debug1 */
|
|
|
++ <1 RK_PB0 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmi_debug2: hdmi-debug2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmi_debug2 */
|
|
|
++ <1 RK_PB1 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmi_debug3: hdmi-debug3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmi_debug3 */
|
|
|
++ <1 RK_PB2 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmi_debug4: hdmi-debug4 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmi_debug4 */
|
|
|
++ <1 RK_PB3 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmi_debug5: hdmi-debug5 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmi_debug5 */
|
|
|
++ <1 RK_PB4 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ hdmi_debug6: hdmi-debug6 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* hdmi_debug6 */
|
|
|
++ <1 RK_PA0 7 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c0m0_xfer: i2c0m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c0_scl_m0 */
|
|
|
++ <0 RK_PB3 2 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c0_sda_m0 */
|
|
|
++ <0 RK_PA6 2 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c0m2_xfer: i2c0m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c0_scl_m2 */
|
|
|
++ <0 RK_PD1 3 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c0_sda_m2 */
|
|
|
++ <0 RK_PD2 3 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c1m0_xfer: i2c1m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c1_scl_m0 */
|
|
|
++ <0 RK_PB5 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c1_sda_m0 */
|
|
|
++ <0 RK_PB6 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c1m1_xfer: i2c1m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c1_scl_m1 */
|
|
|
++ <0 RK_PB0 2 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c1_sda_m1 */
|
|
|
++ <0 RK_PB1 2 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c1m2_xfer: i2c1m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c1_scl_m2 */
|
|
|
++ <0 RK_PD4 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c1_sda_m2 */
|
|
|
++ <0 RK_PD5 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c1m3_xfer: i2c1m3-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c1_scl_m3 */
|
|
|
++ <2 RK_PD4 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c1_sda_m3 */
|
|
|
++ <2 RK_PD5 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c1m4_xfer: i2c1m4-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c1_scl_m4 */
|
|
|
++ <1 RK_PD2 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c1_sda_m4 */
|
|
|
++ <1 RK_PD3 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c2 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c2m0_xfer: i2c2m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c2_scl_m0 */
|
|
|
++ <0 RK_PB7 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c2_sda_m0 */
|
|
|
++ <0 RK_PC0 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c2m2_xfer: i2c2m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c2_scl_m2 */
|
|
|
++ <2 RK_PA3 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c2_sda_m2 */
|
|
|
++ <2 RK_PA2 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c2m3_xfer: i2c2m3-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c2_scl_m3 */
|
|
|
++ <1 RK_PC5 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c2_sda_m3 */
|
|
|
++ <1 RK_PC4 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c2m4_xfer: i2c2m4-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c2_scl_m4 */
|
|
|
++ <1 RK_PA1 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c2_sda_m4 */
|
|
|
++ <1 RK_PA0 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c3 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c3m0_xfer: i2c3m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c3_scl_m0 */
|
|
|
++ <1 RK_PC1 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c3_sda_m0 */
|
|
|
++ <1 RK_PC0 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c3m1_xfer: i2c3m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c3_scl_m1 */
|
|
|
++ <3 RK_PB7 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c3_sda_m1 */
|
|
|
++ <3 RK_PC0 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c3m2_xfer: i2c3m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c3_scl_m2 */
|
|
|
++ <4 RK_PA4 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c3_sda_m2 */
|
|
|
++ <4 RK_PA5 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c3m4_xfer: i2c3m4-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c3_scl_m4 */
|
|
|
++ <4 RK_PD0 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c3_sda_m4 */
|
|
|
++ <4 RK_PD1 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c4 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c4m0_xfer: i2c4m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c4_scl_m0 */
|
|
|
++ <3 RK_PA6 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c4_sda_m0 */
|
|
|
++ <3 RK_PA5 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c4m2_xfer: i2c4m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c4_scl_m2 */
|
|
|
++ <0 RK_PC5 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c4_sda_m2 */
|
|
|
++ <0 RK_PC4 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c4m3_xfer: i2c4m3-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c4_scl_m3 */
|
|
|
++ <1 RK_PA3 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c4_sda_m3 */
|
|
|
++ <1 RK_PA2 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c4m4_xfer: i2c4m4-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c4_scl_m4 */
|
|
|
++ <1 RK_PC7 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c4_sda_m4 */
|
|
|
++ <1 RK_PC6 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c5 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c5m0_xfer: i2c5m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c5_scl_m0 */
|
|
|
++ <3 RK_PC7 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c5_sda_m0 */
|
|
|
++ <3 RK_PD0 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c5m1_xfer: i2c5m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c5_scl_m1 */
|
|
|
++ <4 RK_PB6 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c5_sda_m1 */
|
|
|
++ <4 RK_PB7 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c5m2_xfer: i2c5m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c5_scl_m2 */
|
|
|
++ <4 RK_PA6 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c5_sda_m2 */
|
|
|
++ <4 RK_PA7 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c5m3_xfer: i2c5m3-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c5_scl_m3 */
|
|
|
++ <1 RK_PB6 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c5_sda_m3 */
|
|
|
++ <1 RK_PB7 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c6 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c6m0_xfer: i2c6m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c6_scl_m0 */
|
|
|
++ <0 RK_PD0 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c6_sda_m0 */
|
|
|
++ <0 RK_PC7 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c6m1_xfer: i2c6m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c6_scl_m1 */
|
|
|
++ <1 RK_PC3 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c6_sda_m1 */
|
|
|
++ <1 RK_PC2 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c6m3_xfer: i2c6m3-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c6_scl_m3 */
|
|
|
++ <4 RK_PB1 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c6_sda_m3 */
|
|
|
++ <4 RK_PB0 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c6m4_xfer: i2c6m4-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c6_scl_m4 */
|
|
|
++ <3 RK_PA1 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c6_sda_m4 */
|
|
|
++ <3 RK_PA0 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c7 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c7m0_xfer: i2c7m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c7_scl_m0 */
|
|
|
++ <1 RK_PD0 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c7_sda_m0 */
|
|
|
++ <1 RK_PD1 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c7m2_xfer: i2c7m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c7_scl_m2 */
|
|
|
++ <3 RK_PD2 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c7_sda_m2 */
|
|
|
++ <3 RK_PD3 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c7m3_xfer: i2c7m3-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c7_scl_m3 */
|
|
|
++ <4 RK_PB2 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c7_sda_m3 */
|
|
|
++ <4 RK_PB3 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2c8 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c8m0_xfer: i2c8m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c8_scl_m0 */
|
|
|
++ <4 RK_PD2 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c8_sda_m0 */
|
|
|
++ <4 RK_PD3 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c8m2_xfer: i2c8m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c8_scl_m2 */
|
|
|
++ <1 RK_PD6 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c8_sda_m2 */
|
|
|
++ <1 RK_PD7 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c8m3_xfer: i2c8m3-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c8_scl_m3 */
|
|
|
++ <4 RK_PC0 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c8_sda_m3 */
|
|
|
++ <4 RK_PC1 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2c8m4_xfer: i2c8m4-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2c8_scl_m4 */
|
|
|
++ <3 RK_PC2 9 &pcfg_pull_none_smt>,
|
|
|
++ /* i2c8_sda_m4 */
|
|
|
++ <3 RK_PC3 9 &pcfg_pull_none_smt>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_lrck: i2s0-lrck {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_lrck */
|
|
|
++ <1 RK_PC5 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_mclk: i2s0-mclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_mclk */
|
|
|
++ <1 RK_PC2 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_sclk: i2s0-sclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_sclk */
|
|
|
++ <1 RK_PC3 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_sdi0: i2s0-sdi0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_sdi0 */
|
|
|
++ <1 RK_PD4 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_sdi1: i2s0-sdi1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_sdi1 */
|
|
|
++ <1 RK_PD3 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_sdi2: i2s0-sdi2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_sdi2 */
|
|
|
++ <1 RK_PD2 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_sdi3: i2s0-sdi3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_sdi3 */
|
|
|
++ <1 RK_PD1 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_sdo0: i2s0-sdo0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_sdo0 */
|
|
|
++ <1 RK_PC7 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_sdo1: i2s0-sdo1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_sdo1 */
|
|
|
++ <1 RK_PD0 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_sdo2: i2s0-sdo2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_sdo2 */
|
|
|
++ <1 RK_PD1 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s0_sdo3: i2s0-sdo3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s0_sdo3 */
|
|
|
++ <1 RK_PD2 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_lrck: i2s1m0-lrck {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_lrck */
|
|
|
++ <4 RK_PA2 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_mclk: i2s1m0-mclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_mclk */
|
|
|
++ <4 RK_PA0 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_sclk: i2s1m0-sclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_sclk */
|
|
|
++ <4 RK_PA1 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_sdi0: i2s1m0-sdi0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_sdi0 */
|
|
|
++ <4 RK_PA5 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_sdi1: i2s1m0-sdi1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_sdi1 */
|
|
|
++ <4 RK_PA6 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_sdi2: i2s1m0-sdi2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_sdi2 */
|
|
|
++ <4 RK_PA7 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_sdi3: i2s1m0-sdi3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_sdi3 */
|
|
|
++ <4 RK_PB0 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_sdo0: i2s1m0-sdo0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_sdo0 */
|
|
|
++ <4 RK_PB1 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_sdo1: i2s1m0-sdo1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_sdo1 */
|
|
|
++ <4 RK_PB2 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_sdo2: i2s1m0-sdo2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_sdo2 */
|
|
|
++ <4 RK_PB3 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m0_sdo3: i2s1m0-sdo3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m0_sdo3 */
|
|
|
++ <4 RK_PB4 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_lrck: i2s1m1-lrck {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_lrck */
|
|
|
++ <0 RK_PB7 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_mclk: i2s1m1-mclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_mclk */
|
|
|
++ <0 RK_PB5 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_sclk: i2s1m1-sclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_sclk */
|
|
|
++ <0 RK_PB6 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_sdi0: i2s1m1-sdi0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_sdi0 */
|
|
|
++ <0 RK_PC5 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_sdi1: i2s1m1-sdi1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_sdi1 */
|
|
|
++ <0 RK_PC6 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_sdi2: i2s1m1-sdi2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_sdi2 */
|
|
|
++ <0 RK_PC7 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_sdi3: i2s1m1-sdi3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_sdi3 */
|
|
|
++ <0 RK_PD0 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_sdo0: i2s1m1-sdo0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_sdo0 */
|
|
|
++ <0 RK_PD1 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_sdo1: i2s1m1-sdo1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_sdo1 */
|
|
|
++ <0 RK_PD2 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_sdo2: i2s1m1-sdo2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_sdo2 */
|
|
|
++ <0 RK_PD4 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s1m1_sdo3: i2s1m1-sdo3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s1m1_sdo3 */
|
|
|
++ <0 RK_PD5 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s2 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s2m0_lrck: i2s2m0-lrck {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s2m0_lrck */
|
|
|
++ <2 RK_PC0 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s2m0_mclk: i2s2m0-mclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s2m0_mclk */
|
|
|
++ <2 RK_PB6 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s2m0_sclk: i2s2m0-sclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s2m0_sclk */
|
|
|
++ <2 RK_PB7 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s2m0_sdi: i2s2m0-sdi {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s2m0_sdi */
|
|
|
++ <2 RK_PC3 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s2m0_sdo: i2s2m0-sdo {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s2m0_sdo */
|
|
|
++ <4 RK_PC3 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s2m1_lrck: i2s2m1-lrck {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s2m1_lrck */
|
|
|
++ <3 RK_PB6 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s2m1_mclk: i2s2m1-mclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s2m1_mclk */
|
|
|
++ <3 RK_PB4 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s2m1_sclk: i2s2m1-sclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s2m1_sclk */
|
|
|
++ <3 RK_PB5 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s2m1_sdi: i2s2m1-sdi {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s2m1_sdi */
|
|
|
++ <3 RK_PB2 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s2m1_sdo: i2s2m1-sdo {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s2m1_sdo */
|
|
|
++ <3 RK_PB3 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ i2s3 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s3_lrck: i2s3-lrck {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s3_lrck */
|
|
|
++ <3 RK_PA2 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s3_mclk: i2s3-mclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s3_mclk */
|
|
|
++ <3 RK_PA0 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s3_sclk: i2s3-sclk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s3_sclk */
|
|
|
++ <3 RK_PA1 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s3_sdi: i2s3-sdi {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s3_sdi */
|
|
|
++ <3 RK_PA4 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ i2s3_sdo: i2s3-sdo {
|
|
|
++ rockchip,pins =
|
|
|
++ /* i2s3_sdo */
|
|
|
++ <3 RK_PA3 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ jtag {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ jtagm0_pins: jtagm0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* jtag_tck_m0 */
|
|
|
++ <4 RK_PD2 5 &pcfg_pull_none>,
|
|
|
++ /* jtag_tms_m0 */
|
|
|
++ <4 RK_PD3 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ jtagm1_pins: jtagm1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* jtag_tck_m1 */
|
|
|
++ <4 RK_PD0 5 &pcfg_pull_none>,
|
|
|
++ /* jtag_tms_m1 */
|
|
|
++ <4 RK_PD1 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ jtagm2_pins: jtagm2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* jtag_tck_m2 */
|
|
|
++ <0 RK_PB5 2 &pcfg_pull_none>,
|
|
|
++ /* jtag_tms_m2 */
|
|
|
++ <0 RK_PB6 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ litcpu {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ litcpu_pins: litcpu-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* litcpu_avs */
|
|
|
++ <0 RK_PD3 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ mcu {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mcum0_pins: mcum0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mcu_jtag_tck_m0 */
|
|
|
++ <4 RK_PD4 5 &pcfg_pull_none>,
|
|
|
++ /* mcu_jtag_tms_m0 */
|
|
|
++ <4 RK_PD5 5 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mcum1_pins: mcum1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mcu_jtag_tck_m1 */
|
|
|
++ <3 RK_PD4 6 &pcfg_pull_none>,
|
|
|
++ /* mcu_jtag_tms_m1 */
|
|
|
++ <3 RK_PD5 6 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ mipi {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipim0_camera0_clk: mipim0-camera0-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipim0_camera0_clk */
|
|
|
++ <4 RK_PB1 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipim0_camera1_clk: mipim0-camera1-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipim0_camera1_clk */
|
|
|
++ <1 RK_PB6 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipim0_camera2_clk: mipim0-camera2-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipim0_camera2_clk */
|
|
|
++ <1 RK_PB7 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipim0_camera3_clk: mipim0-camera3-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipim0_camera3_clk */
|
|
|
++ <1 RK_PD6 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipim0_camera4_clk: mipim0-camera4-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipim0_camera4_clk */
|
|
|
++ <1 RK_PD7 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipim1_camera0_clk: mipim1-camera0-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipim1_camera0_clk */
|
|
|
++ <3 RK_PA5 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipim1_camera1_clk: mipim1-camera1-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipim1_camera1_clk */
|
|
|
++ <3 RK_PA6 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipim1_camera2_clk: mipim1-camera2-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipim1_camera2_clk */
|
|
|
++ <3 RK_PA7 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipim1_camera3_clk: mipim1-camera3-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipim1_camera3_clk */
|
|
|
++ <3 RK_PB0 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipim1_camera4_clk: mipim1-camera4-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipim1_camera4_clk */
|
|
|
++ <3 RK_PB1 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipi_te0: mipi-te0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipi_te0 */
|
|
|
++ <3 RK_PC2 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ mipi_te1: mipi-te1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* mipi_te1 */
|
|
|
++ <3 RK_PC3 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ npu {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ npu_pins: npu-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* npu_avs */
|
|
|
++ <0 RK_PC6 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie20x1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie20x1m0_pins: pcie20x1m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie20x1_2_clkreqn_m0 */
|
|
|
++ <3 RK_PC7 4 &pcfg_pull_none>,
|
|
|
++ /* pcie20x1_2_perstn_m0 */
|
|
|
++ <3 RK_PD1 4 &pcfg_pull_none>,
|
|
|
++ /* pcie20x1_2_waken_m0 */
|
|
|
++ <3 RK_PD0 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie20x1m1_pins: pcie20x1m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie20x1_2_clkreqn_m1 */
|
|
|
++ <4 RK_PB7 4 &pcfg_pull_none>,
|
|
|
++ /* pcie20x1_2_perstn_m1 */
|
|
|
++ <4 RK_PC1 4 &pcfg_pull_none>,
|
|
|
++ /* pcie20x1_2_waken_m1 */
|
|
|
++ <4 RK_PC0 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie20x1_2_button_rstn */
|
|
|
++ <4 RK_PB3 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie30phy {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30phy_pins: pcie30phy-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30phy_dtb0 */
|
|
|
++ <1 RK_PC4 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30phy_dtb1 */
|
|
|
++ <1 RK_PD1 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie30x1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x1m0_pins: pcie30x1m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x1_0_clkreqn_m0 */
|
|
|
++ <0 RK_PC0 12 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_0_perstn_m0 */
|
|
|
++ <0 RK_PC5 12 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_0_waken_m0 */
|
|
|
++ <0 RK_PC4 12 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_1_clkreqn_m0 */
|
|
|
++ <0 RK_PB5 12 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_1_perstn_m0 */
|
|
|
++ <0 RK_PB7 12 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_1_waken_m0 */
|
|
|
++ <0 RK_PB6 12 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x1m1_pins: pcie30x1m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x1_0_clkreqn_m1 */
|
|
|
++ <4 RK_PA3 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_0_perstn_m1 */
|
|
|
++ <4 RK_PA5 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_0_waken_m1 */
|
|
|
++ <4 RK_PA4 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_1_clkreqn_m1 */
|
|
|
++ <4 RK_PA0 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_1_perstn_m1 */
|
|
|
++ <4 RK_PA2 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_1_waken_m1 */
|
|
|
++ <4 RK_PA1 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x1m2_pins: pcie30x1m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x1_0_clkreqn_m2 */
|
|
|
++ <1 RK_PB5 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_0_perstn_m2 */
|
|
|
++ <1 RK_PB4 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_0_waken_m2 */
|
|
|
++ <1 RK_PB3 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_1_clkreqn_m2 */
|
|
|
++ <1 RK_PA0 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_1_perstn_m2 */
|
|
|
++ <1 RK_PA7 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x1_1_waken_m2 */
|
|
|
++ <1 RK_PA1 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x1_0_button_rstn */
|
|
|
++ <4 RK_PB1 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x1_1_button_rstn */
|
|
|
++ <4 RK_PB2 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie30x2 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x2m0_pins: pcie30x2m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x2_clkreqn_m0 */
|
|
|
++ <0 RK_PD1 12 &pcfg_pull_none>,
|
|
|
++ /* pcie30x2_perstn_m0 */
|
|
|
++ <0 RK_PD4 12 &pcfg_pull_none>,
|
|
|
++ /* pcie30x2_waken_m0 */
|
|
|
++ <0 RK_PD2 12 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x2m1_pins: pcie30x2m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x2_clkreqn_m1 */
|
|
|
++ <4 RK_PA6 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x2_perstn_m1 */
|
|
|
++ <4 RK_PB0 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x2_waken_m1 */
|
|
|
++ <4 RK_PA7 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x2m2_pins: pcie30x2m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x2_clkreqn_m2 */
|
|
|
++ <3 RK_PD2 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x2_perstn_m2 */
|
|
|
++ <3 RK_PD4 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x2_waken_m2 */
|
|
|
++ <3 RK_PD3 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x2m3_pins: pcie30x2m3-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x2_clkreqn_m3 */
|
|
|
++ <1 RK_PD7 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x2_perstn_m3 */
|
|
|
++ <1 RK_PB7 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x2_waken_m3 */
|
|
|
++ <1 RK_PB6 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x2_button_rstn: pcie30x2-button-rstn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x2_button_rstn */
|
|
|
++ <3 RK_PC1 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pcie30x4 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x4m0_pins: pcie30x4m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x4_clkreqn_m0 */
|
|
|
++ <0 RK_PC6 12 &pcfg_pull_none>,
|
|
|
++ /* pcie30x4_perstn_m0 */
|
|
|
++ <0 RK_PD0 12 &pcfg_pull_none>,
|
|
|
++ /* pcie30x4_waken_m0 */
|
|
|
++ <0 RK_PC7 12 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x4m1_pins: pcie30x4m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x4_clkreqn_m1 */
|
|
|
++ <4 RK_PB4 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x4_perstn_m1 */
|
|
|
++ <4 RK_PB6 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x4_waken_m1 */
|
|
|
++ <4 RK_PB5 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x4m2_pins: pcie30x4m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x4_clkreqn_m2 */
|
|
|
++ <3 RK_PC4 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x4_perstn_m2 */
|
|
|
++ <3 RK_PC6 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x4_waken_m2 */
|
|
|
++ <3 RK_PC5 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x4m3_pins: pcie30x4m3-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x4_clkreqn_m3 */
|
|
|
++ <1 RK_PB0 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x4_perstn_m3 */
|
|
|
++ <1 RK_PB2 4 &pcfg_pull_none>,
|
|
|
++ /* pcie30x4_waken_m3 */
|
|
|
++ <1 RK_PB1 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pcie30x4_button_rstn: pcie30x4-button-rstn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pcie30x4_button_rstn */
|
|
|
++ <3 RK_PD5 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pdm0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m0_clk: pdm0m0-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0_clk0_m0 */
|
|
|
++ <1 RK_PC6 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m0_clk1: pdm0m0-clk1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0m0_clk1 */
|
|
|
++ <1 RK_PC4 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m0_sdi0: pdm0m0-sdi0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0m0_sdi0 */
|
|
|
++ <1 RK_PD5 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m0_sdi1: pdm0m0-sdi1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0m0_sdi1 */
|
|
|
++ <1 RK_PD1 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m0_sdi2: pdm0m0-sdi2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0m0_sdi2 */
|
|
|
++ <1 RK_PD2 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m0_sdi3: pdm0m0-sdi3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0m0_sdi3 */
|
|
|
++ <1 RK_PD3 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m1_clk: pdm0m1-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0_clk0_m1 */
|
|
|
++ <0 RK_PC0 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m1_clk1: pdm0m1-clk1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0m1_clk1 */
|
|
|
++ <0 RK_PC4 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m1_sdi0: pdm0m1-sdi0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0m1_sdi0 */
|
|
|
++ <0 RK_PC7 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m1_sdi1: pdm0m1-sdi1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0m1_sdi1 */
|
|
|
++ <0 RK_PD0 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m1_sdi2: pdm0m1-sdi2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0m1_sdi2 */
|
|
|
++ <0 RK_PD4 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm0m1_sdi3: pdm0m1-sdi3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm0m1_sdi3 */
|
|
|
++ <0 RK_PD6 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pdm1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m0_clk: pdm1m0-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1_clk0_m0 */
|
|
|
++ <4 RK_PD5 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m0_clk1: pdm1m0-clk1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1m0_clk1 */
|
|
|
++ <4 RK_PD4 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m0_sdi0: pdm1m0-sdi0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1m0_sdi0 */
|
|
|
++ <4 RK_PD3 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m0_sdi1: pdm1m0-sdi1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1m0_sdi1 */
|
|
|
++ <4 RK_PD2 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m0_sdi2: pdm1m0-sdi2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1m0_sdi2 */
|
|
|
++ <4 RK_PD1 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m0_sdi3: pdm1m0-sdi3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1m0_sdi3 */
|
|
|
++ <4 RK_PD0 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m1_clk: pdm1m1-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1_clk0_m1 */
|
|
|
++ <1 RK_PB4 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m1_clk1: pdm1m1-clk1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1m1_clk1 */
|
|
|
++ <1 RK_PB3 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m1_sdi0: pdm1m1-sdi0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1m1_sdi0 */
|
|
|
++ <1 RK_PA7 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m1_sdi1: pdm1m1-sdi1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1m1_sdi1 */
|
|
|
++ <1 RK_PB0 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m1_sdi2: pdm1m1-sdi2 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1m1_sdi2 */
|
|
|
++ <1 RK_PB1 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pdm1m1_sdi3: pdm1m1-sdi3 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pdm1m1_sdi3 */
|
|
|
++ <1 RK_PB2 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pmic {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pmic_pins: pmic-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pmic_int_l */
|
|
|
++ <0 RK_PA7 0 &pcfg_pull_up>,
|
|
|
++ /* pmic_sleep1 */
|
|
|
++ <0 RK_PA2 1 &pcfg_pull_none>,
|
|
|
++ /* pmic_sleep2 */
|
|
|
++ <0 RK_PA3 1 &pcfg_pull_none>,
|
|
|
++ /* pmic_sleep3 */
|
|
|
++ <0 RK_PC1 1 &pcfg_pull_none>,
|
|
|
++ /* pmic_sleep4 */
|
|
|
++ <0 RK_PC2 1 &pcfg_pull_none>,
|
|
|
++ /* pmic_sleep5 */
|
|
|
++ <0 RK_PC3 1 &pcfg_pull_none>,
|
|
|
++ /* pmic_sleep6 */
|
|
|
++ <0 RK_PD6 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pmu {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pmu_pins: pmu-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pmu_debug */
|
|
|
++ <0 RK_PA5 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm0m0_pins: pwm0m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm0_m0 */
|
|
|
++ <0 RK_PB7 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm0m1_pins: pwm0m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm0_m1 */
|
|
|
++ <1 RK_PD2 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm0m2_pins: pwm0m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm0_m2 */
|
|
|
++ <1 RK_PA2 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm1m0_pins: pwm1m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm1_m0 */
|
|
|
++ <0 RK_PC0 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm1m1_pins: pwm1m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm1_m1 */
|
|
|
++ <1 RK_PD3 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm1m2_pins: pwm1m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm1_m2 */
|
|
|
++ <1 RK_PA3 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm2 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm2m0_pins: pwm2m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm2_m0 */
|
|
|
++ <0 RK_PC4 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm2m1_pins: pwm2m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm2_m1 */
|
|
|
++ <3 RK_PB1 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm3 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm3m0_pins: pwm3m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm3_ir_m0 */
|
|
|
++ <0 RK_PD4 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm3m1_pins: pwm3m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm3_ir_m1 */
|
|
|
++ <3 RK_PB2 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm3m2_pins: pwm3m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm3_ir_m2 */
|
|
|
++ <1 RK_PC2 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm3m3_pins: pwm3m3-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm3_ir_m3 */
|
|
|
++ <1 RK_PA7 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm4 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm4m0_pins: pwm4m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm4_m0 */
|
|
|
++ <0 RK_PC5 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm5 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm5m0_pins: pwm5m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm5_m0 */
|
|
|
++ <0 RK_PB1 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm5m1_pins: pwm5m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm5_m1 */
|
|
|
++ <0 RK_PC6 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm6 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm6m0_pins: pwm6m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm6_m0 */
|
|
|
++ <0 RK_PC7 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm6m1_pins: pwm6m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm6_m1 */
|
|
|
++ <4 RK_PC1 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm7 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm7m0_pins: pwm7m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm7_ir_m0 */
|
|
|
++ <0 RK_PD0 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm7m1_pins: pwm7m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm7_ir_m1 */
|
|
|
++ <4 RK_PD4 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm7m2_pins: pwm7m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm7_ir_m2 */
|
|
|
++ <1 RK_PC3 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm8 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm8m0_pins: pwm8m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm8_m0 */
|
|
|
++ <3 RK_PA7 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm8m1_pins: pwm8m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm8_m1 */
|
|
|
++ <4 RK_PD0 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm8m2_pins: pwm8m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm8_m2 */
|
|
|
++ <3 RK_PD0 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm9 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm9m0_pins: pwm9m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm9_m0 */
|
|
|
++ <3 RK_PB0 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm9m1_pins: pwm9m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm9_m1 */
|
|
|
++ <4 RK_PD1 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm9m2_pins: pwm9m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm9_m2 */
|
|
|
++ <3 RK_PD1 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm10 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm10m0_pins: pwm10m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm10_m0 */
|
|
|
++ <3 RK_PA0 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm10m1_pins: pwm10m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm10_m1 */
|
|
|
++ <4 RK_PD3 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm10m2_pins: pwm10m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm10_m2 */
|
|
|
++ <3 RK_PD3 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm11 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm11m0_pins: pwm11m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm11_ir_m0 */
|
|
|
++ <3 RK_PA1 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm11m1_pins: pwm11m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm11_ir_m1 */
|
|
|
++ <4 RK_PB4 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm11m2_pins: pwm11m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm11_ir_m2 */
|
|
|
++ <1 RK_PC4 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm11m3_pins: pwm11m3-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm11_ir_m3 */
|
|
|
++ <3 RK_PD5 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm12 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm12m0_pins: pwm12m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm12_m0 */
|
|
|
++ <3 RK_PB5 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm12m1_pins: pwm12m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm12_m1 */
|
|
|
++ <4 RK_PB5 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm13 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm13m0_pins: pwm13m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm13_m0 */
|
|
|
++ <3 RK_PB6 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm13m1_pins: pwm13m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm13_m1 */
|
|
|
++ <4 RK_PB6 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm13m2_pins: pwm13m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm13_m2 */
|
|
|
++ <1 RK_PB7 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm14 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm14m0_pins: pwm14m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm14_m0 */
|
|
|
++ <3 RK_PC2 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm14m1_pins: pwm14m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm14_m1 */
|
|
|
++ <4 RK_PB2 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm14m2_pins: pwm14m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm14_m2 */
|
|
|
++ <1 RK_PD6 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ pwm15 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm15m0_pins: pwm15m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm15_ir_m0 */
|
|
|
++ <3 RK_PC3 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm15m1_pins: pwm15m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm15_ir_m1 */
|
|
|
++ <4 RK_PB3 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm15m2_pins: pwm15m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm15_ir_m2 */
|
|
|
++ <1 RK_PC6 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ pwm15m3_pins: pwm15m3-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* pwm15_ir_m3 */
|
|
|
++ <1 RK_PD7 11 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ refclk {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ refclk_pins: refclk-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* refclk_out */
|
|
|
++ <0 RK_PA0 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ sata {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sata_pins: sata-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sata_cp_pod */
|
|
|
++ <0 RK_PC6 13 &pcfg_pull_none>,
|
|
|
++ /* sata_cpdet */
|
|
|
++ <0 RK_PD4 13 &pcfg_pull_none>,
|
|
|
++ /* sata_mp_switch */
|
|
|
++ <0 RK_PD5 13 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ sata0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sata0m0_pins: sata0m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sata0_act_led_m0 */
|
|
|
++ <4 RK_PB6 6 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sata0m1_pins: sata0m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sata0_act_led_m1 */
|
|
|
++ <1 RK_PB3 6 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ sata1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sata1m0_pins: sata1m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sata1_act_led_m0 */
|
|
|
++ <4 RK_PB5 6 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sata1m1_pins: sata1m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sata1_act_led_m1 */
|
|
|
++ <1 RK_PA1 6 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ sata2 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sata2m0_pins: sata2m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sata2_act_led_m0 */
|
|
|
++ <4 RK_PB1 6 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sata2m1_pins: sata2m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sata2_act_led_m1 */
|
|
|
++ <1 RK_PB7 6 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ sdio {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sdiom1_pins: sdiom1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sdio_clk_m1 */
|
|
|
++ <3 RK_PA5 2 &pcfg_pull_none>,
|
|
|
++ /* sdio_cmd_m1 */
|
|
|
++ <3 RK_PA4 2 &pcfg_pull_none>,
|
|
|
++ /* sdio_d0_m1 */
|
|
|
++ <3 RK_PA0 2 &pcfg_pull_none>,
|
|
|
++ /* sdio_d1_m1 */
|
|
|
++ <3 RK_PA1 2 &pcfg_pull_none>,
|
|
|
++ /* sdio_d2_m1 */
|
|
|
++ <3 RK_PA2 2 &pcfg_pull_none>,
|
|
|
++ /* sdio_d3_m1 */
|
|
|
++ <3 RK_PA3 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ sdmmc {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sdmmc_bus4: sdmmc-bus4 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sdmmc_d0 */
|
|
|
++ <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* sdmmc_d1 */
|
|
|
++ <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* sdmmc_d2 */
|
|
|
++ <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
|
|
|
++ /* sdmmc_d3 */
|
|
|
++ <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sdmmc_clk: sdmmc-clk {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sdmmc_clk */
|
|
|
++ <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sdmmc_cmd: sdmmc-cmd {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sdmmc_cmd */
|
|
|
++ <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sdmmc_det: sdmmc-det {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sdmmc_det */
|
|
|
++ <0 RK_PA4 1 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ sdmmc_pwren: sdmmc-pwren {
|
|
|
++ rockchip,pins =
|
|
|
++ /* sdmmc_pwren */
|
|
|
++ <0 RK_PA5 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ spdif0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spdif0m0_tx: spdif0m0-tx {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spdif0m0_tx */
|
|
|
++ <1 RK_PB6 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spdif0m1_tx: spdif0m1-tx {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spdif0m1_tx */
|
|
|
++ <4 RK_PB4 6 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ spdif1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spdif1m0_tx: spdif1m0-tx {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spdif1m0_tx */
|
|
|
++ <1 RK_PB7 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spdif1m1_tx: spdif1m1-tx {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spdif1m1_tx */
|
|
|
++ <4 RK_PB1 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spdif1m2_tx: spdif1m2-tx {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spdif1m2_tx */
|
|
|
++ <4 RK_PC1 3 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ spi0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m0_pins: spi0m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_clk_m0 */
|
|
|
++ <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi0_miso_m0 */
|
|
|
++ <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi0_mosi_m0 */
|
|
|
++ <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m0_cs0: spi0m0-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_cs0_m0 */
|
|
|
++ <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m0_cs1: spi0m0-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_cs1_m0 */
|
|
|
++ <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m1_pins: spi0m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_clk_m1 */
|
|
|
++ <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi0_miso_m1 */
|
|
|
++ <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi0_mosi_m1 */
|
|
|
++ <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m1_cs0: spi0m1-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_cs0_m1 */
|
|
|
++ <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m1_cs1: spi0m1-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_cs1_m1 */
|
|
|
++ <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m2_pins: spi0m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_clk_m2 */
|
|
|
++ <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi0_miso_m2 */
|
|
|
++ <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi0_mosi_m2 */
|
|
|
++ <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m2_cs0: spi0m2-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_cs0_m2 */
|
|
|
++ <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m2_cs1: spi0m2-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_cs1_m2 */
|
|
|
++ <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m3_pins: spi0m3-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_clk_m3 */
|
|
|
++ <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi0_miso_m3 */
|
|
|
++ <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi0_mosi_m3 */
|
|
|
++ <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m3_cs0: spi0m3-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_cs0_m3 */
|
|
|
++ <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi0m3_cs1: spi0m3-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi0_cs1_m3 */
|
|
|
++ <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ spi1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi1m1_pins: spi1m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi1_clk_m1 */
|
|
|
++ <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi1_miso_m1 */
|
|
|
++ <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi1_mosi_m1 */
|
|
|
++ <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi1m1_cs0: spi1m1-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi1_cs0_m1 */
|
|
|
++ <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi1m1_cs1: spi1m1-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi1_cs1_m1 */
|
|
|
++ <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi1m2_pins: spi1m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi1_clk_m2 */
|
|
|
++ <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi1_miso_m2 */
|
|
|
++ <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi1_mosi_m2 */
|
|
|
++ <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi1m2_cs0: spi1m2-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi1_cs0_m2 */
|
|
|
++ <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi1m2_cs1: spi1m2-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi1_cs1_m2 */
|
|
|
++ <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ spi2 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi2m0_pins: spi2m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi2_clk_m0 */
|
|
|
++ <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi2_miso_m0 */
|
|
|
++ <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi2_mosi_m0 */
|
|
|
++ <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi2m0_cs0: spi2m0-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi2_cs0_m0 */
|
|
|
++ <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi2m0_cs1: spi2m0-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi2_cs1_m0 */
|
|
|
++ <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi2m1_pins: spi2m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi2_clk_m1 */
|
|
|
++ <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi2_miso_m1 */
|
|
|
++ <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi2_mosi_m1 */
|
|
|
++ <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi2m1_cs0: spi2m1-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi2_cs0_m1 */
|
|
|
++ <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi2m1_cs1: spi2m1-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi2_cs1_m1 */
|
|
|
++ <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi2m2_pins: spi2m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi2_clk_m2 */
|
|
|
++ <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi2_miso_m2 */
|
|
|
++ <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi2_mosi_m2 */
|
|
|
++ <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi2m2_cs0: spi2m2-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi2_cs0_m2 */
|
|
|
++ <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi2m2_cs1: spi2m2-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi2_cs1_m2 */
|
|
|
++ <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ spi3 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m1_pins: spi3m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_clk_m1 */
|
|
|
++ <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi3_miso_m1 */
|
|
|
++ <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi3_mosi_m1 */
|
|
|
++ <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m1_cs0: spi3m1-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_cs0_m1 */
|
|
|
++ <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m1_cs1: spi3m1-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_cs1_m1 */
|
|
|
++ <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m2_pins: spi3m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_clk_m2 */
|
|
|
++ <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi3_miso_m2 */
|
|
|
++ <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi3_mosi_m2 */
|
|
|
++ <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m2_cs0: spi3m2-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_cs0_m2 */
|
|
|
++ <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m2_cs1: spi3m2-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_cs1_m2 */
|
|
|
++ <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m3_pins: spi3m3-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_clk_m3 */
|
|
|
++ <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi3_miso_m3 */
|
|
|
++ <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi3_mosi_m3 */
|
|
|
++ <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m3_cs0: spi3m3-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_cs0_m3 */
|
|
|
++ <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m3_cs1: spi3m3-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_cs1_m3 */
|
|
|
++ <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ spi4 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi4m0_pins: spi4m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi4_clk_m0 */
|
|
|
++ <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi4_miso_m0 */
|
|
|
++ <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi4_mosi_m0 */
|
|
|
++ <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi4m0_cs0: spi4m0-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi4_cs0_m0 */
|
|
|
++ <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi4m0_cs1: spi4m0-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi4_cs1_m0 */
|
|
|
++ <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi4m1_pins: spi4m1-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi4_clk_m1 */
|
|
|
++ <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi4_miso_m1 */
|
|
|
++ <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi4_mosi_m1 */
|
|
|
++ <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi4m1_cs0: spi4m1-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi4_cs0_m1 */
|
|
|
++ <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi4m1_cs1: spi4m1-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi4_cs1_m1 */
|
|
|
++ <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi4m2_pins: spi4m2-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi4_clk_m2 */
|
|
|
++ <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi4_miso_m2 */
|
|
|
++ <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi4_mosi_m2 */
|
|
|
++ <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi4m2_cs0: spi4m2-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi4_cs0_m2 */
|
|
|
++ <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ tsadc {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ tsadcm1_shut: tsadcm1-shut {
|
|
|
++ rockchip,pins =
|
|
|
++ /* tsadcm1_shut */
|
|
|
++ <0 RK_PA2 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ tsadc_shut: tsadc-shut {
|
|
|
++ rockchip,pins =
|
|
|
++ /* tsadc_shut */
|
|
|
++ <0 RK_PA1 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ tsadc_shut_org: tsadc-shut-org {
|
|
|
++ rockchip,pins =
|
|
|
++ /* tsadc_shut_org */
|
|
|
++ <0 RK_PA1 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart0 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart0m0_xfer: uart0m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart0_rx_m0 */
|
|
|
++ <0 RK_PC4 4 &pcfg_pull_up>,
|
|
|
++ /* uart0_tx_m0 */
|
|
|
++ <0 RK_PC5 4 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart0m1_xfer: uart0m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart0_rx_m1 */
|
|
|
++ <0 RK_PB0 4 &pcfg_pull_up>,
|
|
|
++ /* uart0_tx_m1 */
|
|
|
++ <0 RK_PB1 4 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart0m2_xfer: uart0m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart0_rx_m2 */
|
|
|
++ <4 RK_PA4 10 &pcfg_pull_up>,
|
|
|
++ /* uart0_tx_m2 */
|
|
|
++ <4 RK_PA3 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart0_ctsn: uart0-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart0_ctsn */
|
|
|
++ <0 RK_PD1 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart0_rtsn: uart0-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart0_rtsn */
|
|
|
++ <0 RK_PC6 4 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart1m1_xfer: uart1m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart1_rx_m1 */
|
|
|
++ <1 RK_PB7 10 &pcfg_pull_up>,
|
|
|
++ /* uart1_tx_m1 */
|
|
|
++ <1 RK_PB6 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart1m1_ctsn: uart1m1-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart1m1_ctsn */
|
|
|
++ <1 RK_PD7 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart1m1_rtsn: uart1m1-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart1m1_rtsn */
|
|
|
++ <1 RK_PD6 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart1m2_xfer: uart1m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart1_rx_m2 */
|
|
|
++ <0 RK_PD2 10 &pcfg_pull_up>,
|
|
|
++ /* uart1_tx_m2 */
|
|
|
++ <0 RK_PD1 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart1m2_ctsn: uart1m2-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart1m2_ctsn */
|
|
|
++ <0 RK_PD0 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart1m2_rtsn: uart1m2-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart1m2_rtsn */
|
|
|
++ <0 RK_PC7 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart2 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart2m0_xfer: uart2m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart2_rx_m0 */
|
|
|
++ <0 RK_PB6 10 &pcfg_pull_up>,
|
|
|
++ /* uart2_tx_m0 */
|
|
|
++ <0 RK_PB5 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart2m1_xfer: uart2m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart2_rx_m1 */
|
|
|
++ <4 RK_PD1 10 &pcfg_pull_up>,
|
|
|
++ /* uart2_tx_m1 */
|
|
|
++ <4 RK_PD0 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart2m2_xfer: uart2m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart2_rx_m2 */
|
|
|
++ <3 RK_PB2 10 &pcfg_pull_up>,
|
|
|
++ /* uart2_tx_m2 */
|
|
|
++ <3 RK_PB1 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart2_ctsn: uart2-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart2_ctsn */
|
|
|
++ <3 RK_PB4 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart2_rtsn: uart2-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart2_rtsn */
|
|
|
++ <3 RK_PB3 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart3 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart3m0_xfer: uart3m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart3_rx_m0 */
|
|
|
++ <1 RK_PC0 10 &pcfg_pull_up>,
|
|
|
++ /* uart3_tx_m0 */
|
|
|
++ <1 RK_PC1 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart3m1_xfer: uart3m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart3_rx_m1 */
|
|
|
++ <3 RK_PB6 10 &pcfg_pull_up>,
|
|
|
++ /* uart3_tx_m1 */
|
|
|
++ <3 RK_PB5 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart3m2_xfer: uart3m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart3_rx_m2 */
|
|
|
++ <4 RK_PA6 10 &pcfg_pull_up>,
|
|
|
++ /* uart3_tx_m2 */
|
|
|
++ <4 RK_PA5 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart3_ctsn: uart3-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart3_ctsn */
|
|
|
++ <1 RK_PC3 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart3_rtsn: uart3-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart3_rtsn */
|
|
|
++ <1 RK_PC2 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart4 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart4m0_xfer: uart4m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart4_rx_m0 */
|
|
|
++ <1 RK_PD3 10 &pcfg_pull_up>,
|
|
|
++ /* uart4_tx_m0 */
|
|
|
++ <1 RK_PD2 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart4m1_xfer: uart4m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart4_rx_m1 */
|
|
|
++ <3 RK_PD0 10 &pcfg_pull_up>,
|
|
|
++ /* uart4_tx_m1 */
|
|
|
++ <3 RK_PD1 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart4m2_xfer: uart4m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart4_rx_m2 */
|
|
|
++ <1 RK_PB2 10 &pcfg_pull_up>,
|
|
|
++ /* uart4_tx_m2 */
|
|
|
++ <1 RK_PB3 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart4_ctsn: uart4-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart4_ctsn */
|
|
|
++ <1 RK_PC7 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart4_rtsn: uart4-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart4_rtsn */
|
|
|
++ <1 RK_PC5 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart5 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart5m0_xfer: uart5m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart5_rx_m0 */
|
|
|
++ <4 RK_PD4 10 &pcfg_pull_up>,
|
|
|
++ /* uart5_tx_m0 */
|
|
|
++ <4 RK_PD5 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart5m0_ctsn: uart5m0-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart5m0_ctsn */
|
|
|
++ <4 RK_PD2 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart5m0_rtsn: uart5m0-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart5m0_rtsn */
|
|
|
++ <4 RK_PD3 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart5m1_xfer: uart5m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart5_rx_m1 */
|
|
|
++ <3 RK_PC5 10 &pcfg_pull_up>,
|
|
|
++ /* uart5_tx_m1 */
|
|
|
++ <3 RK_PC4 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart5m1_ctsn: uart5m1-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart5m1_ctsn */
|
|
|
++ <2 RK_PA2 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart5m1_rtsn: uart5m1-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart5m1_rtsn */
|
|
|
++ <2 RK_PA3 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart5m2_xfer: uart5m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart5_rx_m2 */
|
|
|
++ <2 RK_PD4 10 &pcfg_pull_up>,
|
|
|
++ /* uart5_tx_m2 */
|
|
|
++ <2 RK_PD5 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart6 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart6m1_xfer: uart6m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart6_rx_m1 */
|
|
|
++ <1 RK_PA0 10 &pcfg_pull_up>,
|
|
|
++ /* uart6_tx_m1 */
|
|
|
++ <1 RK_PA1 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart6m1_ctsn: uart6m1-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart6m1_ctsn */
|
|
|
++ <1 RK_PA3 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart6m1_rtsn: uart6m1-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart6m1_rtsn */
|
|
|
++ <1 RK_PA2 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart6m2_xfer: uart6m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart6_rx_m2 */
|
|
|
++ <1 RK_PD1 10 &pcfg_pull_up>,
|
|
|
++ /* uart6_tx_m2 */
|
|
|
++ <1 RK_PD0 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart7 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart7m1_xfer: uart7m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart7_rx_m1 */
|
|
|
++ <3 RK_PC1 10 &pcfg_pull_up>,
|
|
|
++ /* uart7_tx_m1 */
|
|
|
++ <3 RK_PC0 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart7m1_ctsn: uart7m1-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart7m1_ctsn */
|
|
|
++ <3 RK_PC3 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart7m1_rtsn: uart7m1-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart7m1_rtsn */
|
|
|
++ <3 RK_PC2 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart7m2_xfer: uart7m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart7_rx_m2 */
|
|
|
++ <1 RK_PB4 10 &pcfg_pull_up>,
|
|
|
++ /* uart7_tx_m2 */
|
|
|
++ <1 RK_PB5 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart8 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart8m0_xfer: uart8m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart8_rx_m0 */
|
|
|
++ <4 RK_PB1 10 &pcfg_pull_up>,
|
|
|
++ /* uart8_tx_m0 */
|
|
|
++ <4 RK_PB0 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart8m0_ctsn: uart8m0-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart8m0_ctsn */
|
|
|
++ <4 RK_PB3 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart8m0_rtsn: uart8m0-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart8m0_rtsn */
|
|
|
++ <4 RK_PB2 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart8m1_xfer: uart8m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart8_rx_m1 */
|
|
|
++ <3 RK_PA3 10 &pcfg_pull_up>,
|
|
|
++ /* uart8_tx_m1 */
|
|
|
++ <3 RK_PA2 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart8m1_ctsn: uart8m1-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart8m1_ctsn */
|
|
|
++ <3 RK_PA5 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart8m1_rtsn: uart8m1-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart8m1_rtsn */
|
|
|
++ <3 RK_PA4 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart8_xfer: uart8-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart8_rx_ */
|
|
|
++ <4 RK_PB1 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart9 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart9m0_xfer: uart9m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart9_rx_m0 */
|
|
|
++ <2 RK_PC4 10 &pcfg_pull_up>,
|
|
|
++ /* uart9_tx_m0 */
|
|
|
++ <2 RK_PC2 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart9m1_xfer: uart9m1-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart9_rx_m1 */
|
|
|
++ <4 RK_PB5 10 &pcfg_pull_up>,
|
|
|
++ /* uart9_tx_m1 */
|
|
|
++ <4 RK_PB4 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart9m1_ctsn: uart9m1-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart9m1_ctsn */
|
|
|
++ <4 RK_PA1 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart9m1_rtsn: uart9m1-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart9m1_rtsn */
|
|
|
++ <4 RK_PA0 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart9m2_xfer: uart9m2-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart9_rx_m2 */
|
|
|
++ <3 RK_PD4 10 &pcfg_pull_up>,
|
|
|
++ /* uart9_tx_m2 */
|
|
|
++ <3 RK_PD5 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart9m2_ctsn: uart9m2-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart9m2_ctsn */
|
|
|
++ <3 RK_PD3 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart9m2_rtsn: uart9m2-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart9m2_rtsn */
|
|
|
++ <3 RK_PD2 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ vop {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ vop_pins: vop-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* vop_post_empty */
|
|
|
++ <1 RK_PA2 1 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++};
|
|
|
++
|
|
|
++/*
|
|
|
++ * This part is edited handly.
|
|
|
++ */
|
|
|
++&pinctrl {
|
|
|
++ bt656 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ bt656_pins: bt656-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* bt1120_clkout */
|
|
|
++ <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
|
|
|
++ /* bt1120_d0 */
|
|
|
++ <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
|
|
|
++ /* bt1120_d1 */
|
|
|
++ <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
|
|
|
++ /* bt1120_d2 */
|
|
|
++ <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
|
|
|
++ /* bt1120_d3 */
|
|
|
++ <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
|
|
|
++ /* bt1120_d4 */
|
|
|
++ <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
|
|
|
++ /* bt1120_d5 */
|
|
|
++ <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
|
|
|
++ /* bt1120_d6 */
|
|
|
++ <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
|
|
|
++ /* bt1120_d7 */
|
|
|
++ <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ gpio-func {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ tsadc_gpio_func: tsadc-gpio-func {
|
|
|
++ rockchip,pins =
|
|
|
++ <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++};
|
|
|
+--- /dev/null
|
|
|
++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra-pinctrl.dtsi
|
|
|
+@@ -0,0 +1,516 @@
|
|
|
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
|
++/*
|
|
|
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
|
|
++ */
|
|
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++
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++#include <dt-bindings/pinctrl/rockchip.h>
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++#include "rockchip-pinconf.dtsi"
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++
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++/*
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++ * This file is auto generated by pin2dts tool, please keep these code
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++ * by adding changes at end of this file.
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++ */
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++&pinctrl {
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++ clk32k {
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++ /omit-if-no-ref/
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++ clk32k_out1: clk32k-out1 {
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++ rockchip,pins =
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++ /* clk32k_out1 */
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++ <2 RK_PC5 1 &pcfg_pull_none>;
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++ };
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++
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++ };
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++
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++ eth0 {
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++ /omit-if-no-ref/
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++ eth0_pins: eth0-pins {
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++ rockchip,pins =
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++ /* eth0_refclko_25m */
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++ <2 RK_PC3 1 &pcfg_pull_none>;
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++ };
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++
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++ };
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++
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++ fspi {
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++ /omit-if-no-ref/
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++ fspim1_pins: fspim1-pins {
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++ rockchip,pins =
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++ /* fspi_clk_m1 */
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++ <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
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++ /* fspi_cs0n_m1 */
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++ <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
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++ /* fspi_d0_m1 */
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++ <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
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++ /* fspi_d1_m1 */
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++ <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
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++ /* fspi_d2_m1 */
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++ <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
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++ /* fspi_d3_m1 */
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++ <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
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++ };
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++
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++ /omit-if-no-ref/
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++ fspim1_cs1: fspim1-cs1 {
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++ rockchip,pins =
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++ /* fspi_cs1n_m1 */
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++ <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
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++ };
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++ };
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++
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++ gmac0 {
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++ /omit-if-no-ref/
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++ gmac0_miim: gmac0-miim {
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++ rockchip,pins =
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++ /* gmac0_mdc */
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++ <4 RK_PC4 1 &pcfg_pull_none>,
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++ /* gmac0_mdio */
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++ <4 RK_PC5 1 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ gmac0_clkinout: gmac0-clkinout {
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++ rockchip,pins =
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++ /* gmac0_mclkinout */
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++ <4 RK_PC3 1 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ gmac0_rx_bus2: gmac0-rx-bus2 {
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++ rockchip,pins =
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++ /* gmac0_rxd0 */
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++ <2 RK_PC1 1 &pcfg_pull_none>,
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++ /* gmac0_rxd1 */
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++ <2 RK_PC2 1 &pcfg_pull_none>,
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++ /* gmac0_rxdv_crs */
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++ <4 RK_PC2 1 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ gmac0_tx_bus2: gmac0-tx-bus2 {
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++ rockchip,pins =
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++ /* gmac0_txd0 */
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++ <2 RK_PB6 1 &pcfg_pull_none>,
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++ /* gmac0_txd1 */
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++ <2 RK_PB7 1 &pcfg_pull_none>,
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++ /* gmac0_txen */
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++ <2 RK_PC0 1 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ gmac0_rgmii_clk: gmac0-rgmii-clk {
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++ rockchip,pins =
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++ /* gmac0_rxclk */
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++ <2 RK_PB0 1 &pcfg_pull_none>,
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++ /* gmac0_txclk */
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++ <2 RK_PB3 1 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ gmac0_rgmii_bus: gmac0-rgmii-bus {
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++ rockchip,pins =
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++ /* gmac0_rxd2 */
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++ <2 RK_PA6 1 &pcfg_pull_none>,
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++ /* gmac0_rxd3 */
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++ <2 RK_PA7 1 &pcfg_pull_none>,
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++ /* gmac0_txd2 */
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++ <2 RK_PB1 1 &pcfg_pull_none>,
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++ /* gmac0_txd3 */
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++ <2 RK_PB2 1 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ gmac0_ppsclk: gmac0-ppsclk {
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++ rockchip,pins =
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++ /* gmac0_ppsclk */
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++ <2 RK_PC4 1 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ gmac0_ppstring: gmac0-ppstring {
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++ rockchip,pins =
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++ /* gmac0_ppstring */
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++ <2 RK_PB5 1 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ gmac0_ptp_refclk: gmac0-ptp-refclk {
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++ rockchip,pins =
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++ /* gmac0_ptp_refclk */
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++ <2 RK_PB4 1 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ gmac0_txer: gmac0-txer {
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++ rockchip,pins =
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++ /* gmac0_txer */
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++ <4 RK_PC6 1 &pcfg_pull_none>;
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++ };
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++
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++ };
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++
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++ hdmi {
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++ /omit-if-no-ref/
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++ hdmim0_tx1_cec: hdmim0-tx1-cec {
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++ rockchip,pins =
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++ /* hdmim0_tx1_cec */
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++ <2 RK_PC4 4 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ hdmim0_tx1_scl: hdmim0-tx1-scl {
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++ rockchip,pins =
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++ /* hdmim0_tx1_scl */
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++ <2 RK_PB5 4 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ hdmim0_tx1_sda: hdmim0-tx1-sda {
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++ rockchip,pins =
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++ /* hdmim0_tx1_sda */
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++ <2 RK_PB4 4 &pcfg_pull_none>;
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++ };
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++ };
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++
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++ i2c0 {
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++ /omit-if-no-ref/
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++ i2c0m1_xfer: i2c0m1-xfer {
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++ rockchip,pins =
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++ /* i2c0_scl_m1 */
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++ <4 RK_PC5 9 &pcfg_pull_none_smt>,
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++ /* i2c0_sda_m1 */
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++ <4 RK_PC6 9 &pcfg_pull_none_smt>;
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++ };
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++ };
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++
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++ i2c2 {
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++ /omit-if-no-ref/
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++ i2c2m1_xfer: i2c2m1-xfer {
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++ rockchip,pins =
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++ /* i2c2_scl_m1 */
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++ <2 RK_PC1 9 &pcfg_pull_none_smt>,
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++ /* i2c2_sda_m1 */
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++ <2 RK_PC0 9 &pcfg_pull_none_smt>;
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++ };
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++ };
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++
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++ i2c3 {
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++ /omit-if-no-ref/
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++ i2c3m3_xfer: i2c3m3-xfer {
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++ rockchip,pins =
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++ /* i2c3_scl_m3 */
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++ <2 RK_PB2 9 &pcfg_pull_none_smt>,
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++ /* i2c3_sda_m3 */
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++ <2 RK_PB3 9 &pcfg_pull_none_smt>;
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++ };
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++ };
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++
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++ i2c4 {
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++ /omit-if-no-ref/
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++ i2c4m1_xfer: i2c4m1-xfer {
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++ rockchip,pins =
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++ /* i2c4_scl_m1 */
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++ <2 RK_PB5 9 &pcfg_pull_none_smt>,
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++ /* i2c4_sda_m1 */
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++ <2 RK_PB4 9 &pcfg_pull_none_smt>;
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++ };
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++ };
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++
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++ i2c5 {
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++ /omit-if-no-ref/
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++ i2c5m4_xfer: i2c5m4-xfer {
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++ rockchip,pins =
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++ /* i2c5_scl_m4 */
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++ <2 RK_PB6 9 &pcfg_pull_none_smt>,
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++ /* i2c5_sda_m4 */
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++ <2 RK_PB7 9 &pcfg_pull_none_smt>;
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++ };
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++ };
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++
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++ i2c6 {
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++ /omit-if-no-ref/
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++ i2c6m2_xfer: i2c6m2-xfer {
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++ rockchip,pins =
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++ /* i2c6_scl_m2 */
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++ <2 RK_PC3 9 &pcfg_pull_none_smt>,
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++ /* i2c6_sda_m2 */
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++ <2 RK_PC2 9 &pcfg_pull_none_smt>;
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++ };
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++ };
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++
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++ i2c7 {
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++ /omit-if-no-ref/
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++ i2c7m1_xfer: i2c7m1-xfer {
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++ rockchip,pins =
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++ /* i2c7_scl_m1 */
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++ <4 RK_PC3 9 &pcfg_pull_none_smt>,
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++ /* i2c7_sda_m1 */
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++ <4 RK_PC4 9 &pcfg_pull_none_smt>;
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++ };
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++ };
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++
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++ i2c8 {
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++ /omit-if-no-ref/
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++ i2c8m1_xfer: i2c8m1-xfer {
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++ rockchip,pins =
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++ /* i2c8_scl_m1 */
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++ <2 RK_PB0 9 &pcfg_pull_none_smt>,
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++ /* i2c8_sda_m1 */
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++ <2 RK_PB1 9 &pcfg_pull_none_smt>;
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++ };
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++ };
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++
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++ i2s2 {
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++ /omit-if-no-ref/
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++ i2s2m0_lrck: i2s2m0-lrck {
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++ rockchip,pins =
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++ /* i2s2m0_lrck */
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++ <2 RK_PC0 2 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ i2s2m0_mclk: i2s2m0-mclk {
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++ rockchip,pins =
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++ /* i2s2m0_mclk */
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++ <2 RK_PB6 2 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ i2s2m0_sclk: i2s2m0-sclk {
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++ rockchip,pins =
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++ /* i2s2m0_sclk */
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++ <2 RK_PB7 2 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ i2s2m0_sdi: i2s2m0-sdi {
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++ rockchip,pins =
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++ /* i2s2m0_sdi */
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++ <2 RK_PC3 2 &pcfg_pull_none>;
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++ };
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++
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++ /omit-if-no-ref/
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++ i2s2m0_sdo: i2s2m0-sdo {
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++ rockchip,pins =
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++ /* i2s2m0_sdo */
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++ <4 RK_PC3 2 &pcfg_pull_none>;
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++ };
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++ };
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++
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++ pwm2 {
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++ /omit-if-no-ref/
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++ pwm2m2_pins: pwm2m2-pins {
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++ rockchip,pins =
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++ /* pwm2_m2 */
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++ <4 RK_PC2 11 &pcfg_pull_none>;
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++ };
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++ };
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++
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++ pwm4 {
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++ /omit-if-no-ref/
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++ pwm4m1_pins: pwm4m1-pins {
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++ rockchip,pins =
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++ /* pwm4_m1 */
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++ <4 RK_PC3 11 &pcfg_pull_none>;
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++ };
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++ };
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++
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++ pwm5 {
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++ /omit-if-no-ref/
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++ pwm5m2_pins: pwm5m2-pins {
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|
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++ rockchip,pins =
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|
++ /* pwm5_m2 */
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|
|
++ <4 RK_PC4 11 &pcfg_pull_none>;
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|
++ };
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++ };
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++
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|
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++ pwm6 {
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|
|
++ /omit-if-no-ref/
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|
|
++ pwm6m2_pins: pwm6m2-pins {
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|
|
++ rockchip,pins =
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|
|
++ /* pwm6_m2 */
|
|
|
++ <4 RK_PC5 11 &pcfg_pull_none>;
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|
|
++ };
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|
++ };
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|
++
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|
|
++ pwm7 {
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|
|
++ /omit-if-no-ref/
|
|
|
++ pwm7m3_pins: pwm7m3-pins {
|
|
|
++ rockchip,pins =
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|
|
++ /* pwm7_ir_m3 */
|
|
|
++ <4 RK_PC6 11 &pcfg_pull_none>;
|
|
|
++ };
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|
|
++ };
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|
|
++
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|
|
++ sdio {
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|
|
++ /omit-if-no-ref/
|
|
|
++ sdiom0_pins: sdiom0-pins {
|
|
|
++ rockchip,pins =
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|
|
++ /* sdio_clk_m0 */
|
|
|
++ <2 RK_PB3 2 &pcfg_pull_none>,
|
|
|
++ /* sdio_cmd_m0 */
|
|
|
++ <2 RK_PB2 2 &pcfg_pull_none>,
|
|
|
++ /* sdio_d0_m0 */
|
|
|
++ <2 RK_PA6 2 &pcfg_pull_none>,
|
|
|
++ /* sdio_d1_m0 */
|
|
|
++ <2 RK_PA7 2 &pcfg_pull_none>,
|
|
|
++ /* sdio_d2_m0 */
|
|
|
++ <2 RK_PB0 2 &pcfg_pull_none>,
|
|
|
++ /* sdio_d3_m0 */
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|
|
++ <2 RK_PB1 2 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ spi1 {
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|
|
++ /omit-if-no-ref/
|
|
|
++ spi1m0_pins: spi1m0-pins {
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|
|
++ rockchip,pins =
|
|
|
++ /* spi1_clk_m0 */
|
|
|
++ <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi1_miso_m0 */
|
|
|
++ <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi1_mosi_m0 */
|
|
|
++ <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi1m0_cs0: spi1m0-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi1_cs0_m0 */
|
|
|
++ <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi1m0_cs1: spi1m0-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi1_cs1_m0 */
|
|
|
++ <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ spi3 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m0_pins: spi3m0-pins {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_clk_m0 */
|
|
|
++ <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi3_miso_m0 */
|
|
|
++ <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
|
|
|
++ /* spi3_mosi_m0 */
|
|
|
++ <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m0_cs0: spi3m0-cs0 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_cs0_m0 */
|
|
|
++ <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ spi3m0_cs1: spi3m0-cs1 {
|
|
|
++ rockchip,pins =
|
|
|
++ /* spi3_cs1_m0 */
|
|
|
++ <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart1 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart1m0_xfer: uart1m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart1_rx_m0 */
|
|
|
++ <2 RK_PB6 10 &pcfg_pull_up>,
|
|
|
++ /* uart1_tx_m0 */
|
|
|
++ <2 RK_PB7 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart1m0_ctsn: uart1m0-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart1m0_ctsn */
|
|
|
++ <2 RK_PC1 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart1m0_rtsn: uart1m0-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart1m0_rtsn */
|
|
|
++ <2 RK_PC0 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart6 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart6m0_xfer: uart6m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart6_rx_m0 */
|
|
|
++ <2 RK_PA6 10 &pcfg_pull_up>,
|
|
|
++ /* uart6_tx_m0 */
|
|
|
++ <2 RK_PA7 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart6m0_ctsn: uart6m0-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart6m0_ctsn */
|
|
|
++ <2 RK_PB1 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart6m0_rtsn: uart6m0-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart6m0_rtsn */
|
|
|
++ <2 RK_PB0 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart7 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart7m0_xfer: uart7m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart7_rx_m0 */
|
|
|
++ <2 RK_PB4 10 &pcfg_pull_up>,
|
|
|
++ /* uart7_tx_m0 */
|
|
|
++ <2 RK_PB5 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart7m0_ctsn: uart7m0-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart7m0_ctsn */
|
|
|
++ <4 RK_PC6 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart7m0_rtsn: uart7m0-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart7m0_rtsn */
|
|
|
++ <4 RK_PC2 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++
|
|
|
++ uart9 {
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart9m0_xfer: uart9m0-xfer {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart9_rx_m0 */
|
|
|
++ <2 RK_PC4 10 &pcfg_pull_up>,
|
|
|
++ /* uart9_tx_m0 */
|
|
|
++ <2 RK_PC2 10 &pcfg_pull_up>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart9m0_ctsn: uart9m0-ctsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart9m0_ctsn */
|
|
|
++ <4 RK_PC5 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++
|
|
|
++ /omit-if-no-ref/
|
|
|
++ uart9m0_rtsn: uart9m0-rtsn {
|
|
|
++ rockchip,pins =
|
|
|
++ /* uart9m0_rtsn */
|
|
|
++ <4 RK_PC4 10 &pcfg_pull_none>;
|
|
|
++ };
|
|
|
++ };
|
|
|
++};
|
|
|
+--- a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi
|
|
|
++++ /dev/null
|
|
|
+@@ -1,516 +0,0 @@
|
|
|
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
|
+-/*
|
|
|
+- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
|
|
+- */
|
|
|
+-
|
|
|
+-#include <dt-bindings/pinctrl/rockchip.h>
|
|
|
+-#include "rockchip-pinconf.dtsi"
|
|
|
+-
|
|
|
+-/*
|
|
|
+- * This file is auto generated by pin2dts tool, please keep these code
|
|
|
+- * by adding changes at end of this file.
|
|
|
+- */
|
|
|
+-&pinctrl {
|
|
|
+- clk32k {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- clk32k_out1: clk32k-out1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* clk32k_out1 */
|
|
|
+- <2 RK_PC5 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- };
|
|
|
+-
|
|
|
+- eth0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- eth0_pins: eth0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* eth0_refclko_25m */
|
|
|
+- <2 RK_PC3 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- };
|
|
|
+-
|
|
|
+- fspi {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- fspim1_pins: fspim1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* fspi_clk_m1 */
|
|
|
+- <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_cs0n_m1 */
|
|
|
+- <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d0_m1 */
|
|
|
+- <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d1_m1 */
|
|
|
+- <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d2_m1 */
|
|
|
+- <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d3_m1 */
|
|
|
+- <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- fspim1_cs1: fspim1-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* fspi_cs1n_m1 */
|
|
|
+- <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- gmac0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac0_miim: gmac0-miim {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac0_mdc */
|
|
|
+- <4 RK_PC4 1 &pcfg_pull_none>,
|
|
|
+- /* gmac0_mdio */
|
|
|
+- <4 RK_PC5 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac0_clkinout: gmac0-clkinout {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac0_mclkinout */
|
|
|
+- <4 RK_PC3 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac0_rx_bus2: gmac0-rx-bus2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac0_rxd0 */
|
|
|
+- <2 RK_PC1 1 &pcfg_pull_none>,
|
|
|
+- /* gmac0_rxd1 */
|
|
|
+- <2 RK_PC2 1 &pcfg_pull_none>,
|
|
|
+- /* gmac0_rxdv_crs */
|
|
|
+- <4 RK_PC2 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac0_tx_bus2: gmac0-tx-bus2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac0_txd0 */
|
|
|
+- <2 RK_PB6 1 &pcfg_pull_none>,
|
|
|
+- /* gmac0_txd1 */
|
|
|
+- <2 RK_PB7 1 &pcfg_pull_none>,
|
|
|
+- /* gmac0_txen */
|
|
|
+- <2 RK_PC0 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac0_rgmii_clk: gmac0-rgmii-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac0_rxclk */
|
|
|
+- <2 RK_PB0 1 &pcfg_pull_none>,
|
|
|
+- /* gmac0_txclk */
|
|
|
+- <2 RK_PB3 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac0_rgmii_bus: gmac0-rgmii-bus {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac0_rxd2 */
|
|
|
+- <2 RK_PA6 1 &pcfg_pull_none>,
|
|
|
+- /* gmac0_rxd3 */
|
|
|
+- <2 RK_PA7 1 &pcfg_pull_none>,
|
|
|
+- /* gmac0_txd2 */
|
|
|
+- <2 RK_PB1 1 &pcfg_pull_none>,
|
|
|
+- /* gmac0_txd3 */
|
|
|
+- <2 RK_PB2 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac0_ppsclk: gmac0-ppsclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac0_ppsclk */
|
|
|
+- <2 RK_PC4 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac0_ppstring: gmac0-ppstring {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac0_ppstring */
|
|
|
+- <2 RK_PB5 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac0_ptp_refclk: gmac0-ptp-refclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac0_ptp_refclk */
|
|
|
+- <2 RK_PB4 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac0_txer: gmac0-txer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac0_txer */
|
|
|
+- <4 RK_PC6 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- };
|
|
|
+-
|
|
|
+- hdmi {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_tx1_cec: hdmim0-tx1-cec {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_tx1_cec */
|
|
|
+- <2 RK_PC4 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_tx1_scl: hdmim0-tx1-scl {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_tx1_scl */
|
|
|
+- <2 RK_PB5 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_tx1_sda: hdmim0-tx1-sda {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_tx1_sda */
|
|
|
+- <2 RK_PB4 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c0m1_xfer: i2c0m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c0_scl_m1 */
|
|
|
+- <4 RK_PC5 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c0_sda_m1 */
|
|
|
+- <4 RK_PC6 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c2m1_xfer: i2c2m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c2_scl_m1 */
|
|
|
+- <2 RK_PC1 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c2_sda_m1 */
|
|
|
+- <2 RK_PC0 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c3 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c3m3_xfer: i2c3m3-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c3_scl_m3 */
|
|
|
+- <2 RK_PB2 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c3_sda_m3 */
|
|
|
+- <2 RK_PB3 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c4 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c4m1_xfer: i2c4m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c4_scl_m1 */
|
|
|
+- <2 RK_PB5 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c4_sda_m1 */
|
|
|
+- <2 RK_PB4 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c5 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c5m4_xfer: i2c5m4-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c5_scl_m4 */
|
|
|
+- <2 RK_PB6 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c5_sda_m4 */
|
|
|
+- <2 RK_PB7 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c6 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c6m2_xfer: i2c6m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c6_scl_m2 */
|
|
|
+- <2 RK_PC3 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c6_sda_m2 */
|
|
|
+- <2 RK_PC2 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c7 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c7m1_xfer: i2c7m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c7_scl_m1 */
|
|
|
+- <4 RK_PC3 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c7_sda_m1 */
|
|
|
+- <4 RK_PC4 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c8 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c8m1_xfer: i2c8m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c8_scl_m1 */
|
|
|
+- <2 RK_PB0 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c8_sda_m1 */
|
|
|
+- <2 RK_PB1 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m0_lrck: i2s2m0-lrck {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m0_lrck */
|
|
|
+- <2 RK_PC0 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m0_mclk: i2s2m0-mclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m0_mclk */
|
|
|
+- <2 RK_PB6 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m0_sclk: i2s2m0-sclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m0_sclk */
|
|
|
+- <2 RK_PB7 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m0_sdi: i2s2m0-sdi {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m0_sdi */
|
|
|
+- <2 RK_PC3 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m0_sdo: i2s2m0-sdo {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m0_sdo */
|
|
|
+- <4 RK_PC3 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm2m2_pins: pwm2m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm2_m2 */
|
|
|
+- <4 RK_PC2 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm4 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm4m1_pins: pwm4m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm4_m1 */
|
|
|
+- <4 RK_PC3 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm5 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm5m2_pins: pwm5m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm5_m2 */
|
|
|
+- <4 RK_PC4 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm6 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm6m2_pins: pwm6m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm6_m2 */
|
|
|
+- <4 RK_PC5 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm7 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm7m3_pins: pwm7m3-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm7_ir_m3 */
|
|
|
+- <4 RK_PC6 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sdio {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sdiom0_pins: sdiom0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sdio_clk_m0 */
|
|
|
+- <2 RK_PB3 2 &pcfg_pull_none>,
|
|
|
+- /* sdio_cmd_m0 */
|
|
|
+- <2 RK_PB2 2 &pcfg_pull_none>,
|
|
|
+- /* sdio_d0_m0 */
|
|
|
+- <2 RK_PA6 2 &pcfg_pull_none>,
|
|
|
+- /* sdio_d1_m0 */
|
|
|
+- <2 RK_PA7 2 &pcfg_pull_none>,
|
|
|
+- /* sdio_d2_m0 */
|
|
|
+- <2 RK_PB0 2 &pcfg_pull_none>,
|
|
|
+- /* sdio_d3_m0 */
|
|
|
+- <2 RK_PB1 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi1m0_pins: spi1m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi1_clk_m0 */
|
|
|
+- <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi1_miso_m0 */
|
|
|
+- <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi1_mosi_m0 */
|
|
|
+- <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi1m0_cs0: spi1m0-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi1_cs0_m0 */
|
|
|
+- <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi1m0_cs1: spi1m0-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi1_cs1_m0 */
|
|
|
+- <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi3 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m0_pins: spi3m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_clk_m0 */
|
|
|
+- <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi3_miso_m0 */
|
|
|
+- <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi3_mosi_m0 */
|
|
|
+- <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m0_cs0: spi3m0-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_cs0_m0 */
|
|
|
+- <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m0_cs1: spi3m0-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_cs1_m0 */
|
|
|
+- <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart1m0_xfer: uart1m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart1_rx_m0 */
|
|
|
+- <2 RK_PB6 10 &pcfg_pull_up>,
|
|
|
+- /* uart1_tx_m0 */
|
|
|
+- <2 RK_PB7 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart1m0_ctsn: uart1m0-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart1m0_ctsn */
|
|
|
+- <2 RK_PC1 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart1m0_rtsn: uart1m0-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart1m0_rtsn */
|
|
|
+- <2 RK_PC0 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart6 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart6m0_xfer: uart6m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart6_rx_m0 */
|
|
|
+- <2 RK_PA6 10 &pcfg_pull_up>,
|
|
|
+- /* uart6_tx_m0 */
|
|
|
+- <2 RK_PA7 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart6m0_ctsn: uart6m0-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart6m0_ctsn */
|
|
|
+- <2 RK_PB1 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart6m0_rtsn: uart6m0-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart6m0_rtsn */
|
|
|
+- <2 RK_PB0 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart7 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart7m0_xfer: uart7m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart7_rx_m0 */
|
|
|
+- <2 RK_PB4 10 &pcfg_pull_up>,
|
|
|
+- /* uart7_tx_m0 */
|
|
|
+- <2 RK_PB5 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart7m0_ctsn: uart7m0-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart7m0_ctsn */
|
|
|
+- <4 RK_PC6 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart7m0_rtsn: uart7m0-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart7m0_rtsn */
|
|
|
+- <4 RK_PC2 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart9 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart9m0_xfer: uart9m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart9_rx_m0 */
|
|
|
+- <2 RK_PC4 10 &pcfg_pull_up>,
|
|
|
+- /* uart9_tx_m0 */
|
|
|
+- <2 RK_PC2 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart9m0_ctsn: uart9m0-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart9m0_ctsn */
|
|
|
+- <4 RK_PC5 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart9m0_rtsn: uart9m0-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart9m0_rtsn */
|
|
|
+- <4 RK_PC4 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-};
|
|
|
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
|
|
|
++++ /dev/null
|
|
|
+@@ -1,3447 +0,0 @@
|
|
|
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
|
+-/*
|
|
|
+- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
|
|
+- */
|
|
|
+-
|
|
|
+-#include <dt-bindings/pinctrl/rockchip.h>
|
|
|
+-#include "rockchip-pinconf.dtsi"
|
|
|
+-
|
|
|
+-/*
|
|
|
+- * This file is auto generated by pin2dts tool, please keep these code
|
|
|
+- * by adding changes at end of this file.
|
|
|
+- */
|
|
|
+-&pinctrl {
|
|
|
+- auddsm {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- auddsm_pins: auddsm-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* auddsm_ln */
|
|
|
+- <3 RK_PA1 4 &pcfg_pull_none>,
|
|
|
+- /* auddsm_lp */
|
|
|
+- <3 RK_PA2 4 &pcfg_pull_none>,
|
|
|
+- /* auddsm_rn */
|
|
|
+- <3 RK_PA3 4 &pcfg_pull_none>,
|
|
|
+- /* auddsm_rp */
|
|
|
+- <3 RK_PA4 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- bt1120 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- bt1120_pins: bt1120-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* bt1120_clkout */
|
|
|
+- <4 RK_PB0 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d0 */
|
|
|
+- <4 RK_PA0 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d1 */
|
|
|
+- <4 RK_PA1 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d2 */
|
|
|
+- <4 RK_PA2 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d3 */
|
|
|
+- <4 RK_PA3 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d4 */
|
|
|
+- <4 RK_PA4 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d5 */
|
|
|
+- <4 RK_PA5 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d6 */
|
|
|
+- <4 RK_PA6 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d7 */
|
|
|
+- <4 RK_PA7 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d8 */
|
|
|
+- <4 RK_PB2 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d9 */
|
|
|
+- <4 RK_PB3 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d10 */
|
|
|
+- <4 RK_PB4 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d11 */
|
|
|
+- <4 RK_PB5 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d12 */
|
|
|
+- <4 RK_PB6 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d13 */
|
|
|
+- <4 RK_PB7 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d14 */
|
|
|
+- <4 RK_PC0 2 &pcfg_pull_none>,
|
|
|
+- /* bt1120_d15 */
|
|
|
+- <4 RK_PC1 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- can0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- can0m0_pins: can0m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* can0_rx_m0 */
|
|
|
+- <0 RK_PC0 11 &pcfg_pull_none>,
|
|
|
+- /* can0_tx_m0 */
|
|
|
+- <0 RK_PB7 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- can0m1_pins: can0m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* can0_rx_m1 */
|
|
|
+- <4 RK_PD5 9 &pcfg_pull_none>,
|
|
|
+- /* can0_tx_m1 */
|
|
|
+- <4 RK_PD4 9 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- can1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- can1m0_pins: can1m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* can1_rx_m0 */
|
|
|
+- <3 RK_PB5 9 &pcfg_pull_none>,
|
|
|
+- /* can1_tx_m0 */
|
|
|
+- <3 RK_PB6 9 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- can1m1_pins: can1m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* can1_rx_m1 */
|
|
|
+- <4 RK_PB2 12 &pcfg_pull_none>,
|
|
|
+- /* can1_tx_m1 */
|
|
|
+- <4 RK_PB3 12 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- can2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- can2m0_pins: can2m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* can2_rx_m0 */
|
|
|
+- <3 RK_PC4 9 &pcfg_pull_none>,
|
|
|
+- /* can2_tx_m0 */
|
|
|
+- <3 RK_PC5 9 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- can2m1_pins: can2m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* can2_rx_m1 */
|
|
|
+- <0 RK_PD4 10 &pcfg_pull_none>,
|
|
|
+- /* can2_tx_m1 */
|
|
|
+- <0 RK_PD5 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- cif {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- cif_clk: cif-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* cif_clkout */
|
|
|
+- <4 RK_PB4 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- cif_dvp_clk: cif-dvp-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* cif_clkin */
|
|
|
+- <4 RK_PB0 1 &pcfg_pull_none>,
|
|
|
+- /* cif_href */
|
|
|
+- <4 RK_PB2 1 &pcfg_pull_none>,
|
|
|
+- /* cif_vsync */
|
|
|
+- <4 RK_PB3 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- cif_dvp_bus16: cif-dvp-bus16 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* cif_d8 */
|
|
|
+- <3 RK_PC4 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d9 */
|
|
|
+- <3 RK_PC5 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d10 */
|
|
|
+- <3 RK_PC6 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d11 */
|
|
|
+- <3 RK_PC7 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d12 */
|
|
|
+- <3 RK_PD0 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d13 */
|
|
|
+- <3 RK_PD1 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d14 */
|
|
|
+- <3 RK_PD2 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d15 */
|
|
|
+- <3 RK_PD3 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- cif_dvp_bus8: cif-dvp-bus8 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* cif_d0 */
|
|
|
+- <4 RK_PA0 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d1 */
|
|
|
+- <4 RK_PA1 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d2 */
|
|
|
+- <4 RK_PA2 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d3 */
|
|
|
+- <4 RK_PA3 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d4 */
|
|
|
+- <4 RK_PA4 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d5 */
|
|
|
+- <4 RK_PA5 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d6 */
|
|
|
+- <4 RK_PA6 1 &pcfg_pull_none>,
|
|
|
+- /* cif_d7 */
|
|
|
+- <4 RK_PA7 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- clk32k {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- clk32k_in: clk32k-in {
|
|
|
+- rockchip,pins =
|
|
|
+- /* clk32k_in */
|
|
|
+- <0 RK_PB2 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- clk32k_out0: clk32k-out0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* clk32k_out0 */
|
|
|
+- <0 RK_PB2 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- cpu {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- cpu_pins: cpu-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* cpu_big0_avs */
|
|
|
+- <0 RK_PD1 2 &pcfg_pull_none>,
|
|
|
+- /* cpu_big1_avs */
|
|
|
+- <0 RK_PD5 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- ddrphych0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- ddrphych0_pins: ddrphych0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* ddrphych0_dtb0 */
|
|
|
+- <4 RK_PA0 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych0_dtb1 */
|
|
|
+- <4 RK_PA1 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych0_dtb2 */
|
|
|
+- <4 RK_PA2 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych0_dtb3 */
|
|
|
+- <4 RK_PA3 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- ddrphych1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- ddrphych1_pins: ddrphych1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* ddrphych1_dtb0 */
|
|
|
+- <4 RK_PA4 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych1_dtb1 */
|
|
|
+- <4 RK_PA5 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych1_dtb2 */
|
|
|
+- <4 RK_PA6 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych1_dtb3 */
|
|
|
+- <4 RK_PA7 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- ddrphych2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- ddrphych2_pins: ddrphych2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* ddrphych2_dtb0 */
|
|
|
+- <4 RK_PB0 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych2_dtb1 */
|
|
|
+- <4 RK_PB1 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych2_dtb2 */
|
|
|
+- <4 RK_PB2 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych2_dtb3 */
|
|
|
+- <4 RK_PB3 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- ddrphych3 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- ddrphych3_pins: ddrphych3-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* ddrphych3_dtb0 */
|
|
|
+- <4 RK_PB4 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych3_dtb1 */
|
|
|
+- <4 RK_PB5 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych3_dtb2 */
|
|
|
+- <4 RK_PB6 7 &pcfg_pull_none>,
|
|
|
+- /* ddrphych3_dtb3 */
|
|
|
+- <4 RK_PB7 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- dp0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- dp0m0_pins: dp0m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* dp0_hpdin_m0 */
|
|
|
+- <4 RK_PB4 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- dp0m1_pins: dp0m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* dp0_hpdin_m1 */
|
|
|
+- <0 RK_PC4 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- dp0m2_pins: dp0m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* dp0_hpdin_m2 */
|
|
|
+- <1 RK_PA0 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- dp1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- dp1m0_pins: dp1m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* dp1_hpdin_m0 */
|
|
|
+- <3 RK_PD5 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- dp1m1_pins: dp1m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* dp1_hpdin_m1 */
|
|
|
+- <0 RK_PC5 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- dp1m2_pins: dp1m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* dp1_hpdin_m2 */
|
|
|
+- <1 RK_PA1 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- emmc {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- emmc_rstnout: emmc-rstnout {
|
|
|
+- rockchip,pins =
|
|
|
+- /* emmc_rstn */
|
|
|
+- <2 RK_PA3 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- emmc_bus8: emmc-bus8 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* emmc_d0 */
|
|
|
+- <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* emmc_d1 */
|
|
|
+- <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* emmc_d2 */
|
|
|
+- <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* emmc_d3 */
|
|
|
+- <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* emmc_d4 */
|
|
|
+- <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* emmc_d5 */
|
|
|
+- <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* emmc_d6 */
|
|
|
+- <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* emmc_d7 */
|
|
|
+- <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- emmc_clk: emmc-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* emmc_clkout */
|
|
|
+- <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- emmc_cmd: emmc-cmd {
|
|
|
+- rockchip,pins =
|
|
|
+- /* emmc_cmd */
|
|
|
+- <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- emmc_data_strobe: emmc-data-strobe {
|
|
|
+- rockchip,pins =
|
|
|
+- /* emmc_data_strobe */
|
|
|
+- <2 RK_PA2 1 &pcfg_pull_down>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- eth1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- eth1_pins: eth1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* eth1_refclko_25m */
|
|
|
+- <3 RK_PA6 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- fspi {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- fspim0_pins: fspim0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* fspi_clk_m0 */
|
|
|
+- <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_cs0n_m0 */
|
|
|
+- <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d0_m0 */
|
|
|
+- <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d1_m0 */
|
|
|
+- <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d2_m0 */
|
|
|
+- <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d3_m0 */
|
|
|
+- <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- fspim0_cs1: fspim0-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* fspi_cs1n_m0 */
|
|
|
+- <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- fspim2_pins: fspim2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* fspi_clk_m2 */
|
|
|
+- <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_cs0n_m2 */
|
|
|
+- <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d0_m2 */
|
|
|
+- <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d1_m2 */
|
|
|
+- <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d2_m2 */
|
|
|
+- <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* fspi_d3_m2 */
|
|
|
+- <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- fspim2_cs1: fspim2-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* fspi_cs1n_m2 */
|
|
|
+- <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- gmac1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac1_miim: gmac1-miim {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac1_mdc */
|
|
|
+- <3 RK_PC2 1 &pcfg_pull_none>,
|
|
|
+- /* gmac1_mdio */
|
|
|
+- <3 RK_PC3 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac1_clkinout: gmac1-clkinout {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac1_mclkinout */
|
|
|
+- <3 RK_PB6 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac1_rx_bus2: gmac1-rx-bus2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac1_rxd0 */
|
|
|
+- <3 RK_PA7 1 &pcfg_pull_none>,
|
|
|
+- /* gmac1_rxd1 */
|
|
|
+- <3 RK_PB0 1 &pcfg_pull_none>,
|
|
|
+- /* gmac1_rxdv_crs */
|
|
|
+- <3 RK_PB1 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac1_tx_bus2: gmac1-tx-bus2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac1_txd0 */
|
|
|
+- <3 RK_PB3 1 &pcfg_pull_none>,
|
|
|
+- /* gmac1_txd1 */
|
|
|
+- <3 RK_PB4 1 &pcfg_pull_none>,
|
|
|
+- /* gmac1_txen */
|
|
|
+- <3 RK_PB5 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac1_rgmii_clk: gmac1-rgmii-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac1_rxclk */
|
|
|
+- <3 RK_PA5 1 &pcfg_pull_none>,
|
|
|
+- /* gmac1_txclk */
|
|
|
+- <3 RK_PA4 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac1_rgmii_bus: gmac1-rgmii-bus {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac1_rxd2 */
|
|
|
+- <3 RK_PA2 1 &pcfg_pull_none>,
|
|
|
+- /* gmac1_rxd3 */
|
|
|
+- <3 RK_PA3 1 &pcfg_pull_none>,
|
|
|
+- /* gmac1_txd2 */
|
|
|
+- <3 RK_PA0 1 &pcfg_pull_none>,
|
|
|
+- /* gmac1_txd3 */
|
|
|
+- <3 RK_PA1 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac1_ppsclk: gmac1-ppsclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac1_ppsclk */
|
|
|
+- <3 RK_PC1 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac1_ppstrig: gmac1-ppstrig {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac1_ppstrig */
|
|
|
+- <3 RK_PC0 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac1_ptp_ref_clk */
|
|
|
+- <3 RK_PB7 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gmac1_txer: gmac1-txer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gmac1_txer */
|
|
|
+- <3 RK_PB2 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- gpu {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- gpu_pins: gpu-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* gpu_avs */
|
|
|
+- <0 RK_PC5 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- hdmi {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_rx_cec: hdmim0-rx-cec {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_rx_cec */
|
|
|
+- <4 RK_PB5 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_rx_hpdin: hdmim0-rx-hpdin {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_rx_hpdin */
|
|
|
+- <4 RK_PB6 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_rx_scl: hdmim0-rx-scl {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_rx_scl */
|
|
|
+- <0 RK_PD2 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_rx_sda: hdmim0-rx-sda {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_rx_sda */
|
|
|
+- <0 RK_PD1 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_tx0_cec: hdmim0-tx0-cec {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_tx0_cec */
|
|
|
+- <4 RK_PC1 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_tx0_hpd: hdmim0-tx0-hpd {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_tx0_hpd */
|
|
|
+- <1 RK_PA5 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_tx0_scl: hdmim0-tx0-scl {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_tx0_scl */
|
|
|
+- <4 RK_PB7 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_tx0_sda: hdmim0-tx0-sda {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_tx0_sda */
|
|
|
+- <4 RK_PC0 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim0_tx1_hpd: hdmim0-tx1-hpd {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim0_tx1_hpd */
|
|
|
+- <1 RK_PA6 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_rx_cec: hdmim1-rx-cec {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_rx_cec */
|
|
|
+- <3 RK_PD1 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_rx_hpdin: hdmim1-rx-hpdin {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_rx_hpdin */
|
|
|
+- <3 RK_PD4 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_rx_scl: hdmim1-rx-scl {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_rx_scl */
|
|
|
+- <3 RK_PD2 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_rx_sda: hdmim1-rx-sda {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_rx_sda */
|
|
|
+- <3 RK_PD3 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_tx0_cec: hdmim1-tx0-cec {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_tx0_cec */
|
|
|
+- <0 RK_PD1 13 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_tx0_hpd: hdmim1-tx0-hpd {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_tx0_hpd */
|
|
|
+- <3 RK_PD4 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_tx0_scl: hdmim1-tx0-scl {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_tx0_scl */
|
|
|
+- <0 RK_PD5 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_tx0_sda: hdmim1-tx0-sda {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_tx0_sda */
|
|
|
+- <0 RK_PD4 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_tx1_cec: hdmim1-tx1-cec {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_tx1_cec */
|
|
|
+- <0 RK_PD2 13 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_tx1_hpd: hdmim1-tx1-hpd {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_tx1_hpd */
|
|
|
+- <3 RK_PB7 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_tx1_scl: hdmim1-tx1-scl {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_tx1_scl */
|
|
|
+- <3 RK_PC6 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim1_tx1_sda: hdmim1-tx1-sda {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim1_tx1_sda */
|
|
|
+- <3 RK_PC5 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim2_rx_cec: hdmim2-rx-cec {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim2_rx_cec */
|
|
|
+- <1 RK_PB7 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim2_rx_hpdin: hdmim2-rx-hpdin {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim2_rx_hpdin */
|
|
|
+- <1 RK_PB6 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim2_rx_scl: hdmim2-rx-scl {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim2_rx_scl */
|
|
|
+- <1 RK_PD6 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim2_rx_sda: hdmim2-rx-sda {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim2_rx_sda */
|
|
|
+- <1 RK_PD7 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim2_tx0_scl: hdmim2-tx0-scl {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim2_tx0_scl */
|
|
|
+- <3 RK_PC7 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim2_tx0_sda: hdmim2-tx0-sda {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim2_tx0_sda */
|
|
|
+- <3 RK_PD0 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim2_tx1_cec: hdmim2-tx1-cec {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim2_tx1_cec */
|
|
|
+- <3 RK_PC4 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim2_tx1_scl: hdmim2-tx1-scl {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim2_tx1_scl */
|
|
|
+- <1 RK_PA4 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmim2_tx1_sda: hdmim2-tx1-sda {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmim2_tx1_sda */
|
|
|
+- <1 RK_PA3 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmi_debug0: hdmi-debug0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmi_debug0 */
|
|
|
+- <1 RK_PA7 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmi_debug1: hdmi-debug1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmi_debug1 */
|
|
|
+- <1 RK_PB0 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmi_debug2: hdmi-debug2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmi_debug2 */
|
|
|
+- <1 RK_PB1 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmi_debug3: hdmi-debug3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmi_debug3 */
|
|
|
+- <1 RK_PB2 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmi_debug4: hdmi-debug4 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmi_debug4 */
|
|
|
+- <1 RK_PB3 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmi_debug5: hdmi-debug5 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmi_debug5 */
|
|
|
+- <1 RK_PB4 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- hdmi_debug6: hdmi-debug6 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* hdmi_debug6 */
|
|
|
+- <1 RK_PA0 7 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c0m0_xfer: i2c0m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c0_scl_m0 */
|
|
|
+- <0 RK_PB3 2 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c0_sda_m0 */
|
|
|
+- <0 RK_PA6 2 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c0m2_xfer: i2c0m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c0_scl_m2 */
|
|
|
+- <0 RK_PD1 3 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c0_sda_m2 */
|
|
|
+- <0 RK_PD2 3 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c1m0_xfer: i2c1m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c1_scl_m0 */
|
|
|
+- <0 RK_PB5 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c1_sda_m0 */
|
|
|
+- <0 RK_PB6 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c1m1_xfer: i2c1m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c1_scl_m1 */
|
|
|
+- <0 RK_PB0 2 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c1_sda_m1 */
|
|
|
+- <0 RK_PB1 2 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c1m2_xfer: i2c1m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c1_scl_m2 */
|
|
|
+- <0 RK_PD4 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c1_sda_m2 */
|
|
|
+- <0 RK_PD5 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c1m3_xfer: i2c1m3-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c1_scl_m3 */
|
|
|
+- <2 RK_PD4 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c1_sda_m3 */
|
|
|
+- <2 RK_PD5 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c1m4_xfer: i2c1m4-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c1_scl_m4 */
|
|
|
+- <1 RK_PD2 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c1_sda_m4 */
|
|
|
+- <1 RK_PD3 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c2m0_xfer: i2c2m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c2_scl_m0 */
|
|
|
+- <0 RK_PB7 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c2_sda_m0 */
|
|
|
+- <0 RK_PC0 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c2m2_xfer: i2c2m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c2_scl_m2 */
|
|
|
+- <2 RK_PA3 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c2_sda_m2 */
|
|
|
+- <2 RK_PA2 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c2m3_xfer: i2c2m3-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c2_scl_m3 */
|
|
|
+- <1 RK_PC5 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c2_sda_m3 */
|
|
|
+- <1 RK_PC4 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c2m4_xfer: i2c2m4-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c2_scl_m4 */
|
|
|
+- <1 RK_PA1 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c2_sda_m4 */
|
|
|
+- <1 RK_PA0 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c3 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c3m0_xfer: i2c3m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c3_scl_m0 */
|
|
|
+- <1 RK_PC1 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c3_sda_m0 */
|
|
|
+- <1 RK_PC0 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c3m1_xfer: i2c3m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c3_scl_m1 */
|
|
|
+- <3 RK_PB7 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c3_sda_m1 */
|
|
|
+- <3 RK_PC0 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c3m2_xfer: i2c3m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c3_scl_m2 */
|
|
|
+- <4 RK_PA4 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c3_sda_m2 */
|
|
|
+- <4 RK_PA5 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c3m4_xfer: i2c3m4-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c3_scl_m4 */
|
|
|
+- <4 RK_PD0 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c3_sda_m4 */
|
|
|
+- <4 RK_PD1 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c4 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c4m0_xfer: i2c4m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c4_scl_m0 */
|
|
|
+- <3 RK_PA6 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c4_sda_m0 */
|
|
|
+- <3 RK_PA5 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c4m2_xfer: i2c4m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c4_scl_m2 */
|
|
|
+- <0 RK_PC5 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c4_sda_m2 */
|
|
|
+- <0 RK_PC4 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c4m3_xfer: i2c4m3-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c4_scl_m3 */
|
|
|
+- <1 RK_PA3 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c4_sda_m3 */
|
|
|
+- <1 RK_PA2 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c4m4_xfer: i2c4m4-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c4_scl_m4 */
|
|
|
+- <1 RK_PC7 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c4_sda_m4 */
|
|
|
+- <1 RK_PC6 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c5 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c5m0_xfer: i2c5m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c5_scl_m0 */
|
|
|
+- <3 RK_PC7 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c5_sda_m0 */
|
|
|
+- <3 RK_PD0 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c5m1_xfer: i2c5m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c5_scl_m1 */
|
|
|
+- <4 RK_PB6 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c5_sda_m1 */
|
|
|
+- <4 RK_PB7 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c5m2_xfer: i2c5m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c5_scl_m2 */
|
|
|
+- <4 RK_PA6 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c5_sda_m2 */
|
|
|
+- <4 RK_PA7 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c5m3_xfer: i2c5m3-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c5_scl_m3 */
|
|
|
+- <1 RK_PB6 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c5_sda_m3 */
|
|
|
+- <1 RK_PB7 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c6 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c6m0_xfer: i2c6m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c6_scl_m0 */
|
|
|
+- <0 RK_PD0 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c6_sda_m0 */
|
|
|
+- <0 RK_PC7 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c6m1_xfer: i2c6m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c6_scl_m1 */
|
|
|
+- <1 RK_PC3 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c6_sda_m1 */
|
|
|
+- <1 RK_PC2 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c6m3_xfer: i2c6m3-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c6_scl_m3 */
|
|
|
+- <4 RK_PB1 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c6_sda_m3 */
|
|
|
+- <4 RK_PB0 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c6m4_xfer: i2c6m4-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c6_scl_m4 */
|
|
|
+- <3 RK_PA1 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c6_sda_m4 */
|
|
|
+- <3 RK_PA0 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c7 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c7m0_xfer: i2c7m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c7_scl_m0 */
|
|
|
+- <1 RK_PD0 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c7_sda_m0 */
|
|
|
+- <1 RK_PD1 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c7m2_xfer: i2c7m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c7_scl_m2 */
|
|
|
+- <3 RK_PD2 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c7_sda_m2 */
|
|
|
+- <3 RK_PD3 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c7m3_xfer: i2c7m3-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c7_scl_m3 */
|
|
|
+- <4 RK_PB2 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c7_sda_m3 */
|
|
|
+- <4 RK_PB3 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2c8 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c8m0_xfer: i2c8m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c8_scl_m0 */
|
|
|
+- <4 RK_PD2 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c8_sda_m0 */
|
|
|
+- <4 RK_PD3 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c8m2_xfer: i2c8m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c8_scl_m2 */
|
|
|
+- <1 RK_PD6 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c8_sda_m2 */
|
|
|
+- <1 RK_PD7 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c8m3_xfer: i2c8m3-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c8_scl_m3 */
|
|
|
+- <4 RK_PC0 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c8_sda_m3 */
|
|
|
+- <4 RK_PC1 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2c8m4_xfer: i2c8m4-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2c8_scl_m4 */
|
|
|
+- <3 RK_PC2 9 &pcfg_pull_none_smt>,
|
|
|
+- /* i2c8_sda_m4 */
|
|
|
+- <3 RK_PC3 9 &pcfg_pull_none_smt>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_lrck: i2s0-lrck {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_lrck */
|
|
|
+- <1 RK_PC5 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_mclk: i2s0-mclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_mclk */
|
|
|
+- <1 RK_PC2 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_sclk: i2s0-sclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_sclk */
|
|
|
+- <1 RK_PC3 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_sdi0: i2s0-sdi0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_sdi0 */
|
|
|
+- <1 RK_PD4 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_sdi1: i2s0-sdi1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_sdi1 */
|
|
|
+- <1 RK_PD3 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_sdi2: i2s0-sdi2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_sdi2 */
|
|
|
+- <1 RK_PD2 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_sdi3: i2s0-sdi3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_sdi3 */
|
|
|
+- <1 RK_PD1 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_sdo0: i2s0-sdo0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_sdo0 */
|
|
|
+- <1 RK_PC7 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_sdo1: i2s0-sdo1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_sdo1 */
|
|
|
+- <1 RK_PD0 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_sdo2: i2s0-sdo2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_sdo2 */
|
|
|
+- <1 RK_PD1 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s0_sdo3: i2s0-sdo3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s0_sdo3 */
|
|
|
+- <1 RK_PD2 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_lrck: i2s1m0-lrck {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_lrck */
|
|
|
+- <4 RK_PA2 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_mclk: i2s1m0-mclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_mclk */
|
|
|
+- <4 RK_PA0 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_sclk: i2s1m0-sclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_sclk */
|
|
|
+- <4 RK_PA1 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_sdi0: i2s1m0-sdi0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_sdi0 */
|
|
|
+- <4 RK_PA5 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_sdi1: i2s1m0-sdi1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_sdi1 */
|
|
|
+- <4 RK_PA6 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_sdi2: i2s1m0-sdi2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_sdi2 */
|
|
|
+- <4 RK_PA7 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_sdi3: i2s1m0-sdi3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_sdi3 */
|
|
|
+- <4 RK_PB0 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_sdo0: i2s1m0-sdo0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_sdo0 */
|
|
|
+- <4 RK_PB1 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_sdo1: i2s1m0-sdo1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_sdo1 */
|
|
|
+- <4 RK_PB2 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_sdo2: i2s1m0-sdo2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_sdo2 */
|
|
|
+- <4 RK_PB3 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m0_sdo3: i2s1m0-sdo3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m0_sdo3 */
|
|
|
+- <4 RK_PB4 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_lrck: i2s1m1-lrck {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_lrck */
|
|
|
+- <0 RK_PB7 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_mclk: i2s1m1-mclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_mclk */
|
|
|
+- <0 RK_PB5 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_sclk: i2s1m1-sclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_sclk */
|
|
|
+- <0 RK_PB6 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_sdi0: i2s1m1-sdi0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_sdi0 */
|
|
|
+- <0 RK_PC5 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_sdi1: i2s1m1-sdi1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_sdi1 */
|
|
|
+- <0 RK_PC6 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_sdi2: i2s1m1-sdi2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_sdi2 */
|
|
|
+- <0 RK_PC7 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_sdi3: i2s1m1-sdi3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_sdi3 */
|
|
|
+- <0 RK_PD0 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_sdo0: i2s1m1-sdo0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_sdo0 */
|
|
|
+- <0 RK_PD1 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_sdo1: i2s1m1-sdo1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_sdo1 */
|
|
|
+- <0 RK_PD2 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_sdo2: i2s1m1-sdo2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_sdo2 */
|
|
|
+- <0 RK_PD4 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s1m1_sdo3: i2s1m1-sdo3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s1m1_sdo3 */
|
|
|
+- <0 RK_PD5 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m0_lrck: i2s2m0-lrck {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m0_lrck */
|
|
|
+- <2 RK_PC0 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m0_mclk: i2s2m0-mclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m0_mclk */
|
|
|
+- <2 RK_PB6 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m0_sclk: i2s2m0-sclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m0_sclk */
|
|
|
+- <2 RK_PB7 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m0_sdi: i2s2m0-sdi {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m0_sdi */
|
|
|
+- <2 RK_PC3 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m0_sdo: i2s2m0-sdo {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m0_sdo */
|
|
|
+- <4 RK_PC3 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m1_lrck: i2s2m1-lrck {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m1_lrck */
|
|
|
+- <3 RK_PB6 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m1_mclk: i2s2m1-mclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m1_mclk */
|
|
|
+- <3 RK_PB4 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m1_sclk: i2s2m1-sclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m1_sclk */
|
|
|
+- <3 RK_PB5 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m1_sdi: i2s2m1-sdi {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m1_sdi */
|
|
|
+- <3 RK_PB2 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s2m1_sdo: i2s2m1-sdo {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s2m1_sdo */
|
|
|
+- <3 RK_PB3 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- i2s3 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s3_lrck: i2s3-lrck {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s3_lrck */
|
|
|
+- <3 RK_PA2 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s3_mclk: i2s3-mclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s3_mclk */
|
|
|
+- <3 RK_PA0 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s3_sclk: i2s3-sclk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s3_sclk */
|
|
|
+- <3 RK_PA1 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s3_sdi: i2s3-sdi {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s3_sdi */
|
|
|
+- <3 RK_PA4 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- i2s3_sdo: i2s3-sdo {
|
|
|
+- rockchip,pins =
|
|
|
+- /* i2s3_sdo */
|
|
|
+- <3 RK_PA3 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- jtag {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- jtagm0_pins: jtagm0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* jtag_tck_m0 */
|
|
|
+- <4 RK_PD2 5 &pcfg_pull_none>,
|
|
|
+- /* jtag_tms_m0 */
|
|
|
+- <4 RK_PD3 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- jtagm1_pins: jtagm1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* jtag_tck_m1 */
|
|
|
+- <4 RK_PD0 5 &pcfg_pull_none>,
|
|
|
+- /* jtag_tms_m1 */
|
|
|
+- <4 RK_PD1 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- jtagm2_pins: jtagm2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* jtag_tck_m2 */
|
|
|
+- <0 RK_PB5 2 &pcfg_pull_none>,
|
|
|
+- /* jtag_tms_m2 */
|
|
|
+- <0 RK_PB6 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- litcpu {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- litcpu_pins: litcpu-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* litcpu_avs */
|
|
|
+- <0 RK_PD3 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- mcu {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mcum0_pins: mcum0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mcu_jtag_tck_m0 */
|
|
|
+- <4 RK_PD4 5 &pcfg_pull_none>,
|
|
|
+- /* mcu_jtag_tms_m0 */
|
|
|
+- <4 RK_PD5 5 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mcum1_pins: mcum1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mcu_jtag_tck_m1 */
|
|
|
+- <3 RK_PD4 6 &pcfg_pull_none>,
|
|
|
+- /* mcu_jtag_tms_m1 */
|
|
|
+- <3 RK_PD5 6 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- mipi {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipim0_camera0_clk: mipim0-camera0-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipim0_camera0_clk */
|
|
|
+- <4 RK_PB1 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipim0_camera1_clk: mipim0-camera1-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipim0_camera1_clk */
|
|
|
+- <1 RK_PB6 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipim0_camera2_clk: mipim0-camera2-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipim0_camera2_clk */
|
|
|
+- <1 RK_PB7 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipim0_camera3_clk: mipim0-camera3-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipim0_camera3_clk */
|
|
|
+- <1 RK_PD6 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipim0_camera4_clk: mipim0-camera4-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipim0_camera4_clk */
|
|
|
+- <1 RK_PD7 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipim1_camera0_clk: mipim1-camera0-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipim1_camera0_clk */
|
|
|
+- <3 RK_PA5 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipim1_camera1_clk: mipim1-camera1-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipim1_camera1_clk */
|
|
|
+- <3 RK_PA6 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipim1_camera2_clk: mipim1-camera2-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipim1_camera2_clk */
|
|
|
+- <3 RK_PA7 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipim1_camera3_clk: mipim1-camera3-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipim1_camera3_clk */
|
|
|
+- <3 RK_PB0 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipim1_camera4_clk: mipim1-camera4-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipim1_camera4_clk */
|
|
|
+- <3 RK_PB1 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipi_te0: mipi-te0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipi_te0 */
|
|
|
+- <3 RK_PC2 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- mipi_te1: mipi-te1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* mipi_te1 */
|
|
|
+- <3 RK_PC3 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- npu {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- npu_pins: npu-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* npu_avs */
|
|
|
+- <0 RK_PC6 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie20x1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie20x1m0_pins: pcie20x1m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie20x1_2_clkreqn_m0 */
|
|
|
+- <3 RK_PC7 4 &pcfg_pull_none>,
|
|
|
+- /* pcie20x1_2_perstn_m0 */
|
|
|
+- <3 RK_PD1 4 &pcfg_pull_none>,
|
|
|
+- /* pcie20x1_2_waken_m0 */
|
|
|
+- <3 RK_PD0 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie20x1m1_pins: pcie20x1m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie20x1_2_clkreqn_m1 */
|
|
|
+- <4 RK_PB7 4 &pcfg_pull_none>,
|
|
|
+- /* pcie20x1_2_perstn_m1 */
|
|
|
+- <4 RK_PC1 4 &pcfg_pull_none>,
|
|
|
+- /* pcie20x1_2_waken_m1 */
|
|
|
+- <4 RK_PC0 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie20x1_2_button_rstn */
|
|
|
+- <4 RK_PB3 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie30phy {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30phy_pins: pcie30phy-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30phy_dtb0 */
|
|
|
+- <1 RK_PC4 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30phy_dtb1 */
|
|
|
+- <1 RK_PD1 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie30x1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x1m0_pins: pcie30x1m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x1_0_clkreqn_m0 */
|
|
|
+- <0 RK_PC0 12 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_0_perstn_m0 */
|
|
|
+- <0 RK_PC5 12 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_0_waken_m0 */
|
|
|
+- <0 RK_PC4 12 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_1_clkreqn_m0 */
|
|
|
+- <0 RK_PB5 12 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_1_perstn_m0 */
|
|
|
+- <0 RK_PB7 12 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_1_waken_m0 */
|
|
|
+- <0 RK_PB6 12 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x1m1_pins: pcie30x1m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x1_0_clkreqn_m1 */
|
|
|
+- <4 RK_PA3 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_0_perstn_m1 */
|
|
|
+- <4 RK_PA5 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_0_waken_m1 */
|
|
|
+- <4 RK_PA4 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_1_clkreqn_m1 */
|
|
|
+- <4 RK_PA0 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_1_perstn_m1 */
|
|
|
+- <4 RK_PA2 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_1_waken_m1 */
|
|
|
+- <4 RK_PA1 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x1m2_pins: pcie30x1m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x1_0_clkreqn_m2 */
|
|
|
+- <1 RK_PB5 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_0_perstn_m2 */
|
|
|
+- <1 RK_PB4 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_0_waken_m2 */
|
|
|
+- <1 RK_PB3 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_1_clkreqn_m2 */
|
|
|
+- <1 RK_PA0 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_1_perstn_m2 */
|
|
|
+- <1 RK_PA7 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x1_1_waken_m2 */
|
|
|
+- <1 RK_PA1 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x1_0_button_rstn */
|
|
|
+- <4 RK_PB1 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x1_1_button_rstn */
|
|
|
+- <4 RK_PB2 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie30x2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x2m0_pins: pcie30x2m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x2_clkreqn_m0 */
|
|
|
+- <0 RK_PD1 12 &pcfg_pull_none>,
|
|
|
+- /* pcie30x2_perstn_m0 */
|
|
|
+- <0 RK_PD4 12 &pcfg_pull_none>,
|
|
|
+- /* pcie30x2_waken_m0 */
|
|
|
+- <0 RK_PD2 12 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x2m1_pins: pcie30x2m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x2_clkreqn_m1 */
|
|
|
+- <4 RK_PA6 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x2_perstn_m1 */
|
|
|
+- <4 RK_PB0 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x2_waken_m1 */
|
|
|
+- <4 RK_PA7 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x2m2_pins: pcie30x2m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x2_clkreqn_m2 */
|
|
|
+- <3 RK_PD2 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x2_perstn_m2 */
|
|
|
+- <3 RK_PD4 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x2_waken_m2 */
|
|
|
+- <3 RK_PD3 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x2m3_pins: pcie30x2m3-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x2_clkreqn_m3 */
|
|
|
+- <1 RK_PD7 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x2_perstn_m3 */
|
|
|
+- <1 RK_PB7 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x2_waken_m3 */
|
|
|
+- <1 RK_PB6 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x2_button_rstn: pcie30x2-button-rstn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x2_button_rstn */
|
|
|
+- <3 RK_PC1 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pcie30x4 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x4m0_pins: pcie30x4m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x4_clkreqn_m0 */
|
|
|
+- <0 RK_PC6 12 &pcfg_pull_none>,
|
|
|
+- /* pcie30x4_perstn_m0 */
|
|
|
+- <0 RK_PD0 12 &pcfg_pull_none>,
|
|
|
+- /* pcie30x4_waken_m0 */
|
|
|
+- <0 RK_PC7 12 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x4m1_pins: pcie30x4m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x4_clkreqn_m1 */
|
|
|
+- <4 RK_PB4 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x4_perstn_m1 */
|
|
|
+- <4 RK_PB6 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x4_waken_m1 */
|
|
|
+- <4 RK_PB5 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x4m2_pins: pcie30x4m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x4_clkreqn_m2 */
|
|
|
+- <3 RK_PC4 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x4_perstn_m2 */
|
|
|
+- <3 RK_PC6 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x4_waken_m2 */
|
|
|
+- <3 RK_PC5 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x4m3_pins: pcie30x4m3-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x4_clkreqn_m3 */
|
|
|
+- <1 RK_PB0 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x4_perstn_m3 */
|
|
|
+- <1 RK_PB2 4 &pcfg_pull_none>,
|
|
|
+- /* pcie30x4_waken_m3 */
|
|
|
+- <1 RK_PB1 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pcie30x4_button_rstn: pcie30x4-button-rstn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pcie30x4_button_rstn */
|
|
|
+- <3 RK_PD5 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pdm0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m0_clk: pdm0m0-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0_clk0_m0 */
|
|
|
+- <1 RK_PC6 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m0_clk1: pdm0m0-clk1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0m0_clk1 */
|
|
|
+- <1 RK_PC4 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m0_sdi0: pdm0m0-sdi0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0m0_sdi0 */
|
|
|
+- <1 RK_PD5 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m0_sdi1: pdm0m0-sdi1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0m0_sdi1 */
|
|
|
+- <1 RK_PD1 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m0_sdi2: pdm0m0-sdi2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0m0_sdi2 */
|
|
|
+- <1 RK_PD2 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m0_sdi3: pdm0m0-sdi3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0m0_sdi3 */
|
|
|
+- <1 RK_PD3 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m1_clk: pdm0m1-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0_clk0_m1 */
|
|
|
+- <0 RK_PC0 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m1_clk1: pdm0m1-clk1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0m1_clk1 */
|
|
|
+- <0 RK_PC4 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m1_sdi0: pdm0m1-sdi0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0m1_sdi0 */
|
|
|
+- <0 RK_PC7 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m1_sdi1: pdm0m1-sdi1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0m1_sdi1 */
|
|
|
+- <0 RK_PD0 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m1_sdi2: pdm0m1-sdi2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0m1_sdi2 */
|
|
|
+- <0 RK_PD4 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm0m1_sdi3: pdm0m1-sdi3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm0m1_sdi3 */
|
|
|
+- <0 RK_PD6 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pdm1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m0_clk: pdm1m0-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1_clk0_m0 */
|
|
|
+- <4 RK_PD5 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m0_clk1: pdm1m0-clk1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1m0_clk1 */
|
|
|
+- <4 RK_PD4 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m0_sdi0: pdm1m0-sdi0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1m0_sdi0 */
|
|
|
+- <4 RK_PD3 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m0_sdi1: pdm1m0-sdi1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1m0_sdi1 */
|
|
|
+- <4 RK_PD2 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m0_sdi2: pdm1m0-sdi2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1m0_sdi2 */
|
|
|
+- <4 RK_PD1 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m0_sdi3: pdm1m0-sdi3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1m0_sdi3 */
|
|
|
+- <4 RK_PD0 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m1_clk: pdm1m1-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1_clk0_m1 */
|
|
|
+- <1 RK_PB4 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m1_clk1: pdm1m1-clk1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1m1_clk1 */
|
|
|
+- <1 RK_PB3 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m1_sdi0: pdm1m1-sdi0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1m1_sdi0 */
|
|
|
+- <1 RK_PA7 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m1_sdi1: pdm1m1-sdi1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1m1_sdi1 */
|
|
|
+- <1 RK_PB0 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m1_sdi2: pdm1m1-sdi2 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1m1_sdi2 */
|
|
|
+- <1 RK_PB1 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pdm1m1_sdi3: pdm1m1-sdi3 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pdm1m1_sdi3 */
|
|
|
+- <1 RK_PB2 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pmic {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pmic_pins: pmic-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pmic_int_l */
|
|
|
+- <0 RK_PA7 0 &pcfg_pull_up>,
|
|
|
+- /* pmic_sleep1 */
|
|
|
+- <0 RK_PA2 1 &pcfg_pull_none>,
|
|
|
+- /* pmic_sleep2 */
|
|
|
+- <0 RK_PA3 1 &pcfg_pull_none>,
|
|
|
+- /* pmic_sleep3 */
|
|
|
+- <0 RK_PC1 1 &pcfg_pull_none>,
|
|
|
+- /* pmic_sleep4 */
|
|
|
+- <0 RK_PC2 1 &pcfg_pull_none>,
|
|
|
+- /* pmic_sleep5 */
|
|
|
+- <0 RK_PC3 1 &pcfg_pull_none>,
|
|
|
+- /* pmic_sleep6 */
|
|
|
+- <0 RK_PD6 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pmu {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pmu_pins: pmu-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pmu_debug */
|
|
|
+- <0 RK_PA5 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm0m0_pins: pwm0m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm0_m0 */
|
|
|
+- <0 RK_PB7 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm0m1_pins: pwm0m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm0_m1 */
|
|
|
+- <1 RK_PD2 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm0m2_pins: pwm0m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm0_m2 */
|
|
|
+- <1 RK_PA2 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm1m0_pins: pwm1m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm1_m0 */
|
|
|
+- <0 RK_PC0 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm1m1_pins: pwm1m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm1_m1 */
|
|
|
+- <1 RK_PD3 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm1m2_pins: pwm1m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm1_m2 */
|
|
|
+- <1 RK_PA3 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm2m0_pins: pwm2m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm2_m0 */
|
|
|
+- <0 RK_PC4 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm2m1_pins: pwm2m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm2_m1 */
|
|
|
+- <3 RK_PB1 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm3 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm3m0_pins: pwm3m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm3_ir_m0 */
|
|
|
+- <0 RK_PD4 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm3m1_pins: pwm3m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm3_ir_m1 */
|
|
|
+- <3 RK_PB2 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm3m2_pins: pwm3m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm3_ir_m2 */
|
|
|
+- <1 RK_PC2 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm3m3_pins: pwm3m3-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm3_ir_m3 */
|
|
|
+- <1 RK_PA7 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm4 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm4m0_pins: pwm4m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm4_m0 */
|
|
|
+- <0 RK_PC5 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm5 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm5m0_pins: pwm5m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm5_m0 */
|
|
|
+- <0 RK_PB1 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm5m1_pins: pwm5m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm5_m1 */
|
|
|
+- <0 RK_PC6 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm6 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm6m0_pins: pwm6m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm6_m0 */
|
|
|
+- <0 RK_PC7 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm6m1_pins: pwm6m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm6_m1 */
|
|
|
+- <4 RK_PC1 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm7 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm7m0_pins: pwm7m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm7_ir_m0 */
|
|
|
+- <0 RK_PD0 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm7m1_pins: pwm7m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm7_ir_m1 */
|
|
|
+- <4 RK_PD4 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm7m2_pins: pwm7m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm7_ir_m2 */
|
|
|
+- <1 RK_PC3 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm8 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm8m0_pins: pwm8m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm8_m0 */
|
|
|
+- <3 RK_PA7 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm8m1_pins: pwm8m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm8_m1 */
|
|
|
+- <4 RK_PD0 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm8m2_pins: pwm8m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm8_m2 */
|
|
|
+- <3 RK_PD0 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm9 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm9m0_pins: pwm9m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm9_m0 */
|
|
|
+- <3 RK_PB0 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm9m1_pins: pwm9m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm9_m1 */
|
|
|
+- <4 RK_PD1 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm9m2_pins: pwm9m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm9_m2 */
|
|
|
+- <3 RK_PD1 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm10 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm10m0_pins: pwm10m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm10_m0 */
|
|
|
+- <3 RK_PA0 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm10m1_pins: pwm10m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm10_m1 */
|
|
|
+- <4 RK_PD3 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm10m2_pins: pwm10m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm10_m2 */
|
|
|
+- <3 RK_PD3 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm11 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm11m0_pins: pwm11m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm11_ir_m0 */
|
|
|
+- <3 RK_PA1 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm11m1_pins: pwm11m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm11_ir_m1 */
|
|
|
+- <4 RK_PB4 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm11m2_pins: pwm11m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm11_ir_m2 */
|
|
|
+- <1 RK_PC4 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm11m3_pins: pwm11m3-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm11_ir_m3 */
|
|
|
+- <3 RK_PD5 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm12 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm12m0_pins: pwm12m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm12_m0 */
|
|
|
+- <3 RK_PB5 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm12m1_pins: pwm12m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm12_m1 */
|
|
|
+- <4 RK_PB5 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm13 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm13m0_pins: pwm13m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm13_m0 */
|
|
|
+- <3 RK_PB6 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm13m1_pins: pwm13m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm13_m1 */
|
|
|
+- <4 RK_PB6 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm13m2_pins: pwm13m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm13_m2 */
|
|
|
+- <1 RK_PB7 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm14 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm14m0_pins: pwm14m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm14_m0 */
|
|
|
+- <3 RK_PC2 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm14m1_pins: pwm14m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm14_m1 */
|
|
|
+- <4 RK_PB2 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm14m2_pins: pwm14m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm14_m2 */
|
|
|
+- <1 RK_PD6 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- pwm15 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm15m0_pins: pwm15m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm15_ir_m0 */
|
|
|
+- <3 RK_PC3 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm15m1_pins: pwm15m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm15_ir_m1 */
|
|
|
+- <4 RK_PB3 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm15m2_pins: pwm15m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm15_ir_m2 */
|
|
|
+- <1 RK_PC6 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- pwm15m3_pins: pwm15m3-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* pwm15_ir_m3 */
|
|
|
+- <1 RK_PD7 11 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- refclk {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- refclk_pins: refclk-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* refclk_out */
|
|
|
+- <0 RK_PA0 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sata {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sata_pins: sata-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sata_cp_pod */
|
|
|
+- <0 RK_PC6 13 &pcfg_pull_none>,
|
|
|
+- /* sata_cpdet */
|
|
|
+- <0 RK_PD4 13 &pcfg_pull_none>,
|
|
|
+- /* sata_mp_switch */
|
|
|
+- <0 RK_PD5 13 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sata0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sata0m0_pins: sata0m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sata0_act_led_m0 */
|
|
|
+- <4 RK_PB6 6 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sata0m1_pins: sata0m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sata0_act_led_m1 */
|
|
|
+- <1 RK_PB3 6 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sata1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sata1m0_pins: sata1m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sata1_act_led_m0 */
|
|
|
+- <4 RK_PB5 6 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sata1m1_pins: sata1m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sata1_act_led_m1 */
|
|
|
+- <1 RK_PA1 6 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sata2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sata2m0_pins: sata2m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sata2_act_led_m0 */
|
|
|
+- <4 RK_PB1 6 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sata2m1_pins: sata2m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sata2_act_led_m1 */
|
|
|
+- <1 RK_PB7 6 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sdio {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sdiom1_pins: sdiom1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sdio_clk_m1 */
|
|
|
+- <3 RK_PA5 2 &pcfg_pull_none>,
|
|
|
+- /* sdio_cmd_m1 */
|
|
|
+- <3 RK_PA4 2 &pcfg_pull_none>,
|
|
|
+- /* sdio_d0_m1 */
|
|
|
+- <3 RK_PA0 2 &pcfg_pull_none>,
|
|
|
+- /* sdio_d1_m1 */
|
|
|
+- <3 RK_PA1 2 &pcfg_pull_none>,
|
|
|
+- /* sdio_d2_m1 */
|
|
|
+- <3 RK_PA2 2 &pcfg_pull_none>,
|
|
|
+- /* sdio_d3_m1 */
|
|
|
+- <3 RK_PA3 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- sdmmc {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sdmmc_bus4: sdmmc-bus4 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sdmmc_d0 */
|
|
|
+- <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* sdmmc_d1 */
|
|
|
+- <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* sdmmc_d2 */
|
|
|
+- <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
|
|
|
+- /* sdmmc_d3 */
|
|
|
+- <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sdmmc_clk: sdmmc-clk {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sdmmc_clk */
|
|
|
+- <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sdmmc_cmd: sdmmc-cmd {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sdmmc_cmd */
|
|
|
+- <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sdmmc_det: sdmmc-det {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sdmmc_det */
|
|
|
+- <0 RK_PA4 1 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- sdmmc_pwren: sdmmc-pwren {
|
|
|
+- rockchip,pins =
|
|
|
+- /* sdmmc_pwren */
|
|
|
+- <0 RK_PA5 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- spdif0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spdif0m0_tx: spdif0m0-tx {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spdif0m0_tx */
|
|
|
+- <1 RK_PB6 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spdif0m1_tx: spdif0m1-tx {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spdif0m1_tx */
|
|
|
+- <4 RK_PB4 6 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- spdif1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spdif1m0_tx: spdif1m0-tx {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spdif1m0_tx */
|
|
|
+- <1 RK_PB7 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spdif1m1_tx: spdif1m1-tx {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spdif1m1_tx */
|
|
|
+- <4 RK_PB1 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spdif1m2_tx: spdif1m2-tx {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spdif1m2_tx */
|
|
|
+- <4 RK_PC1 3 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m0_pins: spi0m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_clk_m0 */
|
|
|
+- <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi0_miso_m0 */
|
|
|
+- <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi0_mosi_m0 */
|
|
|
+- <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m0_cs0: spi0m0-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_cs0_m0 */
|
|
|
+- <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m0_cs1: spi0m0-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_cs1_m0 */
|
|
|
+- <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m1_pins: spi0m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_clk_m1 */
|
|
|
+- <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi0_miso_m1 */
|
|
|
+- <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi0_mosi_m1 */
|
|
|
+- <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m1_cs0: spi0m1-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_cs0_m1 */
|
|
|
+- <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m1_cs1: spi0m1-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_cs1_m1 */
|
|
|
+- <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m2_pins: spi0m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_clk_m2 */
|
|
|
+- <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi0_miso_m2 */
|
|
|
+- <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi0_mosi_m2 */
|
|
|
+- <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m2_cs0: spi0m2-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_cs0_m2 */
|
|
|
+- <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m2_cs1: spi0m2-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_cs1_m2 */
|
|
|
+- <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m3_pins: spi0m3-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_clk_m3 */
|
|
|
+- <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi0_miso_m3 */
|
|
|
+- <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi0_mosi_m3 */
|
|
|
+- <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m3_cs0: spi0m3-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_cs0_m3 */
|
|
|
+- <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi0m3_cs1: spi0m3-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi0_cs1_m3 */
|
|
|
+- <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi1m1_pins: spi1m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi1_clk_m1 */
|
|
|
+- <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi1_miso_m1 */
|
|
|
+- <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi1_mosi_m1 */
|
|
|
+- <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi1m1_cs0: spi1m1-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi1_cs0_m1 */
|
|
|
+- <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi1m1_cs1: spi1m1-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi1_cs1_m1 */
|
|
|
+- <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi1m2_pins: spi1m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi1_clk_m2 */
|
|
|
+- <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi1_miso_m2 */
|
|
|
+- <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi1_mosi_m2 */
|
|
|
+- <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi1m2_cs0: spi1m2-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi1_cs0_m2 */
|
|
|
+- <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi1m2_cs1: spi1m2-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi1_cs1_m2 */
|
|
|
+- <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi2m0_pins: spi2m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi2_clk_m0 */
|
|
|
+- <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi2_miso_m0 */
|
|
|
+- <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi2_mosi_m0 */
|
|
|
+- <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi2m0_cs0: spi2m0-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi2_cs0_m0 */
|
|
|
+- <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi2m0_cs1: spi2m0-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi2_cs1_m0 */
|
|
|
+- <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi2m1_pins: spi2m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi2_clk_m1 */
|
|
|
+- <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi2_miso_m1 */
|
|
|
+- <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi2_mosi_m1 */
|
|
|
+- <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi2m1_cs0: spi2m1-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi2_cs0_m1 */
|
|
|
+- <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi2m1_cs1: spi2m1-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi2_cs1_m1 */
|
|
|
+- <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi2m2_pins: spi2m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi2_clk_m2 */
|
|
|
+- <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi2_miso_m2 */
|
|
|
+- <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi2_mosi_m2 */
|
|
|
+- <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi2m2_cs0: spi2m2-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi2_cs0_m2 */
|
|
|
+- <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi2m2_cs1: spi2m2-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi2_cs1_m2 */
|
|
|
+- <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi3 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m1_pins: spi3m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_clk_m1 */
|
|
|
+- <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi3_miso_m1 */
|
|
|
+- <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi3_mosi_m1 */
|
|
|
+- <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m1_cs0: spi3m1-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_cs0_m1 */
|
|
|
+- <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m1_cs1: spi3m1-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_cs1_m1 */
|
|
|
+- <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m2_pins: spi3m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_clk_m2 */
|
|
|
+- <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi3_miso_m2 */
|
|
|
+- <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi3_mosi_m2 */
|
|
|
+- <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m2_cs0: spi3m2-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_cs0_m2 */
|
|
|
+- <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m2_cs1: spi3m2-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_cs1_m2 */
|
|
|
+- <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m3_pins: spi3m3-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_clk_m3 */
|
|
|
+- <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi3_miso_m3 */
|
|
|
+- <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi3_mosi_m3 */
|
|
|
+- <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m3_cs0: spi3m3-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_cs0_m3 */
|
|
|
+- <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi3m3_cs1: spi3m3-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi3_cs1_m3 */
|
|
|
+- <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- spi4 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi4m0_pins: spi4m0-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi4_clk_m0 */
|
|
|
+- <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi4_miso_m0 */
|
|
|
+- <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi4_mosi_m0 */
|
|
|
+- <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi4m0_cs0: spi4m0-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi4_cs0_m0 */
|
|
|
+- <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi4m0_cs1: spi4m0-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi4_cs1_m0 */
|
|
|
+- <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi4m1_pins: spi4m1-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi4_clk_m1 */
|
|
|
+- <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi4_miso_m1 */
|
|
|
+- <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi4_mosi_m1 */
|
|
|
+- <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi4m1_cs0: spi4m1-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi4_cs0_m1 */
|
|
|
+- <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi4m1_cs1: spi4m1-cs1 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi4_cs1_m1 */
|
|
|
+- <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi4m2_pins: spi4m2-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi4_clk_m2 */
|
|
|
+- <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi4_miso_m2 */
|
|
|
+- <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
|
|
|
+- /* spi4_mosi_m2 */
|
|
|
+- <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- spi4m2_cs0: spi4m2-cs0 {
|
|
|
+- rockchip,pins =
|
|
|
+- /* spi4_cs0_m2 */
|
|
|
+- <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- tsadc {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- tsadcm1_shut: tsadcm1-shut {
|
|
|
+- rockchip,pins =
|
|
|
+- /* tsadcm1_shut */
|
|
|
+- <0 RK_PA2 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- tsadc_shut: tsadc-shut {
|
|
|
+- rockchip,pins =
|
|
|
+- /* tsadc_shut */
|
|
|
+- <0 RK_PA1 2 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- tsadc_shut_org: tsadc-shut-org {
|
|
|
+- rockchip,pins =
|
|
|
+- /* tsadc_shut_org */
|
|
|
+- <0 RK_PA1 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart0 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart0m0_xfer: uart0m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart0_rx_m0 */
|
|
|
+- <0 RK_PC4 4 &pcfg_pull_up>,
|
|
|
+- /* uart0_tx_m0 */
|
|
|
+- <0 RK_PC5 4 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart0m1_xfer: uart0m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart0_rx_m1 */
|
|
|
+- <0 RK_PB0 4 &pcfg_pull_up>,
|
|
|
+- /* uart0_tx_m1 */
|
|
|
+- <0 RK_PB1 4 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart0m2_xfer: uart0m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart0_rx_m2 */
|
|
|
+- <4 RK_PA4 10 &pcfg_pull_up>,
|
|
|
+- /* uart0_tx_m2 */
|
|
|
+- <4 RK_PA3 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart0_ctsn: uart0-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart0_ctsn */
|
|
|
+- <0 RK_PD1 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart0_rtsn: uart0-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart0_rtsn */
|
|
|
+- <0 RK_PC6 4 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart1 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart1m1_xfer: uart1m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart1_rx_m1 */
|
|
|
+- <1 RK_PB7 10 &pcfg_pull_up>,
|
|
|
+- /* uart1_tx_m1 */
|
|
|
+- <1 RK_PB6 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart1m1_ctsn: uart1m1-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart1m1_ctsn */
|
|
|
+- <1 RK_PD7 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart1m1_rtsn: uart1m1-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart1m1_rtsn */
|
|
|
+- <1 RK_PD6 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart1m2_xfer: uart1m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart1_rx_m2 */
|
|
|
+- <0 RK_PD2 10 &pcfg_pull_up>,
|
|
|
+- /* uart1_tx_m2 */
|
|
|
+- <0 RK_PD1 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart1m2_ctsn: uart1m2-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart1m2_ctsn */
|
|
|
+- <0 RK_PD0 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart1m2_rtsn: uart1m2-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart1m2_rtsn */
|
|
|
+- <0 RK_PC7 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart2 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart2m0_xfer: uart2m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart2_rx_m0 */
|
|
|
+- <0 RK_PB6 10 &pcfg_pull_up>,
|
|
|
+- /* uart2_tx_m0 */
|
|
|
+- <0 RK_PB5 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart2m1_xfer: uart2m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart2_rx_m1 */
|
|
|
+- <4 RK_PD1 10 &pcfg_pull_up>,
|
|
|
+- /* uart2_tx_m1 */
|
|
|
+- <4 RK_PD0 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart2m2_xfer: uart2m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart2_rx_m2 */
|
|
|
+- <3 RK_PB2 10 &pcfg_pull_up>,
|
|
|
+- /* uart2_tx_m2 */
|
|
|
+- <3 RK_PB1 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart2_ctsn: uart2-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart2_ctsn */
|
|
|
+- <3 RK_PB4 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart2_rtsn: uart2-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart2_rtsn */
|
|
|
+- <3 RK_PB3 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart3 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart3m0_xfer: uart3m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart3_rx_m0 */
|
|
|
+- <1 RK_PC0 10 &pcfg_pull_up>,
|
|
|
+- /* uart3_tx_m0 */
|
|
|
+- <1 RK_PC1 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart3m1_xfer: uart3m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart3_rx_m1 */
|
|
|
+- <3 RK_PB6 10 &pcfg_pull_up>,
|
|
|
+- /* uart3_tx_m1 */
|
|
|
+- <3 RK_PB5 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart3m2_xfer: uart3m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart3_rx_m2 */
|
|
|
+- <4 RK_PA6 10 &pcfg_pull_up>,
|
|
|
+- /* uart3_tx_m2 */
|
|
|
+- <4 RK_PA5 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart3_ctsn: uart3-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart3_ctsn */
|
|
|
+- <1 RK_PC3 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart3_rtsn: uart3-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart3_rtsn */
|
|
|
+- <1 RK_PC2 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart4 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart4m0_xfer: uart4m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart4_rx_m0 */
|
|
|
+- <1 RK_PD3 10 &pcfg_pull_up>,
|
|
|
+- /* uart4_tx_m0 */
|
|
|
+- <1 RK_PD2 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart4m1_xfer: uart4m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart4_rx_m1 */
|
|
|
+- <3 RK_PD0 10 &pcfg_pull_up>,
|
|
|
+- /* uart4_tx_m1 */
|
|
|
+- <3 RK_PD1 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart4m2_xfer: uart4m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart4_rx_m2 */
|
|
|
+- <1 RK_PB2 10 &pcfg_pull_up>,
|
|
|
+- /* uart4_tx_m2 */
|
|
|
+- <1 RK_PB3 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart4_ctsn: uart4-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart4_ctsn */
|
|
|
+- <1 RK_PC7 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart4_rtsn: uart4-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart4_rtsn */
|
|
|
+- <1 RK_PC5 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart5 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart5m0_xfer: uart5m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart5_rx_m0 */
|
|
|
+- <4 RK_PD4 10 &pcfg_pull_up>,
|
|
|
+- /* uart5_tx_m0 */
|
|
|
+- <4 RK_PD5 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart5m0_ctsn: uart5m0-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart5m0_ctsn */
|
|
|
+- <4 RK_PD2 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart5m0_rtsn: uart5m0-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart5m0_rtsn */
|
|
|
+- <4 RK_PD3 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart5m1_xfer: uart5m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart5_rx_m1 */
|
|
|
+- <3 RK_PC5 10 &pcfg_pull_up>,
|
|
|
+- /* uart5_tx_m1 */
|
|
|
+- <3 RK_PC4 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart5m1_ctsn: uart5m1-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart5m1_ctsn */
|
|
|
+- <2 RK_PA2 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart5m1_rtsn: uart5m1-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart5m1_rtsn */
|
|
|
+- <2 RK_PA3 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart5m2_xfer: uart5m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart5_rx_m2 */
|
|
|
+- <2 RK_PD4 10 &pcfg_pull_up>,
|
|
|
+- /* uart5_tx_m2 */
|
|
|
+- <2 RK_PD5 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart6 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart6m1_xfer: uart6m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart6_rx_m1 */
|
|
|
+- <1 RK_PA0 10 &pcfg_pull_up>,
|
|
|
+- /* uart6_tx_m1 */
|
|
|
+- <1 RK_PA1 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart6m1_ctsn: uart6m1-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart6m1_ctsn */
|
|
|
+- <1 RK_PA3 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart6m1_rtsn: uart6m1-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart6m1_rtsn */
|
|
|
+- <1 RK_PA2 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart6m2_xfer: uart6m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart6_rx_m2 */
|
|
|
+- <1 RK_PD1 10 &pcfg_pull_up>,
|
|
|
+- /* uart6_tx_m2 */
|
|
|
+- <1 RK_PD0 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart7 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart7m1_xfer: uart7m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart7_rx_m1 */
|
|
|
+- <3 RK_PC1 10 &pcfg_pull_up>,
|
|
|
+- /* uart7_tx_m1 */
|
|
|
+- <3 RK_PC0 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart7m1_ctsn: uart7m1-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart7m1_ctsn */
|
|
|
+- <3 RK_PC3 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart7m1_rtsn: uart7m1-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart7m1_rtsn */
|
|
|
+- <3 RK_PC2 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart7m2_xfer: uart7m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart7_rx_m2 */
|
|
|
+- <1 RK_PB4 10 &pcfg_pull_up>,
|
|
|
+- /* uart7_tx_m2 */
|
|
|
+- <1 RK_PB5 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart8 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart8m0_xfer: uart8m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart8_rx_m0 */
|
|
|
+- <4 RK_PB1 10 &pcfg_pull_up>,
|
|
|
+- /* uart8_tx_m0 */
|
|
|
+- <4 RK_PB0 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart8m0_ctsn: uart8m0-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart8m0_ctsn */
|
|
|
+- <4 RK_PB3 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart8m0_rtsn: uart8m0-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart8m0_rtsn */
|
|
|
+- <4 RK_PB2 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart8m1_xfer: uart8m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart8_rx_m1 */
|
|
|
+- <3 RK_PA3 10 &pcfg_pull_up>,
|
|
|
+- /* uart8_tx_m1 */
|
|
|
+- <3 RK_PA2 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart8m1_ctsn: uart8m1-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart8m1_ctsn */
|
|
|
+- <3 RK_PA5 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart8m1_rtsn: uart8m1-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart8m1_rtsn */
|
|
|
+- <3 RK_PA4 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart8_xfer: uart8-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart8_rx_ */
|
|
|
+- <4 RK_PB1 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- uart9 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart9m0_xfer: uart9m0-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart9_rx_m0 */
|
|
|
+- <2 RK_PC4 10 &pcfg_pull_up>,
|
|
|
+- /* uart9_tx_m0 */
|
|
|
+- <2 RK_PC2 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart9m1_xfer: uart9m1-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart9_rx_m1 */
|
|
|
+- <4 RK_PB5 10 &pcfg_pull_up>,
|
|
|
+- /* uart9_tx_m1 */
|
|
|
+- <4 RK_PB4 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart9m1_ctsn: uart9m1-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart9m1_ctsn */
|
|
|
+- <4 RK_PA1 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart9m1_rtsn: uart9m1-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart9m1_rtsn */
|
|
|
+- <4 RK_PA0 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart9m2_xfer: uart9m2-xfer {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart9_rx_m2 */
|
|
|
+- <3 RK_PD4 10 &pcfg_pull_up>,
|
|
|
+- /* uart9_tx_m2 */
|
|
|
+- <3 RK_PD5 10 &pcfg_pull_up>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart9m2_ctsn: uart9m2-ctsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart9m2_ctsn */
|
|
|
+- <3 RK_PD3 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+-
|
|
|
+- /omit-if-no-ref/
|
|
|
+- uart9m2_rtsn: uart9m2-rtsn {
|
|
|
+- rockchip,pins =
|
|
|
+- /* uart9m2_rtsn */
|
|
|
+- <3 RK_PD2 10 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- vop {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- vop_pins: vop-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* vop_post_empty */
|
|
|
+- <1 RK_PA2 1 &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-};
|
|
|
+-
|
|
|
+-/*
|
|
|
+- * This part is edited handly.
|
|
|
+- */
|
|
|
+-&pinctrl {
|
|
|
+- bt656 {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- bt656_pins: bt656-pins {
|
|
|
+- rockchip,pins =
|
|
|
+- /* bt1120_clkout */
|
|
|
+- <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
|
|
|
+- /* bt1120_d0 */
|
|
|
+- <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
|
|
|
+- /* bt1120_d1 */
|
|
|
+- <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
|
|
|
+- /* bt1120_d2 */
|
|
|
+- <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
|
|
|
+- /* bt1120_d3 */
|
|
|
+- <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
|
|
|
+- /* bt1120_d4 */
|
|
|
+- <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
|
|
|
+- /* bt1120_d5 */
|
|
|
+- <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
|
|
|
+- /* bt1120_d6 */
|
|
|
+- <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
|
|
|
+- /* bt1120_d7 */
|
|
|
+- <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-
|
|
|
+- gpio-func {
|
|
|
+- /omit-if-no-ref/
|
|
|
+- tsadc_gpio_func: tsadc-gpio-func {
|
|
|
+- rockchip,pins =
|
|
|
+- <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
+- };
|
|
|
+- };
|
|
|
+-};
|
Tianling Shen