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@@ -4,10 +4,77 @@
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#include <linux/init.h>
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#include <asm/mach-ralink/rt288x.h>
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-#include <asm/mach-ralink/rt288x_pci.h>
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-extern int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
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-extern int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
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+#define RT2880_PCI_SLOT1_BASE 0x20000000
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+#define RALINK_PCI_BASE 0xA0440000
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+#define RT2880_PCI_PCICFG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0000))
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+#define RT2880_PCI_ARBCTL ((unsigned long*)(RALINK_PCI_BASE + 0x0080))
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+#define RT2880_PCI_BAR0SETUP_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0010))
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+#define RT2880_PCI_CONFIG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0020))
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+#define RT2880_PCI_CONFIG_DATA ((unsigned long*)(RALINK_PCI_BASE + 0x0024))
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+#define RT2880_PCI_MEMBASE ((unsigned long*)(RALINK_PCI_BASE + 0x0028))
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+#define RT2880_PCI_IOBASE ((unsigned long*)(RALINK_PCI_BASE + 0x002C))
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+#define RT2880_PCI_IMBASEBAR0_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0018))
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+#define RT2880_PCI_ID ((unsigned long*)(RALINK_PCI_BASE + 0x0030))
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+#define RT2880_PCI_CLASS ((unsigned long*)(RALINK_PCI_BASE + 0x0034))
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+#define RT2880_PCI_SUBID ((unsigned long*)(RALINK_PCI_BASE + 0x0038))
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+#define RT2880_PCI_PCIMSK_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x000C))
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+
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+#define PCI_ACCESS_READ 0
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+#define PCI_ACCESS_WRITE 1
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+
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+static int config_access(unsigned char access_type, struct pci_bus *bus,
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+ unsigned int devfn, unsigned char where, u32 * data)
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+{
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+ unsigned int slot = PCI_SLOT(devfn);
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+ unsigned int address;
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+ u8 func = PCI_FUNC(devfn);
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+ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where& 0xfc) | 0x80000000;
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+ writel(address, RT2880_PCI_CONFIG_ADDR);
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+ if (access_type == PCI_ACCESS_WRITE)
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+ writel(*data, RT2880_PCI_CONFIG_DATA);
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+ else
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+ *data = readl(RT2880_PCI_CONFIG_DATA);
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+ return 0;
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+}
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+
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+int
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+pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
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+{
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+ u32 data = 0;
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+ if(config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ if(size == 1)
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+ *val = (data >> ((where & 3) << 3)) & 0xff;
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+ else if(size == 2)
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+ *val = (data >> ((where & 3) << 3)) & 0xffff;
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+ else
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+ *val = data;
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+int
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+pci_config_write(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 val)
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+{
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+ u32 data = 0;
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+ if(size == 4)
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+ {
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+ data = val;
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+ } else {
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+ if(config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ if(size == 1)
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+ data = (data & ~(0xff << ((where & 3) << 3))) |
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+ (val << ((where & 3) << 3));
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+ else if(size == 2)
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+ data = (data & ~(0xffff << ((where & 3) << 3))) |
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+ (val << ((where & 3) << 3));
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+ }
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+ if(config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ return PCIBIOS_SUCCESSFUL;
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+}
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struct pci_ops rt2880_pci_ops = {
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.read = pci_config_read,
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