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@@ -0,0 +1,318 @@
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+// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
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+/*
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+ * Device Tree file for ipTIME NAS1dual
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+ *
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+ * Copyright (C) 2020 Sungbo Eo <[email protected]>
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+ *
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+ * Based on armada-385-linksys.dtsi
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+ * Copyright (C) 2015 Imre Kaloz <[email protected]>
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+ */
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/input/input.h>
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+#include "armada-385.dtsi"
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+
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+/ {
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+ model = "ipTIME NAS1dual";
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+ compatible = "iptime,nas1dual", "marvell,armada385", "marvell,armada380";
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+
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+ aliases {
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+ led-boot = &led_ready;
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+ led-failsafe = &led_ready;
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+ led-running = &led_ready;
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+ led-upgrade = &led_ready;
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+ label-mac-device = ð0;
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+ };
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+
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+ chosen {
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+ bootargs = "console=ttyS0,115200n8";
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ memory@0 {
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+ device_type = "memory";
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+ reg = <0x00000000 0x80000000>; /* 2GB */
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+ };
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+
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+ soc {
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+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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+ };
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gpio_keys_pins>;
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+
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+ power {
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+ label = "Power Button";
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+ linux,input-type = <EV_SW>;
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+ linux,code = <KEY_POWER>;
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+ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ reset {
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+ label = "Reset Button";
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+ linux,code = <KEY_RESTART>;
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+ gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ copy {
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+ label = "USB Copy Button";
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+ linux,code = <KEY_COPY>;
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+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+
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+ gpio-leds {
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+ compatible = "gpio-leds";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gpio_leds_pins>;
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+
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+ led_ready: ready {
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+ label = "blue:ready";
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+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ hdd {
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+ label = "blue:hdd";
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+ gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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+ linux,default-trigger = "disk-activity";
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+ };
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+
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+ usb {
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+ label = "blue:usb";
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+ gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
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+ trigger-sources = <&usb3_0_port1 &usb3_0_port2>;
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+ linux,default-trigger = "usbport";
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+ };
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+ };
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+
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+ gpio-fan {
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+ compatible = "gpio-fan";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gpio_fan_pins>;
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+ gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>,
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+ <&gpio1 18 GPIO_ACTIVE_HIGH>;
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+ /* We don't know the exact rpm, just use dummy values here. */
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+ gpio-fan,speed-map = <0 0>, <1 1>, <2 2>;
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+ #cooling-cells = <2>;
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+ };
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+
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+ gpio-poweroff {
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+ compatible = "gpio-poweroff";
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+ gpios = <&pca9536 1 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ regulators {
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sata_power_pins>;
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+
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+ reg_sata_power: regulator@1 {
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+ compatible = "regulator-fixed";
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+ reg = <1>;
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+ regulator-name = "sata-power";
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+ regulator-min-microvolt = <12000000>;
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+ regulator-max-microvolt = <12000000>;
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+ gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
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+ regulator-always-on;
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+ };
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+ };
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+};
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+
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+&ahci0 {
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ sata-port@0 {
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+ reg = <0>;
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+ target-supply = <®_sata_power>;
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+ #thermal-sensor-cells = <0>;
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+ };
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+};
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+
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+&bm {
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+ status = "okay";
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+};
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+
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+&bm_bppi {
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+ status = "okay";
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+};
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+
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+ð0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&ge0_rgmii_pins>;
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+ status = "okay";
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+ phy-handle = <ðphy1>;
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+ phy-connection-type = "rgmii-id";
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+ buffer-manager = <&bm>;
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+ bm,pool-long = <0>;
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+ bm,pool-short = <1>;
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+ nvmem-cells = <&macaddr_uboot_fffa8>;
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+ nvmem-cell-names = "mac-address";
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+};
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+
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+ð1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&ge1_rgmii_pins>;
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+ status = "okay";
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+ phy-handle = <ðphy0>;
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+ phy-connection-type = "rgmii-id";
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+ buffer-manager = <&bm>;
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+ bm,pool-long = <2>;
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+ bm,pool-short = <3>;
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+ nvmem-cells = <&macaddr_uboot_fffa8>;
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+ nvmem-cell-names = "mac-address";
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+};
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+
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+&i2c0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c0_pins>;
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+ status = "okay";
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+
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+ pca9536: gpio@41 {
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+ compatible = "nxp,pca9536";
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+ reg = <0x41>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ gpio-line-names = "power-led", "power-board";
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+ };
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+};
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+
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+&mdio {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mdio_pins>;
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+
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+ /* LED1: On - Link, Blink - Activity, Off - No Link */
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+
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+ ethphy0: ethernet-phy@0 {
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+ reg = <0>;
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+ marvell,reg-init = <3 16 0 0x1017>;
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+ };
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+
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+ ethphy1: ethernet-phy@1 {
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+ reg = <1>;
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+ marvell,reg-init = <3 16 0 0x1017>;
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+ };
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+};
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+
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+&pinctrl {
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+ gpio_keys_pins: gpio-keys-pins {
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+ marvell,pins = "mpp24", "mpp26", "mpp48";
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+ marvell,function = "gpio";
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+ };
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+
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+ gpio_leds_pins: gpio-leds-pins {
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+ marvell,pins = "mpp18", "mpp20", "mpp51";
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+ marvell,function = "gpio";
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+ };
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+
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+ gpio_fan_pins: gpio-fan-pins {
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+ marvell,pins = "mpp25", "mpp50";
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+ marvell,function = "gpio";
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+ };
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+
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+ sata_power_pins: sata-power-pins {
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+ marvell,pins = "mpp52";
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+ marvell,function = "gpio";
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+ };
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+
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+ uart1_pins_alt: uart-pins-1-alt {
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+ marvell,pins = "mpp45", "mpp46";
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+ marvell,function = "ua1";
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+ };
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+};
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+
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+&spi1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi1_pins>;
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+ status = "okay";
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+
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+ flash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <40000000>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ reg = <0x00000000 0x00100000>;
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+ label = "u-boot";
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+ read-only;
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+
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+ compatible = "nvmem-cells";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ macaddr_uboot_fffa8: macaddr@fffa8 {
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+ reg = <0xfffa8 0x6>;
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+ };
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+ };
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+
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+ partition@100000 {
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+ reg = <0x00100000 0x03ec0000>;
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+ label = "firmware";
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+
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ reg = <0x00000000 0x00600000>;
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+ label = "kernel";
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+ };
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+
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+ partition@600000 {
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+ reg = <0x00600000 0x038c0000>;
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+ label = "rootfs";
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+ };
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+ };
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+
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+ partition@3fc0000 {
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+ reg = <0x03fc0000 0x00040000>;
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+ label = "config";
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+ read-only;
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+ };
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+ };
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+ };
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+};
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+
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+&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_pins>;
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart1_pins_alt>;
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+ status = "okay";
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+};
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+
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+&usb3_0 {
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ usb3_0_port1: port@1 {
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+ reg = <1>;
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+ #trigger-source-cells = <0>;
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+ };
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+
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+ usb3_0_port2: port@2 {
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+ reg = <2>;
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+ #trigger-source-cells = <0>;
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+ };
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+};
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