qualcommbe: ipq95xx: Update patch with upstream version and refresh

Update patch with upstream version and automatically refresh with make
target/linux/refresh.

Also backport one additional fix patch for NAND patch and drop a patch
merged upstream.

Link: https://github.com/openwrt/openwrt/pull/17725
Signed-off-by: Christian Marangi <[email protected]>

target/linux/qualcommbe/patches-6.6/100-02-mtd-rawnand-qcom-cleanup-qcom_nandc-driver.patch → target/linux/qualcommbe/patches-6.6/016-01-v6.14-mtd-rawnand-qcom-cleanup-qcom_nandc-driver.patch

@@ -1,101 +1,27 @@
-From 1142a905d3450a40ac03cbe1426b16cd9650c5f7 Mon Sep 17 00:00:00 2001
+From 8c52932da5e6756fa66f52f0720da283fba13aa6 Mon Sep 17 00:00:00 2001
 From: Md Sadre Alam <[email protected]>
-Date: Thu, 4 Apr 2024 16:19:43 +0530
-Subject: [PATCH v10 2/8] mtd: rawnand: qcom: cleanup qcom_nandc driver
+Date: Wed, 20 Nov 2024 14:45:00 +0530
+Subject: [PATCH 1/4] mtd: rawnand: qcom: cleanup qcom_nandc driver
 
-cleanup qcom_nandc driver as below
+Perform a global cleanup of the Qualcomm NAND
+controller driver with the following improvements:
 
-- Remove register value indirection api
+- Remove register value indirection API
 
-- Remove set_reg() api
+- Remove set_reg() API
 
-- Convert read_loc_first & read_loc_last macro to function
+- Convert read_loc_first & read_loc_last macro to functions
 
-- Renamed multiple variables
+- Rename multiple variables
 
 Signed-off-by: Md Sadre Alam <[email protected]>
+Signed-off-by: Miquel Raynal <[email protected]>
 ---
+ drivers/mtd/nand/raw/qcom_nandc.c | 516 ++++++++++++++----------------
+ 1 file changed, 234 insertions(+), 282 deletions(-)
 
-Change in [v10]
-
-* No change
-
-Change in [v9]
-
-* Changed type of cmd1, vld to u32 from __le32 in qcom_nand_controller
-  structure
-* Changed type of cfg0, cfg1, cfg0_raw, cfg1_raw, clrflashstatus,
-  ecc_buf_cfg, ecc_bch_cfg, clrreadstatus to u32 in qcom_nand_host
-  structure
-* In nandc_set_read_loc_first() api added cpu_to_le32() macro to fix
-  compilation warning reported by kernel test bot
-* In nandc_set_read_loc_last() api added cpu_to_le32() macro to fix
-  compilation warning reported by kernel test bot
-* Changed data type of cw_offset, read_size, is_last_read_loc to
-  u32 in nandc_set_read_loc() api to fix compilation warning reported
-  by kernel test bot
-* In set_address() api added cpu_to_le32() macro to fix compilation
-  warning reported by kernel test bot
-* In update_rw_regs() api added cpu_to_le32() macro to fix compilation
-  warning reported by kernel test bot
-* In qcom_op_cmd_mapping() api added cpu_to_le32() macro to fix compilation
-  warning reported by kernel test bot
-* In qcom_read_status_exec() api added cpu_to_le32() macro to fix compilation
-  warning reported by kernel test bot
-* In qcom_read_id_type_exec() api added cpu_to_le32() macro to fix compilation
-  warning reported by kernel test bot
-* In qcom_misc_cmd_type_exec() api added cpu_to_le32() macro to fix compilation
-  warning reported by kernel test bot
-* In qcom_param_page_type_exec() api added cpu_to_le32() macro to fix
-  compilation warning reported by kernel test bot 
-
-Change in [v8]
-
-* Fixed compilation warning reported by kernel test robot
-* Added "chip" description in nandc_set_read_loc_first()
-* Added "chip" description in nandc_set_read_loc_last()
-* Changed data type of read_location0, read_location1, 
-  read_location2, read_location3, read_location_last0,
-  read_location_last1, read_location_last2, read_location_last3,
-  addr0, addr1, cmd, cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg,
-  clrflashstatus, clrreadstatus, orig_cmd1, orig_vld to 
-  __le32 to fix compilation warning reported by kernel test robot
- 
-Change in [v7]
-
-* No change
-
-Change in [v6]
-
-* No change
-
-Change in [v5]
-
-* Cleand up raw nand driver.
-
-* Removed register value indirection
-
-* Removed set_reg() api.
-
-Change in [v4]
-
-* This patch was not included in [v4]
-
-Change in [v3]
-
-* This patch was not included in [v3]
-
-Change in [v2]
-
-* This patch was not included in [v2]
-
-Change in [v1]
-
-* This patch was not included in [v1]
-
- drivers/mtd/nand/raw/qcom_nandc.c | 506 ++++++++++++++----------------
- 1 file changed, 229 insertions(+), 277 deletions(-)
-
+diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
+index 636bba2528bf..9ae8c9f2ab55 100644
 --- a/drivers/mtd/nand/raw/qcom_nandc.c
 +++ b/drivers/mtd/nand/raw/qcom_nandc.c
 @@ -189,17 +189,6 @@
@@ -153,7 +79,7 @@ Change in [v1]
 - * @is_bam - whether NAND controller is using BAM
 - * @is_qpic - whether NAND CTRL is part of qpic IP
 - * @qpic_v2 - flag to indicate QPIC IP version 2
-+ * @supports_bam - whether NAND controller is using BAM
++ * @supports_bam - whether NAND controller is using Bus Access Manager (BAM)
 + * @nandc_part_of_qpic - whether NAND controller is part of qpic IP
 + * @qpic_version2 - flag to indicate QPIC IP version 2
   * @use_codeword_fixup - whether NAND has different layout for boot partitions
@@ -170,7 +96,7 @@ Change in [v1]
  	bool use_codeword_fixup;
  };
  
-@@ -613,19 +599,18 @@ static void clear_bam_transaction(struct
+@@ -613,19 +599,11 @@ static void clear_bam_transaction(struct qcom_nand_controller *nandc)
  {
  	struct bam_transaction *bam_txn = nandc->bam_txn;
  
@@ -178,20 +104,21 @@ Change in [v1]
 +	if (!nandc->props->supports_bam)
  		return;
  
- 	bam_txn->bam_ce_pos = 0;
- 	bam_txn->bam_ce_start = 0;
- 	bam_txn->cmd_sgl_pos = 0;
- 	bam_txn->cmd_sgl_start = 0;
- 	bam_txn->tx_sgl_pos = 0;
- 	bam_txn->tx_sgl_start = 0;
- 	bam_txn->rx_sgl_pos = 0;
- 	bam_txn->rx_sgl_start = 0;
+-	bam_txn->bam_ce_pos = 0;
+-	bam_txn->bam_ce_start = 0;
+-	bam_txn->cmd_sgl_pos = 0;
+-	bam_txn->cmd_sgl_start = 0;
+-	bam_txn->tx_sgl_pos = 0;
+-	bam_txn->tx_sgl_start = 0;
+-	bam_txn->rx_sgl_pos = 0;
+-	bam_txn->rx_sgl_start = 0;
++	memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8);
  	bam_txn->last_data_desc = NULL;
 -	bam_txn->wait_second_completion = false;
  
  	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
  		      QPIC_PER_CW_CMD_SGL);
-@@ -640,17 +618,7 @@ static void qpic_bam_dma_done(void *data
+@@ -640,46 +618,35 @@ static void qpic_bam_dma_done(void *data)
  {
  	struct bam_transaction *bam_txn = data;
  
@@ -209,21 +136,44 @@ Change in [v1]
 +	complete(&bam_txn->txn_done);
  }
  
- static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
-@@ -676,10 +644,9 @@ static inline void nandc_write(struct qc
+-static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
++static struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
+ {
+ 	return container_of(chip, struct qcom_nand_host, chip);
+ }
+ 
+-static inline struct qcom_nand_controller *
++static struct qcom_nand_controller *
+ get_qcom_nand_controller(struct nand_chip *chip)
+ {
+ 	return container_of(chip->controller, struct qcom_nand_controller,
+ 			    controller);
+ }
+ 
+-static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
++static u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
+ {
+ 	return ioread32(nandc->base + offset);
+ }
+ 
+-static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
+-			       u32 val)
++static void nandc_write(struct qcom_nand_controller *nandc, int offset,
++			u32 val)
+ {
  	iowrite32(val, nandc->base + offset);
  }
  
 -static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
 -					  bool is_cpu)
-+static inline void nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
++static void nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
  {
 -	if (!nandc->props->is_bam)
 +	if (!nandc->props->supports_bam)
  		return;
  
  	if (is_cpu)
-@@ -694,93 +661,90 @@ static inline void nandc_read_buffer_syn
+@@ -694,93 +661,90 @@ static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
  					   DMA_FROM_DEVICE);
  }
  
@@ -279,27 +229,14 @@ Change in [v1]
 -	default:
 -		return NULL;
 -	}
--}
--
--static void nandc_set_reg(struct nand_chip *chip, int offset,
--			  u32 val)
--{
--	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
--	struct nandc_regs *regs = nandc->regs;
--	__le32 *reg;
--
--	reg = offset_to_nandc_reg(regs, offset);
--
--	if (reg)
--		*reg = cpu_to_le32(val);
--}
--
- /* Helper to check the code word, whether it is last cw or not */
- static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
- {
- 	return cw == (ecc->steps - 1);
++/* Helper to check whether this is the last CW or not */
++static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
++{
++	return cw == (ecc->steps - 1);
  }
  
+-static void nandc_set_reg(struct nand_chip *chip, int offset,
+-			  u32 val)
 +/**
 + * nandc_set_read_loc_first() - to set read location first register
 + * @chip:		NAND Private Flash Chip Data
@@ -313,8 +250,12 @@ Change in [v1]
 +static void nandc_set_read_loc_first(struct nand_chip *chip,
 +				     int reg_base, u32 cw_offset,
 +				     u32 read_size, u32 is_last_read_loc)
-+{
-+	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+ {
+ 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+-	struct nandc_regs *regs = nandc->regs;
+-	__le32 *reg;
+-
+-	reg = offset_to_nandc_reg(regs, offset);
 +	__le32 locreg_val;
 +	u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
 +		  ((read_size) << READ_LOCATION_SIZE) |
@@ -351,9 +292,16 @@ Change in [v1]
 +	u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
 +		  ((read_size) << READ_LOCATION_SIZE) |
 +		  ((is_last_read_loc) << READ_LOCATION_LAST));
-+
+ 
+-	if (reg)
+-		*reg = cpu_to_le32(val);
+-}
 +	locreg_val = cpu_to_le32(val);
-+
+ 
+-/* Helper to check the code word, whether it is last cw or not */
+-static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
+-{
+-	return cw == (ecc->steps - 1);
 +	if (reg_base == NAND_READ_LOCATION_LAST_CW_0)
 +		nandc->regs->read_location_last0 = locreg_val;
 +	else if (reg_base == NAND_READ_LOCATION_LAST_CW_1)
@@ -362,8 +310,8 @@ Change in [v1]
 +		nandc->regs->read_location_last2 = locreg_val;
 +	else if (reg_base == NAND_READ_LOCATION_LAST_CW_3)
 +		nandc->regs->read_location_last3 = locreg_val;
-+}
-+
+ }
+ 
  /* helper to configure location register values */
  static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg,
 -			       int cw_offset, int read_size, int is_last_read_loc)
@@ -384,7 +332,7 @@ Change in [v1]
  		return nandc_set_read_loc_last(chip, reg_base, cw_offset,
  				read_size, is_last_read_loc);
  	else
-@@ -792,12 +756,13 @@ static void nandc_set_read_loc(struct na
+@@ -792,12 +756,13 @@ static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg,
  static void set_address(struct qcom_nand_host *host, u16 column, int page)
  {
  	struct nand_chip *chip = &host->chip;
@@ -400,7 +348,7 @@ Change in [v1]
  }
  
  /*
-@@ -811,41 +776,43 @@ static void set_address(struct qcom_nand
+@@ -811,41 +776,43 @@ static void set_address(struct qcom_nand_host *host, u16 column, int page)
  static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, int cw)
  {
  	struct nand_chip *chip = &host->chip;
@@ -465,7 +413,7 @@ Change in [v1]
  
  	if (read)
  		nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ?
-@@ -1121,7 +1088,7 @@ static int read_reg_dma(struct qcom_nand
+@@ -1121,7 +1088,7 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
  	if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
  		first = dev_cmd_reg_addr(nandc, first);
  
@@ -474,11 +422,11 @@ Change in [v1]
  		return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
  					     num_regs, flags);
  
-@@ -1136,25 +1103,16 @@ static int read_reg_dma(struct qcom_nand
+@@ -1136,25 +1103,16 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
   * write_reg_dma:	prepares a descriptor to write a given number of
   *			contiguous registers
   *
-+ * @vaddr:		contnigeous memory from where register value will
++ * @vaddr:		contiguous memory from where register value will
 + *			be written
   * @first:		offset of the first register in the contiguous block
   * @num_regs:		number of registers to write
@@ -504,7 +452,7 @@ Change in [v1]
  
  	if (first == NAND_EXEC_CMD)
  		flags |= NAND_BAM_NWD;
-@@ -1165,7 +1123,7 @@ static int write_reg_dma(struct qcom_nan
+@@ -1165,7 +1123,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
  	if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
  		first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
  
@@ -513,7 +461,7 @@ Change in [v1]
  		return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
  					     num_regs, flags);
  
-@@ -1188,7 +1146,7 @@ static int write_reg_dma(struct qcom_nan
+@@ -1188,7 +1146,7 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
  static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
  			 const u8 *vaddr, int size, unsigned int flags)
  {
@@ -522,7 +470,7 @@ Change in [v1]
  		return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
  
  	return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
-@@ -1206,7 +1164,7 @@ static int read_data_dma(struct qcom_nan
+@@ -1206,7 +1164,7 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
  static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
  			  const u8 *vaddr, int size, unsigned int flags)
  {
@@ -531,7 +479,7 @@ Change in [v1]
  		return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
  
  	return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
-@@ -1220,13 +1178,14 @@ static void config_nand_page_read(struct
+@@ -1220,13 +1178,14 @@ static void config_nand_page_read(struct nand_chip *chip)
  {
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  
@@ -553,7 +501,7 @@ Change in [v1]
  }
  
  /*
-@@ -1239,16 +1198,16 @@ config_nand_cw_read(struct nand_chip *ch
+@@ -1239,16 +1198,16 @@ config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  	struct nand_ecc_ctrl *ecc = &chip->ecc;
  
@@ -577,7 +525,7 @@ Change in [v1]
  
  	if (use_ecc) {
  		read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0);
-@@ -1279,10 +1238,10 @@ static void config_nand_page_write(struc
+@@ -1279,10 +1238,10 @@ static void config_nand_page_write(struct nand_chip *chip)
  {
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  
@@ -592,7 +540,7 @@ Change in [v1]
  			      NAND_BAM_NEXT_SGL);
  }
  
-@@ -1294,13 +1253,13 @@ static void config_nand_cw_write(struct
+@@ -1294,13 +1253,13 @@ static void config_nand_cw_write(struct nand_chip *chip)
  {
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  
@@ -610,7 +558,7 @@ Change in [v1]
  }
  
  /* helpers to submit/free our list of dma descriptors */
-@@ -1311,7 +1270,7 @@ static int submit_descs(struct qcom_nand
+@@ -1311,7 +1270,7 @@ static int submit_descs(struct qcom_nand_controller *nandc)
  	struct bam_transaction *bam_txn = nandc->bam_txn;
  	int ret = 0;
  
@@ -619,7 +567,7 @@ Change in [v1]
  		if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
  			ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
  			if (ret)
-@@ -1336,14 +1295,9 @@ static int submit_descs(struct qcom_nand
+@@ -1336,14 +1295,9 @@ static int submit_descs(struct qcom_nand_controller *nandc)
  	list_for_each_entry(desc, &nandc->desc_list, node)
  		cookie = dmaengine_submit(desc->dma_desc);
  
@@ -635,7 +583,7 @@ Change in [v1]
  
  		dma_async_issue_pending(nandc->tx_chan);
  		dma_async_issue_pending(nandc->rx_chan);
-@@ -1365,7 +1319,7 @@ err_unmap_free_desc:
+@@ -1365,7 +1319,7 @@ static int submit_descs(struct qcom_nand_controller *nandc)
  	list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
  		list_del(&desc->node);
  
@@ -644,7 +592,7 @@ Change in [v1]
  			dma_unmap_sg(nandc->dev, desc->bam_sgl,
  				     desc->sgl_cnt, desc->dir);
  		else
-@@ -1382,7 +1336,7 @@ err_unmap_free_desc:
+@@ -1382,7 +1336,7 @@ static int submit_descs(struct qcom_nand_controller *nandc)
  static void clear_read_regs(struct qcom_nand_controller *nandc)
  {
  	nandc->reg_read_pos = 0;
@@ -653,7 +601,7 @@ Change in [v1]
  }
  
  /*
-@@ -1446,7 +1400,7 @@ static int check_flash_errors(struct qco
+@@ -1446,7 +1400,7 @@ static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt)
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  	int i;
  
@@ -662,7 +610,7 @@ Change in [v1]
  
  	for (i = 0; i < cw_cnt; i++) {
  		u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
-@@ -1476,7 +1430,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *
+@@ -1476,7 +1430,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
  	clear_read_regs(nandc);
  	host->use_ecc = false;
  
@@ -671,7 +619,7 @@ Change in [v1]
  		raw_cw = ecc->steps - 1;
  
  	clear_bam_transaction(nandc);
-@@ -1497,7 +1451,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *
+@@ -1497,7 +1451,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
  		oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
  	}
  
@@ -680,7 +628,7 @@ Change in [v1]
  		nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
  		read_loc += data_size1;
  
-@@ -1621,7 +1575,7 @@ static int parse_read_errors(struct qcom
+@@ -1621,7 +1575,7 @@ static int parse_read_errors(struct qcom_nand_host *host, u8 *data_buf,
  	u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
  
  	buf = (struct read_stats *)nandc->reg_read_buf;
@@ -689,7 +637,7 @@ Change in [v1]
  
  	for (i = 0; i < ecc->steps; i++, buf++) {
  		u32 flash, buffer, erased_cw;
-@@ -1734,7 +1688,7 @@ static int read_page_ecc(struct qcom_nan
+@@ -1734,7 +1688,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
  			oob_size = host->ecc_bytes_hw + host->spare_bytes;
  		}
  
@@ -698,7 +646,7 @@ Change in [v1]
  			if (data_buf && oob_buf) {
  				nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
  				nandc_set_read_loc(chip, i, 1, data_size,
-@@ -2455,14 +2409,14 @@ static int qcom_nand_attach_chip(struct
+@@ -2455,14 +2409,14 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
  
  	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
  	/* Free the initially allocated BAM transaction for reading the ONFI params */
@@ -715,7 +663,7 @@ Change in [v1]
  		nandc->bam_txn = alloc_bam_transaction(nandc);
  		if (!nandc->bam_txn) {
  			dev_err(nandc->dev,
-@@ -2522,7 +2476,7 @@ static int qcom_nand_attach_chip(struct
+@@ -2522,7 +2476,7 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
  				| ecc_mode << ECC_MODE
  				| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
  
@@ -724,7 +672,7 @@ Change in [v1]
  		host->ecc_buf_cfg = 0x203 << NUM_STEPS;
  
  	host->clrflashstatus = FS_READY_BSY_N;
-@@ -2556,7 +2510,7 @@ static int qcom_op_cmd_mapping(struct na
+@@ -2556,7 +2510,7 @@ static int qcom_op_cmd_mapping(struct nand_chip *chip, u8 opcode,
  		cmd = OP_FETCH_ID;
  		break;
  	case NAND_CMD_PARAM:
@@ -733,7 +681,7 @@ Change in [v1]
  			cmd = OP_PAGE_READ_ONFI_READ;
  		else
  			cmd = OP_PAGE_READ;
-@@ -2609,7 +2563,7 @@ static int qcom_parse_instructions(struc
+@@ -2609,7 +2563,7 @@ static int qcom_parse_instructions(struct nand_chip *chip,
  			if (ret < 0)
  				return ret;
  
@@ -742,7 +690,7 @@ Change in [v1]
  			q_op->rdy_delay_ns = instr->delay_ns;
  			break;
  
-@@ -2619,10 +2573,10 @@ static int qcom_parse_instructions(struc
+@@ -2619,10 +2573,10 @@ static int qcom_parse_instructions(struct nand_chip *chip,
  			addrs = &instr->ctx.addr.addrs[offset];
  
  			for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
@@ -755,7 +703,7 @@ Change in [v1]
  
  			q_op->rdy_delay_ns = instr->delay_ns;
  			break;
-@@ -2663,7 +2617,7 @@ static int qcom_wait_rdy_poll(struct nan
+@@ -2663,7 +2617,7 @@ static int qcom_wait_rdy_poll(struct nand_chip *chip, unsigned int time_ms)
  	unsigned long start = jiffies + msecs_to_jiffies(time_ms);
  	u32 flash;
  
@@ -764,7 +712,7 @@ Change in [v1]
  
  	do {
  		flash = le32_to_cpu(nandc->reg_read_buf[0]);
-@@ -2706,11 +2660,11 @@ static int qcom_read_status_exec(struct
+@@ -2706,11 +2660,11 @@ static int qcom_read_status_exec(struct nand_chip *chip,
  	clear_read_regs(nandc);
  	clear_bam_transaction(nandc);
  
@@ -780,7 +728,7 @@ Change in [v1]
  	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
  
  	ret = submit_descs(nandc);
-@@ -2719,7 +2673,7 @@ static int qcom_read_status_exec(struct
+@@ -2719,7 +2673,7 @@ static int qcom_read_status_exec(struct nand_chip *chip,
  		goto err_out;
  	}
  
@@ -789,7 +737,7 @@ Change in [v1]
  
  	for (i = 0; i < num_cw; i++) {
  		flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
-@@ -2763,16 +2717,14 @@ static int qcom_read_id_type_exec(struct
+@@ -2763,16 +2717,14 @@ static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subo
  	clear_read_regs(nandc);
  	clear_bam_transaction(nandc);
  
@@ -798,14 +746,14 @@ Change in [v1]
 -	nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg);
 -	nandc_set_reg(chip, NAND_FLASH_CHIP_SELECT,
 -		      nandc->props->is_bam ? 0 : DM_EN);
+-
+-	nandc_set_reg(chip, NAND_EXEC_CMD, 1);
 +	nandc->regs->cmd = q_op.cmd_reg;
 +	nandc->regs->addr0 = q_op.addr1_reg;
 +	nandc->regs->addr1 = q_op.addr2_reg;
 +	nandc->regs->chip_sel = cpu_to_le32(nandc->props->supports_bam ? 0 : DM_EN);
 +	nandc->regs->exec = cpu_to_le32(1);
  
--	nandc_set_reg(chip, NAND_EXEC_CMD, 1);
--
 -	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
 -	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 +	write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
@@ -813,7 +761,7 @@ Change in [v1]
  
  	read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
  
-@@ -2786,7 +2738,7 @@ static int qcom_read_id_type_exec(struct
+@@ -2786,7 +2738,7 @@ static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subo
  	op_id = q_op.data_instr_idx;
  	len = nand_subop_get_data_len(subop, op_id);
  
@@ -822,7 +770,7 @@ Change in [v1]
  	memcpy(instr->ctx.data.buf.in, nandc->reg_read_buf, len);
  
  err_out:
-@@ -2807,15 +2759,14 @@ static int qcom_misc_cmd_type_exec(struc
+@@ -2807,15 +2759,14 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub
  
  	if (q_op.flag == OP_PROGRAM_PAGE) {
  		goto wait_rdy;
@@ -845,7 +793,7 @@ Change in [v1]
  		return 0;
  	}
  
-@@ -2826,14 +2777,14 @@ static int qcom_misc_cmd_type_exec(struc
+@@ -2826,14 +2777,14 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub
  	clear_read_regs(nandc);
  	clear_bam_transaction(nandc);
  
@@ -866,7 +814,7 @@ Change in [v1]
  	read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
  
  	ret = submit_descs(nandc);
-@@ -2864,7 +2815,7 @@ static int qcom_param_page_type_exec(str
+@@ -2864,7 +2815,7 @@ static int qcom_param_page_type_exec(struct nand_chip *chip,  const struct nand_
  	if (ret)
  		return ret;
  
@@ -875,28 +823,12 @@ Change in [v1]
  
  	nandc->buf_count = 0;
  	nandc->buf_start = 0;
-@@ -2872,38 +2823,38 @@ static int qcom_param_page_type_exec(str
+@@ -2872,38 +2823,38 @@ static int qcom_param_page_type_exec(struct nand_chip *chip,  const struct nand_
  	clear_read_regs(nandc);
  	clear_bam_transaction(nandc);
  
 -	nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);
-+	nandc->regs->cmd = q_op.cmd_reg;
-+	nandc->regs->addr0 = 0;
-+	nandc->regs->addr1 = 0;
-+
-+	nandc->regs->cfg0 = cpu_to_le32(0 << CW_PER_PAGE
-+			    | 512 << UD_SIZE_BYTES
-+			    | 5 << NUM_ADDR_CYCLES
-+			    | 0 << SPARE_SIZE_BYTES);
-+
-+	nandc->regs->cfg1 = cpu_to_le32(7 << NAND_RECOVERY_CYCLES
-+			    | 0 << CS_ACTIVE_BSY
-+			    | 17 << BAD_BLOCK_BYTE_NUM
-+			    | 1 << BAD_BLOCK_IN_SPARE_AREA
-+			    | 2 << WR_RD_BSY_GAP
-+			    | 0 << WIDE_FLASH
-+			    | 1 << DEV0_CFG1_ECC_DISABLE);
- 
+-
 -	nandc_set_reg(chip, NAND_ADDR0, 0);
 -	nandc_set_reg(chip, NAND_ADDR1, 0);
 -	nandc_set_reg(chip, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
@@ -912,6 +844,23 @@ Change in [v1]
 -					| 1 << DEV0_CFG1_ECC_DISABLE);
 -	if (!nandc->props->qpic_v2)
 -		nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
++	nandc->regs->cmd = q_op.cmd_reg;
++	nandc->regs->addr0 = 0;
++	nandc->regs->addr1 = 0;
++
++	nandc->regs->cfg0 = cpu_to_le32(0 << CW_PER_PAGE |
++					512 << UD_SIZE_BYTES |
++					5 << NUM_ADDR_CYCLES |
++					0 << SPARE_SIZE_BYTES);
++
++	nandc->regs->cfg1 = cpu_to_le32(7 << NAND_RECOVERY_CYCLES |
++					0 << CS_ACTIVE_BSY |
++					17 << BAD_BLOCK_BYTE_NUM |
++					1 << BAD_BLOCK_IN_SPARE_AREA |
++					2 << WR_RD_BSY_GAP |
++					0 << WIDE_FLASH |
++					1 << DEV0_CFG1_ECC_DISABLE);
++
 +	if (!nandc->props->qpic_version2)
 +		nandc->regs->ecc_buf_cfg = cpu_to_le32(1 << ECC_CFG_ECC_DISABLE);
  
@@ -929,19 +878,18 @@ Change in [v1]
  	}
  
 -	nandc_set_reg(chip, NAND_EXEC_CMD, 1);
--
++	nandc->regs->exec = cpu_to_le32(1);
+ 
 -	if (!nandc->props->qpic_v2) {
 -		nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
 -		nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
-+	nandc->regs->exec = cpu_to_le32(1);
-+
 +	if (!nandc->props->qpic_version2) {
 +		nandc->regs->orig_cmd1 = cpu_to_le32(nandc->cmd1);
 +		nandc->regs->orig_vld = cpu_to_le32(nandc->vld);
  	}
  
  	instr = q_op.data_instr;
-@@ -2912,9 +2863,9 @@ static int qcom_param_page_type_exec(str
+@@ -2912,9 +2863,9 @@ static int qcom_param_page_type_exec(struct nand_chip *chip,  const struct nand_
  
  	nandc_set_read_loc(chip, 0, 0, 0, len, 1);
  
@@ -954,7 +902,7 @@ Change in [v1]
  	}
  
  	nandc->buf_count = len;
-@@ -2926,9 +2877,10 @@ static int qcom_param_page_type_exec(str
+@@ -2926,9 +2877,10 @@ static int qcom_param_page_type_exec(struct nand_chip *chip,  const struct nand_
  		      nandc->buf_count, 0);
  
  	/* restore CMD1 and VLD regs */
@@ -968,7 +916,7 @@ Change in [v1]
  	}
  
  	ret = submit_descs(nandc);
-@@ -3017,7 +2969,7 @@ static const struct nand_controller_ops
+@@ -3017,7 +2969,7 @@ static const struct nand_controller_ops qcom_nandc_ops = {
  
  static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
  {
@@ -977,7 +925,7 @@ Change in [v1]
  		if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
  			dma_unmap_single(nandc->dev, nandc->reg_read_dma,
  					 MAX_REG_RD *
-@@ -3070,7 +3022,7 @@ static int qcom_nandc_alloc(struct qcom_
+@@ -3070,7 +3022,7 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
  	if (!nandc->reg_read_buf)
  		return -ENOMEM;
  
@@ -986,7 +934,7 @@ Change in [v1]
  		nandc->reg_read_dma =
  			dma_map_single(nandc->dev, nandc->reg_read_buf,
  				       MAX_REG_RD *
-@@ -3151,15 +3103,15 @@ static int qcom_nandc_setup(struct qcom_
+@@ -3151,15 +3103,15 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
  	u32 nand_ctrl;
  
  	/* kill onenand */
@@ -1005,7 +953,7 @@ Change in [v1]
  		nand_ctrl = nandc_read(nandc, NAND_CTRL);
  
  		/*
-@@ -3176,7 +3128,7 @@ static int qcom_nandc_setup(struct qcom_
+@@ -3176,7 +3128,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
  	}
  
  	/* save the original values of these registers */
@@ -1014,7 +962,7 @@ Change in [v1]
  		nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1));
  		nandc->vld = NAND_DEV_CMD_VLD_VAL;
  	}
-@@ -3349,7 +3301,7 @@ static int qcom_nandc_parse_dt(struct pl
+@@ -3349,7 +3301,7 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
  	struct device_node *np = nandc->dev->of_node;
  	int ret;
  
@@ -1023,7 +971,7 @@ Change in [v1]
  		ret = of_property_read_u32(np, "qcom,cmd-crci",
  					   &nandc->cmd_crci);
  		if (ret) {
-@@ -3474,30 +3426,30 @@ static void qcom_nandc_remove(struct pla
+@@ -3474,30 +3426,30 @@ static void qcom_nandc_remove(struct platform_device *pdev)
  
  static const struct qcom_nandc_props ipq806x_nandc_props = {
  	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
@@ -1062,3 +1010,6 @@ Change in [v1]
  	.dev_cmd_reg_start = 0x7000,
  };
  
+-- 
+2.47.1
+

target/linux/qualcommbe/patches-6.6/100-03-mtd-rawnand-qcom-Add-qcom-prefix-to-common-api.patch → target/linux/qualcommbe/patches-6.6/016-02-v6.14-mtd-rawnand-qcom-Add-qcom-prefix-to-common-api.patch

@@ -1,57 +1,20 @@
-From dde50ed4a7bdb79b4bb408781d3e4846d4c49f0a Mon Sep 17 00:00:00 2001
+From 1d479f5b345e0c3650fec4dddeef9fc6fab30c8b Mon Sep 17 00:00:00 2001
 From: Md Sadre Alam <[email protected]>
-Date: Wed, 11 Sep 2024 11:13:42 +0530
-Subject: [PATCH v10 3/8] mtd: rawnand: qcom: Add qcom prefix to common api
+Date: Wed, 20 Nov 2024 14:45:01 +0530
+Subject: [PATCH 2/4] mtd: rawnand: qcom: Add qcom prefix to common api
 
 Add qcom prefix to all the api which will be commonly
 used by spi nand driver and raw nand driver.
 
+Reviewed-by: Konrad Dybcio <[email protected]>
 Signed-off-by: Md Sadre Alam <[email protected]>
+Signed-off-by: Miquel Raynal <[email protected]>
 ---
-
-Change in [v10]
-
-* No change
-
-Change in [v9]
-
-* No change
-
-Change in [v8]
-
-* No change
-
-Change in [v7]
-
-* No change
-
-Change in [v6]
-
-* No change
-
-Change in [v5]
-
-* Add qcom_ prefix to all common API.
-
-Change in [v4]
-
-* This patch was not included in [v4]
-
-Change in [v3]
-
-* This patch was not included in [v3]
-
-Change in [v2]
-
-* This patch was not included in [v2]
-
-Change in [v1]
-
-* This patch was not included in [v1]
-
  drivers/mtd/nand/raw/qcom_nandc.c | 320 +++++++++++++++---------------
  1 file changed, 160 insertions(+), 160 deletions(-)
 
+diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
+index 9ae8c9f2ab55..6da5d23d2c8b 100644
 --- a/drivers/mtd/nand/raw/qcom_nandc.c
 +++ b/drivers/mtd/nand/raw/qcom_nandc.c
 @@ -53,7 +53,7 @@
@@ -81,7 +44,7 @@ Change in [v1]
  {
  	struct bam_transaction *bam_txn = nandc->bam_txn;
  
-@@ -559,7 +559,7 @@ static void free_bam_transaction(struct
+@@ -559,7 +559,7 @@ static void free_bam_transaction(struct qcom_nand_controller *nandc)
  
  /* Allocates and Initializes the BAM transaction */
  static struct bam_transaction *
@@ -90,7 +53,7 @@ Change in [v1]
  {
  	struct bam_transaction *bam_txn;
  	size_t bam_txn_size;
-@@ -595,7 +595,7 @@ alloc_bam_transaction(struct qcom_nand_c
+@@ -595,7 +595,7 @@ alloc_bam_transaction(struct qcom_nand_controller *nandc)
  }
  
  /* Clears the BAM transaction indexes */
@@ -99,7 +62,7 @@ Change in [v1]
  {
  	struct bam_transaction *bam_txn = nandc->bam_txn;
  
-@@ -614,7 +614,7 @@ static void clear_bam_transaction(struct
+@@ -614,7 +614,7 @@ static void clear_bam_transaction(struct qcom_nand_controller *nandc)
  }
  
  /* Callback for DMA descriptor completion */
@@ -108,16 +71,16 @@ Change in [v1]
  {
  	struct bam_transaction *bam_txn = data;
  
-@@ -644,7 +644,7 @@ static inline void nandc_write(struct qc
+@@ -644,7 +644,7 @@ static void nandc_write(struct qcom_nand_controller *nandc, int offset,
  	iowrite32(val, nandc->base + offset);
  }
  
--static inline void nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
-+static inline void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
+-static void nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
++static void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
  {
  	if (!nandc->props->supports_bam)
  		return;
-@@ -824,9 +824,9 @@ static void update_rw_regs(struct qcom_n
+@@ -824,9 +824,9 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
   * for BAM. This descriptor will be added in the NAND DMA descriptor queue
   * which will be submitted to DMA engine.
   */
@@ -130,7 +93,7 @@ Change in [v1]
  {
  	struct desc_info *desc;
  	struct scatterlist *sgl;
-@@ -903,9 +903,9 @@ static int prepare_bam_async_desc(struct
+@@ -903,9 +903,9 @@ static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
   * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
   * after the current command element.
   */
@@ -143,7 +106,7 @@ Change in [v1]
  {
  	int bam_ce_size;
  	int i, ret;
-@@ -943,9 +943,9 @@ static int prep_bam_dma_desc_cmd(struct
+@@ -943,9 +943,9 @@ static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
  		bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
  
  		if (flags & NAND_BAM_NWD) {
@@ -156,7 +119,7 @@ Change in [v1]
  			if (ret)
  				return ret;
  		}
-@@ -958,9 +958,8 @@ static int prep_bam_dma_desc_cmd(struct
+@@ -958,9 +958,8 @@ static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
   * Prepares the data descriptor for BAM DMA which will be used for NAND
   * data reads and writes.
   */
@@ -168,7 +131,7 @@ Change in [v1]
  {
  	int ret;
  	struct bam_transaction *bam_txn = nandc->bam_txn;
-@@ -979,8 +978,8 @@ static int prep_bam_dma_desc_data(struct
+@@ -979,8 +978,8 @@ static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
  		 * is not set, form the DMA descriptor
  		 */
  		if (!(flags & NAND_BAM_NO_EOT)) {
@@ -179,7 +142,7 @@ Change in [v1]
  			if (ret)
  				return ret;
  		}
-@@ -989,9 +988,9 @@ static int prep_bam_dma_desc_data(struct
+@@ -989,9 +988,9 @@ static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
  	return 0;
  }
  
@@ -192,7 +155,7 @@ Change in [v1]
  {
  	struct desc_info *desc;
  	struct dma_async_tx_descriptor *dma_desc;
-@@ -1069,15 +1068,15 @@ err:
+@@ -1069,15 +1068,15 @@ static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
  }
  
  /*
@@ -211,7 +174,7 @@ Change in [v1]
  {
  	bool flow_control = false;
  	void *vaddr;
-@@ -1089,18 +1088,18 @@ static int read_reg_dma(struct qcom_nand
+@@ -1089,18 +1088,18 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
  		first = dev_cmd_reg_addr(nandc, first);
  
  	if (nandc->props->supports_bam)
@@ -232,8 +195,8 @@ Change in [v1]
 + * qcom_write_reg_dma:	prepares a descriptor to write a given number of
   *			contiguous registers
   *
-  * @vaddr:		contnigeous memory from where register value will
-@@ -1109,8 +1108,8 @@ static int read_reg_dma(struct qcom_nand
+  * @vaddr:		contiguous memory from where register value will
+@@ -1109,8 +1108,8 @@ static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
   * @num_regs:		number of registers to write
   * @flags:		flags to control DMA descriptor preparation
   */
@@ -244,7 +207,7 @@ Change in [v1]
  {
  	bool flow_control = false;
  
-@@ -1124,18 +1123,18 @@ static int write_reg_dma(struct qcom_nan
+@@ -1124,18 +1123,18 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr,
  		first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
  
  	if (nandc->props->supports_bam)
@@ -266,7 +229,7 @@ Change in [v1]
   *			controller's internal buffer to the buffer 'vaddr'
   *
   * @reg_off:		offset within the controller's data buffer
-@@ -1143,17 +1142,17 @@ static int write_reg_dma(struct qcom_nan
+@@ -1143,17 +1142,17 @@ static int write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr,
   * @size:		DMA transaction size in bytes
   * @flags:		flags to control DMA descriptor preparation
   */
@@ -289,7 +252,7 @@ Change in [v1]
   *			'vaddr' to the controller's internal buffer
   *
   * @reg_off:		offset within the controller's data buffer
-@@ -1161,13 +1160,13 @@ static int read_data_dma(struct qcom_nan
+@@ -1161,13 +1160,13 @@ static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
   * @size:		DMA transaction size in bytes
   * @flags:		flags to control DMA descriptor preparation
   */
@@ -307,7 +270,7 @@ Change in [v1]
  }
  
  /*
-@@ -1178,14 +1177,14 @@ static void config_nand_page_read(struct
+@@ -1178,14 +1177,14 @@ static void config_nand_page_read(struct nand_chip *chip)
  {
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  
@@ -329,7 +292,7 @@ Change in [v1]
  }
  
  /*
-@@ -1204,17 +1203,17 @@ config_nand_cw_read(struct nand_chip *ch
+@@ -1204,17 +1203,17 @@ config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
  		reg = &nandc->regs->read_location_last0;
  
  	if (nandc->props->supports_bam)
@@ -354,7 +317,7 @@ Change in [v1]
  	}
  }
  
-@@ -1238,11 +1237,11 @@ static void config_nand_page_write(struc
+@@ -1238,11 +1237,11 @@ static void config_nand_page_write(struct nand_chip *chip)
  {
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  
@@ -370,7 +333,7 @@ Change in [v1]
  }
  
  /*
-@@ -1253,17 +1252,18 @@ static void config_nand_cw_write(struct
+@@ -1253,17 +1252,18 @@ static void config_nand_cw_write(struct nand_chip *chip)
  {
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  
@@ -395,7 +358,7 @@ Change in [v1]
  {
  	struct desc_info *desc, *n;
  	dma_cookie_t cookie = 0;
-@@ -1272,21 +1272,21 @@ static int submit_descs(struct qcom_nand
+@@ -1272,21 +1272,21 @@ static int submit_descs(struct qcom_nand_controller *nandc)
  
  	if (nandc->props->supports_bam) {
  		if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
@@ -422,7 +385,7 @@ Change in [v1]
  			if (ret)
  				goto err_unmap_free_desc;
  		}
-@@ -1296,7 +1296,7 @@ static int submit_descs(struct qcom_nand
+@@ -1296,7 +1296,7 @@ static int submit_descs(struct qcom_nand_controller *nandc)
  		cookie = dmaengine_submit(desc->dma_desc);
  
  	if (nandc->props->supports_bam) {
@@ -431,7 +394,7 @@ Change in [v1]
  		bam_txn->last_cmd_desc->callback_param = bam_txn;
  
  		dma_async_issue_pending(nandc->tx_chan);
-@@ -1314,7 +1314,7 @@ static int submit_descs(struct qcom_nand
+@@ -1314,7 +1314,7 @@ static int submit_descs(struct qcom_nand_controller *nandc)
  err_unmap_free_desc:
  	/*
  	 * Unmap the dma sg_list and free the desc allocated by both
@@ -440,7 +403,7 @@ Change in [v1]
  	 */
  	list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
  		list_del(&desc->node);
-@@ -1333,10 +1333,10 @@ err_unmap_free_desc:
+@@ -1333,10 +1333,10 @@ static int submit_descs(struct qcom_nand_controller *nandc)
  }
  
  /* reset the register read buffer for next NAND operation */
@@ -453,7 +416,7 @@ Change in [v1]
  }
  
  /*
-@@ -1400,7 +1400,7 @@ static int check_flash_errors(struct qco
+@@ -1400,7 +1400,7 @@ static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt)
  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  	int i;
  
@@ -462,7 +425,7 @@ Change in [v1]
  
  	for (i = 0; i < cw_cnt; i++) {
  		u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
-@@ -1427,13 +1427,13 @@ qcom_nandc_read_cw_raw(struct mtd_info *
+@@ -1427,13 +1427,13 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
  	nand_read_page_op(chip, page, 0, NULL, 0);
  	nandc->buf_count = 0;
  	nandc->buf_start = 0;
@@ -478,7 +441,7 @@ Change in [v1]
  	set_address(host, host->cw_size * cw, page);
  	update_rw_regs(host, 1, true, raw_cw);
  	config_nand_page_read(chip);
-@@ -1466,18 +1466,18 @@ qcom_nandc_read_cw_raw(struct mtd_info *
+@@ -1466,18 +1466,18 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
  
  	config_nand_cw_read(chip, false, raw_cw);
  
@@ -502,7 +465,7 @@ Change in [v1]
  	if (ret) {
  		dev_err(nandc->dev, "failure to read raw cw %d\n", cw);
  		return ret;
-@@ -1575,7 +1575,7 @@ static int parse_read_errors(struct qcom
+@@ -1575,7 +1575,7 @@ static int parse_read_errors(struct qcom_nand_host *host, u8 *data_buf,
  	u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
  
  	buf = (struct read_stats *)nandc->reg_read_buf;
@@ -511,7 +474,7 @@ Change in [v1]
  
  	for (i = 0; i < ecc->steps; i++, buf++) {
  		u32 flash, buffer, erased_cw;
-@@ -1704,8 +1704,8 @@ static int read_page_ecc(struct qcom_nan
+@@ -1704,8 +1704,8 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
  		config_nand_cw_read(chip, true, i);
  
  		if (data_buf)
@@ -522,7 +485,7 @@ Change in [v1]
  
  		/*
  		 * when ecc is enabled, the controller doesn't read the real
-@@ -1720,8 +1720,8 @@ static int read_page_ecc(struct qcom_nan
+@@ -1720,8 +1720,8 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
  			for (j = 0; j < host->bbm_size; j++)
  				*oob_buf++ = 0xff;
  
@@ -533,7 +496,7 @@ Change in [v1]
  		}
  
  		if (data_buf)
-@@ -1730,7 +1730,7 @@ static int read_page_ecc(struct qcom_nan
+@@ -1730,7 +1730,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
  			oob_buf += oob_size;
  	}
  
@@ -542,7 +505,7 @@ Change in [v1]
  	if (ret) {
  		dev_err(nandc->dev, "failure to read page/oob\n");
  		return ret;
-@@ -1751,7 +1751,7 @@ static int copy_last_cw(struct qcom_nand
+@@ -1751,7 +1751,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
  	int size;
  	int ret;
  
@@ -551,7 +514,7 @@ Change in [v1]
  
  	size = host->use_ecc ? host->cw_data : host->cw_size;
  
-@@ -1763,9 +1763,9 @@ static int copy_last_cw(struct qcom_nand
+@@ -1763,9 +1763,9 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
  
  	config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);
  
@@ -563,7 +526,7 @@ Change in [v1]
  	if (ret)
  		dev_err(nandc->dev, "failed to copy last codeword\n");
  
-@@ -1851,14 +1851,14 @@ static int qcom_nandc_read_page(struct n
+@@ -1851,14 +1851,14 @@ static int qcom_nandc_read_page(struct nand_chip *chip, u8 *buf,
  	nandc->buf_count = 0;
  	nandc->buf_start = 0;
  	host->use_ecc = true;
@@ -580,7 +543,7 @@ Change in [v1]
  
  	return read_page_ecc(host, data_buf, oob_buf, page);
  }
-@@ -1899,8 +1899,8 @@ static int qcom_nandc_read_oob(struct na
+@@ -1899,8 +1899,8 @@ static int qcom_nandc_read_oob(struct nand_chip *chip, int page)
  	if (host->nr_boot_partitions)
  		qcom_nandc_codeword_fixup(host, page);
  
@@ -591,7 +554,7 @@ Change in [v1]
  
  	host->use_ecc = true;
  	set_address(host, 0, page);
-@@ -1927,8 +1927,8 @@ static int qcom_nandc_write_page(struct
+@@ -1927,8 +1927,8 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const u8 *buf,
  	set_address(host, 0, page);
  	nandc->buf_count = 0;
  	nandc->buf_start = 0;
@@ -602,7 +565,7 @@ Change in [v1]
  
  	data_buf = (u8 *)buf;
  	oob_buf = chip->oob_poi;
-@@ -1949,8 +1949,8 @@ static int qcom_nandc_write_page(struct
+@@ -1949,8 +1949,8 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const u8 *buf,
  			oob_size = ecc->bytes;
  		}
  
@@ -613,7 +576,7 @@ Change in [v1]
  
  		/*
  		 * when ECC is enabled, we don't really need to write anything
-@@ -1962,8 +1962,8 @@ static int qcom_nandc_write_page(struct
+@@ -1962,8 +1962,8 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const u8 *buf,
  		if (qcom_nandc_is_last_cw(ecc, i)) {
  			oob_buf += host->bbm_size;
  
@@ -624,7 +587,7 @@ Change in [v1]
  		}
  
  		config_nand_cw_write(chip);
-@@ -1972,7 +1972,7 @@ static int qcom_nandc_write_page(struct
+@@ -1972,7 +1972,7 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const u8 *buf,
  		oob_buf += oob_size;
  	}
  
@@ -633,7 +596,7 @@ Change in [v1]
  	if (ret) {
  		dev_err(nandc->dev, "failure to write page\n");
  		return ret;
-@@ -1997,8 +1997,8 @@ static int qcom_nandc_write_page_raw(str
+@@ -1997,8 +1997,8 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip,
  		qcom_nandc_codeword_fixup(host, page);
  
  	nand_prog_page_begin_op(chip, page, 0, NULL, 0);
@@ -644,7 +607,7 @@ Change in [v1]
  
  	data_buf = (u8 *)buf;
  	oob_buf = chip->oob_poi;
-@@ -2024,28 +2024,28 @@ static int qcom_nandc_write_page_raw(str
+@@ -2024,28 +2024,28 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip,
  			oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
  		}
  
@@ -681,7 +644,7 @@ Change in [v1]
  	if (ret) {
  		dev_err(nandc->dev, "failure to write raw page\n");
  		return ret;
-@@ -2075,7 +2075,7 @@ static int qcom_nandc_write_oob(struct n
+@@ -2075,7 +2075,7 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page)
  		qcom_nandc_codeword_fixup(host, page);
  
  	host->use_ecc = true;
@@ -690,7 +653,7 @@ Change in [v1]
  
  	/* calculate the data and oob size for the last codeword/step */
  	data_size = ecc->size - ((ecc->steps - 1) << 2);
-@@ -2090,11 +2090,11 @@ static int qcom_nandc_write_oob(struct n
+@@ -2090,11 +2090,11 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page)
  	update_rw_regs(host, 1, false, 0);
  
  	config_nand_page_write(chip);
@@ -705,7 +668,7 @@ Change in [v1]
  	if (ret) {
  		dev_err(nandc->dev, "failure to write oob\n");
  		return ret;
-@@ -2121,7 +2121,7 @@ static int qcom_nandc_block_bad(struct n
+@@ -2121,7 +2121,7 @@ static int qcom_nandc_block_bad(struct nand_chip *chip, loff_t ofs)
  	 */
  	host->use_ecc = false;
  
@@ -714,7 +677,7 @@ Change in [v1]
  	ret = copy_last_cw(host, page);
  	if (ret)
  		goto err;
-@@ -2148,8 +2148,8 @@ static int qcom_nandc_block_markbad(stru
+@@ -2148,8 +2148,8 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs)
  	struct nand_ecc_ctrl *ecc = &chip->ecc;
  	int page, ret;
  
@@ -725,7 +688,7 @@ Change in [v1]
  
  	/*
  	 * to mark the BBM as bad, we flash the entire last codeword with 0s.
-@@ -2166,11 +2166,11 @@ static int qcom_nandc_block_markbad(stru
+@@ -2166,11 +2166,11 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs)
  	update_rw_regs(host, 1, false, ecc->steps - 1);
  
  	config_nand_page_write(chip);
@@ -740,7 +703,7 @@ Change in [v1]
  	if (ret) {
  		dev_err(nandc->dev, "failure to update BBM\n");
  		return ret;
-@@ -2410,14 +2410,14 @@ static int qcom_nand_attach_chip(struct
+@@ -2410,14 +2410,14 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
  	mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops);
  	/* Free the initially allocated BAM transaction for reading the ONFI params */
  	if (nandc->props->supports_bam)
@@ -757,7 +720,7 @@ Change in [v1]
  		if (!nandc->bam_txn) {
  			dev_err(nandc->dev,
  				"failed to allocate bam transaction\n");
-@@ -2617,7 +2617,7 @@ static int qcom_wait_rdy_poll(struct nan
+@@ -2617,7 +2617,7 @@ static int qcom_wait_rdy_poll(struct nand_chip *chip, unsigned int time_ms)
  	unsigned long start = jiffies + msecs_to_jiffies(time_ms);
  	u32 flash;
  
@@ -766,7 +729,7 @@ Change in [v1]
  
  	do {
  		flash = le32_to_cpu(nandc->reg_read_buf[0]);
-@@ -2657,23 +2657,23 @@ static int qcom_read_status_exec(struct
+@@ -2657,23 +2657,23 @@ static int qcom_read_status_exec(struct nand_chip *chip,
  	nandc->buf_start = 0;
  	host->use_ecc = false;
  
@@ -797,7 +760,7 @@ Change in [v1]
  
  	for (i = 0; i < num_cw; i++) {
  		flash_status = le32_to_cpu(nandc->reg_read_buf[i]);
-@@ -2714,8 +2714,8 @@ static int qcom_read_id_type_exec(struct
+@@ -2714,8 +2714,8 @@ static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subo
  	nandc->buf_start = 0;
  	host->use_ecc = false;
  
@@ -808,7 +771,7 @@ Change in [v1]
  
  	nandc->regs->cmd = q_op.cmd_reg;
  	nandc->regs->addr0 = q_op.addr1_reg;
-@@ -2723,12 +2723,12 @@ static int qcom_read_id_type_exec(struct
+@@ -2723,12 +2723,12 @@ static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subo
  	nandc->regs->chip_sel = cpu_to_le32(nandc->props->supports_bam ? 0 : DM_EN);
  	nandc->regs->exec = cpu_to_le32(1);
  
@@ -825,7 +788,7 @@ Change in [v1]
  	if (ret) {
  		dev_err(nandc->dev, "failure in submitting read id descriptor\n");
  		goto err_out;
-@@ -2738,7 +2738,7 @@ static int qcom_read_id_type_exec(struct
+@@ -2738,7 +2738,7 @@ static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subo
  	op_id = q_op.data_instr_idx;
  	len = nand_subop_get_data_len(subop, op_id);
  
@@ -834,7 +797,7 @@ Change in [v1]
  	memcpy(instr->ctx.data.buf.in, nandc->reg_read_buf, len);
  
  err_out:
-@@ -2774,20 +2774,20 @@ static int qcom_misc_cmd_type_exec(struc
+@@ -2774,20 +2774,20 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub
  	nandc->buf_start = 0;
  	host->use_ecc = false;
  
@@ -862,7 +825,7 @@ Change in [v1]
  	if (ret) {
  		dev_err(nandc->dev, "failure in submitting misc descriptor\n");
  		goto err_out;
-@@ -2820,8 +2820,8 @@ static int qcom_param_page_type_exec(str
+@@ -2820,8 +2820,8 @@ static int qcom_param_page_type_exec(struct nand_chip *chip,  const struct nand_
  	nandc->buf_count = 0;
  	nandc->buf_start = 0;
  	host->use_ecc = false;
@@ -873,7 +836,7 @@ Change in [v1]
  
  	nandc->regs->cmd = q_op.cmd_reg;
  	nandc->regs->addr0 = 0;
-@@ -2864,8 +2864,8 @@ static int qcom_param_page_type_exec(str
+@@ -2864,8 +2864,8 @@ static int qcom_param_page_type_exec(struct nand_chip *chip,  const struct nand_
  	nandc_set_read_loc(chip, 0, 0, 0, len, 1);
  
  	if (!nandc->props->qpic_version2) {
@@ -884,7 +847,7 @@ Change in [v1]
  	}
  
  	nandc->buf_count = len;
-@@ -2873,17 +2873,17 @@ static int qcom_param_page_type_exec(str
+@@ -2873,17 +2873,17 @@ static int qcom_param_page_type_exec(struct nand_chip *chip,  const struct nand_
  
  	config_nand_single_cw_page_read(chip, false, 0);
  
@@ -908,7 +871,7 @@ Change in [v1]
  	if (ret) {
  		dev_err(nandc->dev, "failure in submitting param page descriptor\n");
  		goto err_out;
-@@ -3067,7 +3067,7 @@ static int qcom_nandc_alloc(struct qcom_
+@@ -3067,7 +3067,7 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
  		 * maximum codeword size
  		 */
  		nandc->max_cwperpage = 1;
@@ -917,3 +880,6 @@ Change in [v1]
  		if (!nandc->bam_txn) {
  			dev_err(nandc->dev,
  				"failed to allocate bam transaction\n");
+-- 
+2.47.1
+

target/linux/qualcommbe/patches-6.6/100-04-mtd-nand-Add-qpic_common-API-file.patch → target/linux/qualcommbe/patches-6.6/016-03-v6.14-mtd-nand-Add-qpic_common-API-file.patch

@@ -1,117 +1,46 @@
-From b00c2f583e54aa8bed2044e5b1898d9accd45415 Mon Sep 17 00:00:00 2001
+From fdf3ee5c6e5278dab4f60b998b47ed2d510bf80f Mon Sep 17 00:00:00 2001
 From: Md Sadre Alam <[email protected]>
-Date: Wed, 11 Sep 2024 17:20:22 +0530
-Subject: [PATCH v10 4/8] mtd: nand: Add qpic_common API file
+Date: Wed, 20 Nov 2024 14:45:02 +0530
+Subject: [PATCH 3/4] mtd: nand: Add qpic_common API file
 
 Add qpic_common.c file which hold all the common
 qpic APIs which will be used by both qpic raw nand
 driver and qpic spi nand driver.
 
 Signed-off-by: Md Sadre Alam <[email protected]>
+Signed-off-by: Miquel Raynal <[email protected]>
 ---
-
-Change in [v10]
-
-* No change
-
-Change in [v9]
-
-* No Change 
-
-Change in [v8]
-
-* Removed "inline" from qcom_nandc_dev_to_mem()
-
-Change in [v7]
-
-* Removed partition.h
-
-* Updated commit message heading
-
-* Made CONFIG_MTD_NAND_QCOM as bool
-
-Change in [v6]
-
-* made changes to select qpic_common.c based on either
-  CONFIG_MTD_NAND_QCOM=y or CONFIG_SPI_QPIC_SNAND=y
-
-* Removed rawnand.h from qpic_common.c
-
-* change nand_controller variable as a pointer type.
-
-Change in [v5]
-
-* Remove multiple dma call back to avoid race condition
-
-Change in [v4]
-
-* Added kernel doc for all common api as per kernel doc
-  standard
-
-* Added QPIC_COMMON config to build qpic_common.c
-
-Change in [v3]
-
-* Added original copy right
-
-* Removed all EXPORT_SYMBOL()
-
-* Made this common api file more generic
-
-* Added qcom_ prefix to all api in this file
-
-* Removed devm_kfree and added kfree
-
-* Moved to_qcom_nand_controller() to raw nand driver
-  since it was only used by raw nand driver, so not needed
-  as common
-
-* Added kernel doc for all api
-
-* made reverse tree of variable declaration in 
-  prep_adm_dma_desc() function
-
-* Added if(!ret) condition in prep_adm_dma_desc()
-  function
-
-* Initialized slave_conf as 0 while declaration
-
-Change in [v2]
-
-* Posted initial support for common api file
-
-Change in [v1]
-
-* Posted as RFC patch for design review
-
- drivers/mtd/nand/Makefile            |    4 +
- drivers/mtd/nand/qpic_common.c       |  738 +++++++++++++++++
- drivers/mtd/nand/raw/Kconfig         |    2 +-
+ drivers/mtd/nand/Makefile            |    2 +-
+ drivers/mtd/nand/qpic_common.c       |  759 ++++++++++++++++++
  drivers/mtd/nand/raw/qcom_nandc.c    | 1092 +-------------------------
  include/linux/mtd/nand-qpic-common.h |  468 +++++++++++
- 5 files changed, 1223 insertions(+), 1081 deletions(-)
+ 4 files changed, 1240 insertions(+), 1081 deletions(-)
  create mode 100644 drivers/mtd/nand/qpic_common.c
  create mode 100644 include/linux/mtd/nand-qpic-common.h
 
+diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
+index 19e1291ac4d5..da1586a36574 100644
 --- a/drivers/mtd/nand/Makefile
 +++ b/drivers/mtd/nand/Makefile
-@@ -5,6 +5,10 @@ obj-$(CONFIG_MTD_NAND_CORE) += nandcore.
+@@ -3,7 +3,7 @@
+ obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
  obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
  obj-$(CONFIG_MTD_NAND_MTK_BMT)	+= mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
- 
-+ifeq ($(CONFIG_MTD_NAND_QCOM),y)
-+obj-y	+= qpic_common.o
-+endif
-+
+-
++obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o
  obj-y	+= onenand/
  obj-y	+= raw/
  obj-y	+= spi/
+diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
+new file mode 100644
+index 000000000000..8abbb960a7ce
 --- /dev/null
 +++ b/drivers/mtd/nand/qpic_common.c
-@@ -0,0 +1,745 @@
+@@ -0,0 +1,759 @@
 +// SPDX-License-Identifier: GPL-2.0-only
 +/*
 + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
++ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved
 + */
 +#include <linux/clk.h>
 +#include <linux/delay.h>
@@ -137,6 +66,7 @@ Change in [v1]
 +
 +	kfree(bam_txn);
 +}
++EXPORT_SYMBOL(qcom_free_bam_transaction);
 +
 +/**
 + * qcom_alloc_bam_transaction() - allocate BAM transaction
@@ -179,6 +109,7 @@ Change in [v1]
 +
 +	return bam_txn;
 +}
++EXPORT_SYMBOL(qcom_alloc_bam_transaction);
 +
 +/**
 + * qcom_clear_bam_transaction() - Clears the BAM transaction
@@ -193,14 +124,7 @@ Change in [v1]
 +	if (!nandc->props->supports_bam)
 +		return;
 +
-+	bam_txn->bam_ce_pos = 0;
-+	bam_txn->bam_ce_start = 0;
-+	bam_txn->cmd_sgl_pos = 0;
-+	bam_txn->cmd_sgl_start = 0;
-+	bam_txn->tx_sgl_pos = 0;
-+	bam_txn->tx_sgl_start = 0;
-+	bam_txn->rx_sgl_pos = 0;
-+	bam_txn->rx_sgl_start = 0;
++	memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8);
 +	bam_txn->last_data_desc = NULL;
 +
 +	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
@@ -210,6 +134,7 @@ Change in [v1]
 +
 +	reinit_completion(&bam_txn->txn_done);
 +}
++EXPORT_SYMBOL(qcom_clear_bam_transaction);
 +
 +/**
 + * qcom_qpic_bam_dma_done() - Callback for DMA descriptor completion
@@ -223,6 +148,7 @@ Change in [v1]
 +
 +	complete(&bam_txn->txn_done);
 +}
++EXPORT_SYMBOL(qcom_qpic_bam_dma_done);
 +
 +/**
 + * qcom_nandc_dev_to_mem() - Check for dma sync for cpu or device
@@ -247,6 +173,7 @@ Change in [v1]
 +					   sizeof(*nandc->reg_read_buf),
 +					   DMA_FROM_DEVICE);
 +}
++EXPORT_SYMBOL(qcom_nandc_dev_to_mem);
 +
 +/**
 + * qcom_prepare_bam_async_desc() - Prepare DMA descriptor
@@ -326,6 +253,7 @@ Change in [v1]
 +
 +	return 0;
 +}
++EXPORT_SYMBOL(qcom_prepare_bam_async_desc);
 +
 +/**
 + * qcom_prep_bam_dma_desc_cmd() - Prepares the command descriptor for BAM DMA
@@ -388,6 +316,7 @@ Change in [v1]
 +
 +	return 0;
 +}
++EXPORT_SYMBOL(qcom_prep_bam_dma_desc_cmd);
 +
 +/**
 + * qcom_prep_bam_dma_desc_data() - Prepares the data descriptor for BAM DMA
@@ -429,6 +358,7 @@ Change in [v1]
 +
 +	return 0;
 +}
++EXPORT_SYMBOL(qcom_prep_bam_dma_desc_data);
 +
 +/**
 + * qcom_prep_adm_dma_desc() - Prepare descriptor for adma
@@ -517,6 +447,7 @@ Change in [v1]
 +
 +	return ret;
 +}
++EXPORT_SYMBOL(qcom_prep_adm_dma_desc);
 +
 +/**
 + * qcom_read_reg_dma() - read a given number of registers to the reg_read_buf pointer
@@ -550,11 +481,12 @@ Change in [v1]
 +	return qcom_prep_adm_dma_desc(nandc, true, first, vaddr,
 +				      num_regs * sizeof(u32), flow_control);
 +}
++EXPORT_SYMBOL(qcom_read_reg_dma);
 +
 +/**
 + * qcom_write_reg_dma() - write a given number of registers
 + * @nandc: qpic nand controller
-+ * @vaddr: contnigeous memory from where register value will
++ * @vaddr: contiguous memory from where register value will
 + *	   be written
 + * @first: offset of the first register in the contiguous block
 + * @num_regs: number of registers to write
@@ -587,6 +519,7 @@ Change in [v1]
 +	return qcom_prep_adm_dma_desc(nandc, false, first, vaddr,
 +				      num_regs * sizeof(u32), flow_control);
 +}
++EXPORT_SYMBOL(qcom_write_reg_dma);
 +
 +/**
 + * qcom_read_data_dma() - transfer data
@@ -607,6 +540,7 @@ Change in [v1]
 +
 +	return qcom_prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
 +}
++EXPORT_SYMBOL(qcom_read_data_dma);
 +
 +/**
 + * qcom_write_data_dma() - transfer data
@@ -627,6 +561,7 @@ Change in [v1]
 +
 +	return qcom_prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
 +}
++EXPORT_SYMBOL(qcom_write_data_dma);
 +
 +/**
 + * qcom_submit_descs() - submit dma descriptor
@@ -703,6 +638,7 @@ Change in [v1]
 +
 +	return ret;
 +}
++EXPORT_SYMBOL(qcom_submit_descs);
 +
 +/**
 + * qcom_clear_read_regs() - reset the read register buffer
@@ -715,6 +651,7 @@ Change in [v1]
 +	nandc->reg_read_pos = 0;
 +	qcom_nandc_dev_to_mem(nandc, false);
 +}
++EXPORT_SYMBOL(qcom_clear_read_regs);
 +
 +/**
 + * qcom_nandc_unalloc() - unallocate qpic nand controller
@@ -744,6 +681,7 @@ Change in [v1]
 +			dma_release_channel(nandc->chan);
 +	}
 +}
++EXPORT_SYMBOL(qcom_nandc_unalloc);
 +
 +/**
 + * qcom_nandc_alloc() - Allocate qpic nand controller
@@ -854,17 +792,12 @@ Change in [v1]
 +	qcom_nandc_unalloc(nandc);
 +	return ret;
 +}
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -330,7 +330,7 @@ config MTD_NAND_HISI504
- 	  Enables support for NAND controller on Hisilicon SoC Hip04.
- 
- config MTD_NAND_QCOM
--	tristate "QCOM NAND controller"
-+	bool "QCOM NAND controller"
- 	depends on ARCH_QCOM || COMPILE_TEST
- 	depends on HAS_IOMEM
- 	help
++EXPORT_SYMBOL(qcom_nandc_alloc);
++
++MODULE_DESCRIPTION("QPIC controller common api");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
+index 6da5d23d2c8b..dcb62fd19dd7 100644
 --- a/drivers/mtd/nand/raw/qcom_nandc.c
 +++ b/drivers/mtd/nand/raw/qcom_nandc.c
 @@ -15,417 +15,7 @@
@@ -1286,7 +1219,7 @@ Change in [v1]
  
  /*
   * NAND special boot partitions
-@@ -530,104 +120,6 @@ struct qcom_nand_host {
+@@ -530,97 +120,6 @@ struct qcom_nand_host {
  	bool bch_enabled;
  };
  
@@ -1295,7 +1228,7 @@ Change in [v1]
 - * among different NAND controllers.
 - * @ecc_modes - ecc mode for NAND
 - * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
-- * @supports_bam - whether NAND controller is using BAM
+- * @supports_bam - whether NAND controller is using Bus Access Manager (BAM)
 - * @nandc_part_of_qpic - whether NAND controller is part of qpic IP
 - * @qpic_version2 - flag to indicate QPIC IP version 2
 - * @use_codeword_fixup - whether NAND has different layout for boot partitions
@@ -1362,14 +1295,7 @@ Change in [v1]
 -	if (!nandc->props->supports_bam)
 -		return;
 -
--	bam_txn->bam_ce_pos = 0;
--	bam_txn->bam_ce_start = 0;
--	bam_txn->cmd_sgl_pos = 0;
--	bam_txn->cmd_sgl_start = 0;
--	bam_txn->tx_sgl_pos = 0;
--	bam_txn->tx_sgl_start = 0;
--	bam_txn->rx_sgl_pos = 0;
--	bam_txn->rx_sgl_start = 0;
+-	memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8);
 -	bam_txn->last_data_desc = NULL;
 -
 -	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
@@ -1388,11 +1314,11 @@ Change in [v1]
 -	complete(&bam_txn->txn_done);
 -}
 -
- static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
+ static struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
  {
  	return container_of(chip, struct qcom_nand_host, chip);
-@@ -629,8 +128,8 @@ static inline struct qcom_nand_host *to_
- static inline struct qcom_nand_controller *
+@@ -629,8 +128,8 @@ static struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
+ static struct qcom_nand_controller *
  get_qcom_nand_controller(struct nand_chip *chip)
  {
 -	return container_of(chip->controller, struct qcom_nand_controller,
@@ -1401,12 +1327,12 @@ Change in [v1]
 +		((u8 *)chip->controller - sizeof(struct qcom_nand_controller));
  }
  
- static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
-@@ -644,23 +143,6 @@ static inline void nandc_write(struct qc
+ static u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
+@@ -644,23 +143,6 @@ static void nandc_write(struct qcom_nand_controller *nandc, int offset,
  	iowrite32(val, nandc->base + offset);
  }
  
--static inline void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
+-static void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu)
 -{
 -	if (!nandc->props->supports_bam)
 -		return;
@@ -1423,13 +1349,14 @@ Change in [v1]
 -					   DMA_FROM_DEVICE);
 -}
 -
- /* Helper to check the code word, whether it is last cw or not */
+ /* Helper to check whether this is the last CW or not */
  static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
  {
-@@ -820,356 +302,6 @@ static void update_rw_regs(struct qcom_n
+@@ -819,356 +301,6 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
+ 				   host->cw_data : host->cw_size, 1);
  }
  
- /*
+-/*
 - * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
 - * for BAM. This descriptor will be added in the NAND DMA descriptor queue
 - * which will be submitted to DMA engine.
@@ -1712,7 +1639,7 @@ Change in [v1]
 - * qcom_write_reg_dma:	prepares a descriptor to write a given number of
 - *			contiguous registers
 - *
-- * @vaddr:		contnigeous memory from where register value will
+- * @vaddr:		contiguous memory from where register value will
 - *			be written
 - * @first:		offset of the first register in the contiguous block
 - * @num_regs:		number of registers to write
@@ -1779,11 +1706,10 @@ Change in [v1]
 -	return qcom_prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
 -}
 -
--/*
+ /*
   * Helper to prepare DMA descriptors for configuring registers
   * before reading a NAND page.
-  */
-@@ -1262,83 +394,6 @@ static void config_nand_cw_write(struct
+@@ -1262,83 +394,6 @@ static void config_nand_cw_write(struct nand_chip *chip)
  			   NAND_BAM_NEXT_SGL);
  }
  
@@ -1867,7 +1793,7 @@ Change in [v1]
  /*
   * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
   * an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS.
-@@ -2967,141 +2022,14 @@ static const struct nand_controller_ops
+@@ -2967,141 +2022,14 @@ static const struct nand_controller_ops qcom_nandc_ops = {
  	.exec_op = qcom_nand_exec_op,
  };
  
@@ -2012,7 +1938,7 @@ Change in [v1]
  	/* kill onenand */
  	if (!nandc->props->nandc_part_of_qpic)
  		nandc_write(nandc, SFLASHC_BURST_CFG, 0);
-@@ -3240,7 +2168,7 @@ static int qcom_nand_host_init_and_regis
+@@ -3240,7 +2168,7 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
  	chip->legacy.block_bad		= qcom_nandc_block_bad;
  	chip->legacy.block_markbad	= qcom_nandc_block_markbad;
  
@@ -2021,7 +1947,7 @@ Change in [v1]
  	chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA |
  			 NAND_SKIP_BBTSCAN;
  
-@@ -3323,17 +2251,21 @@ static int qcom_nandc_parse_dt(struct pl
+@@ -3323,17 +2251,21 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
  static int qcom_nandc_probe(struct platform_device *pdev)
  {
  	struct qcom_nand_controller *nandc;
@@ -2044,6 +1970,9 @@ Change in [v1]
  
  	dev_data = of_device_get_match_data(dev);
  	if (!dev_data) {
+diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
+new file mode 100644
+index 000000000000..425994429387
 --- /dev/null
 +++ b/include/linux/mtd/nand-qpic-common.h
 @@ -0,0 +1,468 @@
@@ -2515,3 +2444,6 @@ Change in [v1]
 +int qcom_nandc_alloc(struct qcom_nand_controller *nandc);
 +#endif
 +
+-- 
+2.47.1
+

target/linux/qualcommbe/patches-6.6/100-05-mtd-rawnand-qcom-use-FIELD_PREP-and-GENMASK.patch → target/linux/qualcommbe/patches-6.6/016-04-v6.14-mtd-rawnand-qcom-use-FIELD_PREP-and-GENMASK.patch

@@ -1,65 +1,25 @@
-From 9c5b6453db27706f090ab06987394aabaaf24e1b Mon Sep 17 00:00:00 2001
+From 0c08080fd71cd5dd59643104b39d3c89d793ab3c Mon Sep 17 00:00:00 2001
 From: Md Sadre Alam <[email protected]>
-Date: Wed, 11 Sep 2024 12:50:42 +0530
-Subject: [PATCH v10 5/8] mtd: rawnand: qcom: use FIELD_PREP and GENMASK
+Date: Wed, 20 Nov 2024 14:45:03 +0530
+Subject: [PATCH 4/4] mtd: rawnand: qcom: use FIELD_PREP and GENMASK
 
 Use the bitfield macro FIELD_PREP, and GENMASK to
 do the shift and mask in one go. This makes the code
 more readable.
 
+Reviewed-by: Konrad Dybcio <[email protected]>
 Signed-off-by: Md Sadre Alam <[email protected]>
+Signed-off-by: Miquel Raynal <[email protected]>
 ---
-
-Change in [v10]
-
-* No change
-
-Change in [v9]
-
-* In update_rw_regs() api added cpu_to_le32() macro to fix compilation
-  issue reported by kernel test bot
-* In qcom_param_page_type_exec() api added cpu_to_le32() macro to fix
-  compilation issue reported by kernel test bot  
-
-Change in [v8]
-
-* No change
-
-Change in [v7]
-
-* No change
-
-Change in [v6]
-
-* Added FIELD_PREP() and GENMASK() macro
-
-Change in [v5]
-
-* This patch was not included in [v1]
-
-Change in [v4]
-
-* This patch was not included in [v4]
-
-Change in [v3]
-
-* This patch was not included in [v3]
-
-Change in [v2]
-
-* This patch was not included in [v2]
-
-Change in [v1]
-
-* This patch was not included in [v1]
-
  drivers/mtd/nand/raw/qcom_nandc.c    | 97 ++++++++++++++--------------
  include/linux/mtd/nand-qpic-common.h | 31 +++++----
  2 files changed, 67 insertions(+), 61 deletions(-)
 
+diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
+index dcb62fd19dd7..d2d2aeee42a7 100644
 --- a/drivers/mtd/nand/raw/qcom_nandc.c
 +++ b/drivers/mtd/nand/raw/qcom_nandc.c
-@@ -281,7 +281,7 @@ static void update_rw_regs(struct qcom_n
+@@ -281,7 +281,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
  				(num_cw - 1) << CW_PER_PAGE);
  
  		cfg1 = cpu_to_le32(host->cfg1_raw);
@@ -68,7 +28,7 @@ Change in [v1]
  	}
  
  	nandc->regs->cmd = cmd;
-@@ -1494,42 +1494,41 @@ static int qcom_nand_attach_chip(struct
+@@ -1494,42 +1494,41 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
  	host->cw_size = host->cw_data + ecc->bytes;
  	bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1;
  
@@ -146,27 +106,26 @@ Change in [v1]
  
  	if (!nandc->props->qpic_version2)
  		host->ecc_buf_cfg = 0x203 << NUM_STEPS;
-@@ -1882,21 +1881,21 @@ static int qcom_param_page_type_exec(str
+@@ -1882,21 +1881,21 @@ static int qcom_param_page_type_exec(struct nand_chip *chip,  const struct nand_
  	nandc->regs->addr0 = 0;
  	nandc->regs->addr1 = 0;
  
--	nandc->regs->cfg0 = cpu_to_le32(0 << CW_PER_PAGE
--			    | 512 << UD_SIZE_BYTES
--			    | 5 << NUM_ADDR_CYCLES
--			    | 0 << SPARE_SIZE_BYTES);
--
--	nandc->regs->cfg1 = cpu_to_le32(7 << NAND_RECOVERY_CYCLES
--			    | 0 << CS_ACTIVE_BSY
--			    | 17 << BAD_BLOCK_BYTE_NUM
--			    | 1 << BAD_BLOCK_IN_SPARE_AREA
--			    | 2 << WR_RD_BSY_GAP
--			    | 0 << WIDE_FLASH
--			    | 1 << DEV0_CFG1_ECC_DISABLE);
+-	nandc->regs->cfg0 = cpu_to_le32(0 << CW_PER_PAGE |
+-					512 << UD_SIZE_BYTES |
+-					5 << NUM_ADDR_CYCLES |
+-					0 << SPARE_SIZE_BYTES);
 +	host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, 0) |
 +		     FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
 +		     FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
 +		     FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
-+
+ 
+-	nandc->regs->cfg1 = cpu_to_le32(7 << NAND_RECOVERY_CYCLES |
+-					0 << CS_ACTIVE_BSY |
+-					17 << BAD_BLOCK_BYTE_NUM |
+-					1 << BAD_BLOCK_IN_SPARE_AREA |
+-					2 << WR_RD_BSY_GAP |
+-					0 << WIDE_FLASH |
+-					1 << DEV0_CFG1_ECC_DISABLE);
 +	host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
 +		     FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
 +		     FIELD_PREP(CS_ACTIVE_BSY, 0) |
@@ -181,6 +140,8 @@ Change in [v1]
  
  	/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
  	if (!nandc->props->qpic_version2) {
+diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
+index 425994429387..e79c79775eb8 100644
 --- a/include/linux/mtd/nand-qpic-common.h
 +++ b/include/linux/mtd/nand-qpic-common.h
 @@ -70,35 +70,42 @@
@@ -238,3 +199,6 @@ Change in [v1]
  
  /* NAND_DEV_CMD1 bits */
  #define	READ_ADDR			0
+-- 
+2.47.1
+

target/linux/qualcommbe/patches-6.6/017-v6.,14-mtd-rawnand-qcom-Fix-build-issue-on-x86-architecture.patch

@@ -0,0 +1,84 @@
+From b9371866799d67a80be0ea9e01bd41987db22f26 Mon Sep 17 00:00:00 2001
+From: Md Sadre Alam <[email protected]>
+Date: Mon, 6 Jan 2025 18:45:58 +0530
+Subject: [PATCH] mtd: rawnand: qcom: Fix build issue on x86 architecture
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Fix a buffer overflow issue in qcom_clear_bam_transaction by using
+struct_group to group related fields and avoid FORTIFY_SOURCE warnings.
+
+On x86 architecture, the following error occurs due to warnings being
+treated as errors:
+
+In function ‘fortify_memset_chk’,
+    inlined from ‘qcom_clear_bam_transaction’ at
+drivers/mtd/nand/qpic_common.c:88:2:
+./include/linux/fortify-string.h:480:25: error: call to ‘__write_overflow_field’
+declared with attribute warning: detected write beyond size of field
+(1st parameter); maybe use struct_group()? [-Werror=attribute-warning]
+  480 |                         __write_overflow_field(p_size_field, size);
+      |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  LD [M]  drivers/mtd/nand/nandcore.o
+  CC [M]  drivers/w1/masters/mxc_w1.o
+cc1: all warnings being treated as errors
+
+This patch addresses the issue by grouping the related fields in
+struct bam_transaction using struct_group and updating the memset call
+accordingly.
+
+Fixes: 8c52932da5e6 ("mtd: rawnand: qcom: cleanup qcom_nandc driver")
+Signed-off-by: Md Sadre Alam <[email protected]>
+Signed-off-by: Miquel Raynal <[email protected]>
+---
+ drivers/mtd/nand/qpic_common.c       |  2 +-
+ include/linux/mtd/nand-qpic-common.h | 19 +++++++++++--------
+ 2 files changed, 12 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
+index 8abbb960a7ce..e0ed25b5afea 100644
+--- a/drivers/mtd/nand/qpic_common.c
++++ b/drivers/mtd/nand/qpic_common.c
+@@ -85,7 +85,7 @@ void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc)
+ 	if (!nandc->props->supports_bam)
+ 		return;
+ 
+-	memset(&bam_txn->bam_ce_pos, 0, sizeof(u32) * 8);
++	memset(&bam_txn->bam_positions, 0, sizeof(bam_txn->bam_positions));
+ 	bam_txn->last_data_desc = NULL;
+ 
+ 	sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
+diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
+index e79c79775eb8..4d9b736ff8b7 100644
+--- a/include/linux/mtd/nand-qpic-common.h
++++ b/include/linux/mtd/nand-qpic-common.h
+@@ -254,14 +254,17 @@ struct bam_transaction {
+ 	struct dma_async_tx_descriptor *last_data_desc;
+ 	struct dma_async_tx_descriptor *last_cmd_desc;
+ 	struct completion txn_done;
+-	u32 bam_ce_pos;
+-	u32 bam_ce_start;
+-	u32 cmd_sgl_pos;
+-	u32 cmd_sgl_start;
+-	u32 tx_sgl_pos;
+-	u32 tx_sgl_start;
+-	u32 rx_sgl_pos;
+-	u32 rx_sgl_start;
++	struct_group(bam_positions,
++		u32 bam_ce_pos;
++		u32 bam_ce_start;
++		u32 cmd_sgl_pos;
++		u32 cmd_sgl_start;
++		u32 tx_sgl_pos;
++		u32 tx_sgl_start;
++		u32 rx_sgl_pos;
++		u32 rx_sgl_start;
++
++	);
+ };
+ 
+ /*
+-- 
+2.47.1
+

target/linux/qualcommbe/patches-6.6/104-02-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ.patch → target/linux/qualcommbe/patches-6.6/018-v6.14-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ.patch

@@ -1,8 +1,7 @@
-From f9ecde8dc380769d1477f01416d2e3a65c4fd881 Mon Sep 17 00:00:00 2001
+From f81715a4c87c3b75ca2640bb61b6c66506061a64 Mon Sep 17 00:00:00 2001
 From: Luo Jie <[email protected]>
-Date: Thu, 7 Nov 2024 17:50:23 +0800
-Subject: [PATCH 2/5] clk: qcom: Add CMN PLL clock controller driver for IPQ
- SoC
+Date: Fri, 3 Jan 2025 15:31:35 +0800
+Subject: [PATCH] clk: qcom: Add CMN PLL clock controller driver for IPQ SoC
 
 The CMN PLL clock controller supplies clocks to the hardware
 blocks that together make up the Ethernet function on Qualcomm
@@ -23,18 +22,21 @@ clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25
 MHZ clock to PCS.
 
 Signed-off-by: Luo Jie <[email protected]>
+Acked-by: Konrad Dybcio <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Bjorn Andersson <[email protected]>
 ---
  drivers/clk/qcom/Kconfig       |   9 +
  drivers/clk/qcom/Makefile      |   1 +
- drivers/clk/qcom/ipq-cmn-pll.c | 436 +++++++++++++++++++++++++++++++++
- 3 files changed, 446 insertions(+)
+ drivers/clk/qcom/ipq-cmn-pll.c | 435 +++++++++++++++++++++++++++++++++
+ 3 files changed, 445 insertions(+)
  create mode 100644 drivers/clk/qcom/ipq-cmn-pll.c
 
 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
-index b9a5cc9fd8c8..3cc7156f881d 100644
+index 42c257e4c433..2daff198aeb3 100644
 --- a/drivers/clk/qcom/Kconfig
 +++ b/drivers/clk/qcom/Kconfig
-@@ -190,6 +190,15 @@ config IPQ_APSS_6018
+@@ -199,6 +199,15 @@ config IPQ_APSS_6018
  	  Say Y if you want to support CPU frequency scaling on
  	  ipq based devices.
  
@@ -51,10 +53,10 @@ index b9a5cc9fd8c8..3cc7156f881d 100644
  	tristate "IPQ4019 Global Clock Controller"
  	help
 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
-index 65b825a54c45..d12ed80a3021 100644
+index 1b749da9c13a..6665049cb8c8 100644
 --- a/drivers/clk/qcom/Makefile
 +++ b/drivers/clk/qcom/Makefile
-@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o
+@@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_X1P42100_GPUCC) += gpucc-x1p42100.o
  obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o
  obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
  obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
@@ -64,10 +66,10 @@ index 65b825a54c45..d12ed80a3021 100644
  obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
 diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c
 new file mode 100644
-index 000000000000..1da8a4a9a8d5
+index 000000000000..432d4c4b7aa6
 --- /dev/null
 +++ b/drivers/clk/qcom/ipq-cmn-pll.c
-@@ -0,0 +1,436 @@
+@@ -0,0 +1,435 @@
 +// SPDX-License-Identifier: GPL-2.0-only
 +/*
 + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
@@ -296,9 +298,8 @@ index 000000000000..1da8a4a9a8d5
 +	}
 +
 +	/* Enable PLL locked detect. */
-+	ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_CTRL,
-+				 CMN_PLL_CTRL_LOCK_DETECT_EN,
-+				 CMN_PLL_CTRL_LOCK_DETECT_EN);
++	ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL,
++			      CMN_PLL_CTRL_LOCK_DETECT_EN);
 +	if (ret)
 +		return ret;
 +
@@ -306,14 +307,14 @@ index 000000000000..1da8a4a9a8d5
 +	 * Reset the CMN PLL block to ensure the updated configurations
 +	 * take effect.
 +	 */
-+	ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,
-+				 CMN_ANA_EN_SW_RSTN, 0);
++	ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,
++				CMN_ANA_EN_SW_RSTN);
 +	if (ret)
 +		return ret;
 +
 +	usleep_range(1000, 1200);
-+	ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,
-+				 CMN_ANA_EN_SW_RSTN, CMN_ANA_EN_SW_RSTN);
++	ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,
++			      CMN_ANA_EN_SW_RSTN);
 +	if (ret)
 +		return ret;
 +
@@ -441,7 +442,7 @@ index 000000000000..1da8a4a9a8d5
 +		return ret;
 +
 +	/*
-+	 * To access the CMN PLL registers, the GCC AHB & SYSY clocks
++	 * To access the CMN PLL registers, the GCC AHB & SYS clocks
 +	 * of CMN PLL block need to be enabled.
 +	 */
 +	ret = pm_clk_add(dev, "ahb");
@@ -505,5 +506,5 @@ index 000000000000..1da8a4a9a8d5
 +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver");
 +MODULE_LICENSE("GPL");
 -- 
-2.45.2
+2.47.1
 

target/linux/qualcommbe/patches-6.6/104-01-dt-bindings-clock-qcom-Add-CMN-PLL-clock-controller-.patch → target/linux/qualcommbe/patches-6.6/019-01-v6.14-dt-bindings-clock-qcom-Add-CMN-PLL-clock-controller-.patch

@@ -1,7 +1,7 @@
-From be826ce36477e94539f5d2dfe292126dbb39b3a4 Mon Sep 17 00:00:00 2001
+From c0f1cbf795095c21b92a46fa1dc47a7b787ce538 Mon Sep 17 00:00:00 2001
 From: Luo Jie <[email protected]>
-Date: Thu, 7 Nov 2024 17:50:22 +0800
-Subject: [PATCH 1/5] dt-bindings: clock: qcom: Add CMN PLL clock controller
+Date: Fri, 3 Jan 2025 15:31:34 +0800
+Subject: [PATCH 1/3] dt-bindings: clock: qcom: Add CMN PLL clock controller
  for IPQ SoC
 
 The CMN PLL controller provides clocks to networking hardware blocks
@@ -14,21 +14,23 @@ connected switch or PHY device. The CMN PLL block also outputs fixed
 rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
 clock supplied to GCC.
 
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
 Signed-off-by: Luo Jie <[email protected]>
+Reviewed-by: Krzysztof Kozlowski <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Bjorn Andersson <[email protected]>
 ---
- .../bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 85 +++++++++++++++++++
- include/dt-bindings/clock/qcom,ipq-cmn-pll.h  | 22 +++++
- 2 files changed, 107 insertions(+)
+ .../bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 77 +++++++++++++++++++
+ include/dt-bindings/clock/qcom,ipq-cmn-pll.h  | 22 ++++++
+ 2 files changed, 99 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
  create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h
 
 diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
 new file mode 100644
-index 000000000000..db8a3ee56067
+index 000000000000..f869b3739be8
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
-@@ -0,0 +1,85 @@
+@@ -0,0 +1,77 @@
 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
 +%YAML 1.2
 +---
@@ -80,20 +82,12 @@ index 000000000000..db8a3ee56067
 +  "#clock-cells":
 +    const: 1
 +
-+  assigned-clocks:
-+    maxItems: 1
-+
-+  assigned-clock-rates-u64:
-+    maxItems: 1
-+
 +required:
 +  - compatible
 +  - reg
 +  - clocks
 +  - clock-names
 +  - "#clock-cells"
-+  - assigned-clocks
-+  - assigned-clock-rates-u64
 +
 +additionalProperties: false
 +
@@ -143,5 +137,5 @@ index 000000000000..936e92b3b62c
 +#define ETH_25MHZ_CLK			9
 +#endif
 -- 
-2.45.2
+2.47.1
 

target/linux/qualcommbe/patches-6.6/104-04-arm64-dts-qcom-Add-CMN-PLL-node-for-IPQ9574-SoC.patch → target/linux/qualcommbe/patches-6.6/019-02-v6.14-arm64-dts-qcom-ipq9574-Add-CMN-PLL-node.patch

@@ -1,7 +1,7 @@
-From ed97b7b7c657baf9c9d8e9dfebd9f7703c870593 Mon Sep 17 00:00:00 2001
+From 758aa2d7e3c0acfe9c952a1cbe6416ec6130c2a1 Mon Sep 17 00:00:00 2001
 From: Luo Jie <[email protected]>
-Date: Thu, 7 Nov 2024 17:50:25 +0800
-Subject: [PATCH 4/5] arm64: dts: qcom: Add CMN PLL node for IPQ9574 SoC
+Date: Fri, 3 Jan 2025 15:31:37 +0800
+Subject: [PATCH 2/3] arm64: dts: qcom: ipq9574: Add CMN PLL node
 
 The CMN PLL clock controller allows selection of an input clock rate
 from a defined set of input clock rates. It in-turn supplies fixed
@@ -20,13 +20,16 @@ automatically configured by hardware (1 for 48 MHZ, 2 for 96 MHZ), to
 ensure output clock to CMN PLL is 48 MHZ.
 
 Signed-off-by: Luo Jie <[email protected]>
+Reviewed-by: Konrad Dybcio <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Bjorn Andersson <[email protected]>
 ---
- .../boot/dts/qcom/ipq9574-rdp-common.dtsi     | 16 +++++++++++-
+ .../boot/dts/qcom/ipq9574-rdp-common.dtsi     | 17 +++++++++++-
  arch/arm64/boot/dts/qcom/ipq9574.dtsi         | 26 ++++++++++++++++++-
- 2 files changed, 40 insertions(+), 2 deletions(-)
+ 2 files changed, 41 insertions(+), 2 deletions(-)
 
 diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
-index 91e104b0f865..78f6a2e053d5 100644
+index 91e104b0f865..bb1ff79360d3 100644
 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
 @@ -3,7 +3,7 @@
@@ -38,14 +41,15 @@ index 91e104b0f865..78f6a2e053d5 100644
   */
  
  /dts-v1/;
-@@ -164,6 +164,20 @@ &usb3 {
+@@ -164,6 +164,21 @@ &usb3 {
  	status = "okay";
  };
  
 +/*
-+ * The bootstrap pins for the board select the XO clock frequency,
-+ * which automatically enables the right dividers to ensure the
-+ * reference clock output from WiFi is 48 MHZ.
++ * The bootstrap pins for the board select the XO clock frequency
++ * (48 MHZ or 96 MHZ used for different RDP type board). This setting
++ * automatically enables the right dividers, to ensure the reference
++ * clock output from WiFi to the CMN PLL is 48 MHZ.
 + */
 +&ref_48mhz_clk {
 +	clock-div = <1>;
@@ -60,7 +64,7 @@ index 91e104b0f865..78f6a2e053d5 100644
 +	clock-frequency = <48000000>;
 +};
 diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-index c113fff22f73..dc4965abff58 100644
+index 00ee3290c181..c543c3492e93 100644
 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
 @@ -3,10 +3,11 @@
@@ -76,7 +80,7 @@ index c113fff22f73..dc4965abff58 100644
  #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
  #include <dt-bindings/interconnect/qcom,ipq9574.h>
  #include <dt-bindings/interrupt-controller/arm-gic.h>
-@@ -21,6 +22,12 @@ / {
+@@ -19,6 +20,12 @@ / {
  	#size-cells = <2>;
  
  	clocks {
@@ -89,7 +93,7 @@ index c113fff22f73..dc4965abff58 100644
  		sleep_clk: sleep-clk {
  			compatible = "fixed-clock";
  			#clock-cells = <0>;
-@@ -30,6 +37,11 @@ xo_board_clk: xo-board-clk {
+@@ -28,6 +35,11 @@ xo_board_clk: xo-board-clk {
  			compatible = "fixed-clock";
  			#clock-cells = <0>;
  		};
@@ -101,7 +105,7 @@ index c113fff22f73..dc4965abff58 100644
  	};
  
  	cpus {
-@@ -245,6 +257,18 @@ mdio: mdio@90000 {
+@@ -335,6 +347,18 @@ pcie1_phy: phy@fc000 {
  			status = "disabled";
  		};
  
@@ -121,5 +125,5 @@ index c113fff22f73..dc4965abff58 100644
  			compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
  			reg = <0x000a4000 0x5a1>;
 -- 
-2.45.2
+2.47.1
 

target/linux/qualcommbe/patches-6.6/104-05-arm64-dts-qcom-Update-IPQ9574-xo_board_clk-to-use-fi.patch → target/linux/qualcommbe/patches-6.6/019-03-v6.14-arm64-dts-qcom-ipq9574-Update-xo_board_clk-to-use-fi.patch

@@ -1,24 +1,27 @@
-From dcb1e63fbc695c3971d7207238a78f66355a2f9a Mon Sep 17 00:00:00 2001
+From 050b312654523aac9495eae3cf7bfa868fd981ce Mon Sep 17 00:00:00 2001
 From: Luo Jie <[email protected]>
-Date: Thu, 7 Nov 2024 17:50:26 +0800
-Subject: [PATCH 5/5] arm64: dts: qcom: Update IPQ9574 xo_board_clk to use
+Date: Fri, 3 Jan 2025 15:31:38 +0800
+Subject: [PATCH 3/3] arm64: dts: qcom: ipq9574: Update xo_board_clk to use
  fixed factor clock
 
 xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock
 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog
 block routing channel.
 
+Reviewed-by: Konrad Dybcio <[email protected]>
 Signed-off-by: Luo Jie <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Bjorn Andersson <[email protected]>
 ---
  arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 7 ++++++-
  arch/arm64/boot/dts/qcom/ipq9574.dtsi            | 3 ++-
  2 files changed, 8 insertions(+), 2 deletions(-)
 
 diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
-index 78f6a2e053d5..9a8692377176 100644
+index bb1ff79360d3..ae12f069f26f 100644
 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
-@@ -174,8 +174,13 @@ &ref_48mhz_clk {
+@@ -175,8 +175,13 @@ &ref_48mhz_clk {
  	clock-mult = <1>;
  };
  
@@ -34,10 +37,10 @@ index 78f6a2e053d5..9a8692377176 100644
  
  &xo_clk {
 diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-index dc4965abff58..376b75976524 100644
+index c543c3492e93..3e93484e7e32 100644
 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-@@ -34,7 +34,8 @@ sleep_clk: sleep-clk {
+@@ -32,7 +32,8 @@ sleep_clk: sleep-clk {
  		};
  
  		xo_board_clk: xo-board-clk {
@@ -48,5 +51,5 @@ index dc4965abff58..376b75976524 100644
  		};
  
 -- 
-2.45.2
+2.47.1
 

target/linux/qualcommbe/patches-6.6/100-06-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Inte.patch

@@ -1,8 +1,18 @@
-From dc12953941ed3b8bc9eb8d47f8c7e74f54b47049 Mon Sep 17 00:00:00 2001
 From: Md Sadre Alam <[email protected]>
-Date: Mon, 19 Aug 2024 11:05:18 +0530
-Subject: [PATCH v10 6/8] spi: spi-qpic: add driver for QCOM SPI NAND flash
- Interface
+To: <[email protected]>, <[email protected]>, <[email protected]>,
+	<[email protected]>, <[email protected]>,
+	<[email protected]>, <[email protected]>,
+	<[email protected]>, <[email protected]>,
+	<[email protected]>,
+	<[email protected]>, <[email protected]>,
+	<[email protected]>, <[email protected]>,
+	<[email protected]>
+Cc: <[email protected]>, <[email protected]>,
+	<[email protected]>
+Subject: [PATCH v14 6/8] spi: spi-qpic: add driver for QCOM SPI NAND flash Interface
+Date: Wed, 20 Nov 2024 14:45:04 +0530	[thread overview]
+Message-ID: <[email protected]> (raw)
+In-Reply-To: <[email protected]>
 
 This driver implements support for the SPI-NAND mode of QCOM NAND Flash
 Interface as a SPI-MEM controller with pipelined ECC capability.
@@ -14,6 +24,31 @@ Signed-off-by: Varadarajan Narayanan <[email protected]>
 Signed-off-by: Md Sadre Alam <[email protected]>
 ---
 
+Change in [v14]
+
+* No Change 
+
+Change in [v13]
+
+* Changed return type of qcom_spi_cmd_mapping() from u32 to
+  int to fix the kernel test bot warning
+* Changed type of variable cmd in qcom_spi_write_page() from u32
+  to int
+* Removed unused variable s_op from qcom_spi_write_page()
+* Updated return value variable type from u32 to int in
+  qcom_spi_send_cmdaddr() 
+
+Change in [v12]
+
+* Added obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o in Makefile
+  to build qpic_common.c based on CONFIG_SPI_QPIC_SNAND
+
+Change in [v11]
+
+* Fixed build error reported by kernel test bot
+* Changed "depends on MTD" to "select MTD" in
+  drivers/spi/Kconfig file
+
 Change in [v10]
 
 * Fixed compilation warnings reported by kernel test robot.
@@ -166,39 +201,42 @@ Change in [v1]
 
 * Added RFC patch for design review
 
- drivers/mtd/nand/Makefile            |    5 +-
+ drivers/mtd/nand/Makefile            |    4 +
  drivers/spi/Kconfig                  |    9 +
  drivers/spi/Makefile                 |    1 +
- drivers/spi/spi-qpic-snand.c         | 1634 ++++++++++++++++++++++++++
+ drivers/spi/spi-qpic-snand.c         | 1633 ++++++++++++++++++++++++++
  include/linux/mtd/nand-qpic-common.h |    7 +
- 5 files changed, 1655 insertions(+), 1 deletion(-)
+ 5 files changed, 1654 insertions(+)
  create mode 100644 drivers/spi/spi-qpic-snand.c
 
+diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
+index da1586a36574..db516a45f0c5 100644
 --- a/drivers/mtd/nand/Makefile
 +++ b/drivers/mtd/nand/Makefile
-@@ -7,8 +7,11 @@ obj-$(CONFIG_MTD_NAND_MTK_BMT)	+= mtk_bm
- 
- ifeq ($(CONFIG_MTD_NAND_QCOM),y)
- obj-y	+= qpic_common.o
-+else
+@@ -3,7 +3,11 @@
+ obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
+ obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
+ obj-$(CONFIG_MTD_NAND_MTK_BMT)	+= mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
 +ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
-+obj-y   += qpic_common.o
++obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o
++else
+ obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o
 +endif
- endif
--
  obj-y	+= onenand/
  obj-y	+= raw/
  obj-y	+= spi/
+diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
+index f51f9466e518..1aaf93964429 100644
 --- a/drivers/spi/Kconfig
 +++ b/drivers/spi/Kconfig
-@@ -870,6 +870,15 @@ config SPI_QCOM_QSPI
+@@ -920,6 +920,15 @@ config SPI_QCOM_QSPI
  	help
  	  QSPI(Quad SPI) driver for Qualcomm QSPI controller.
  
 +config SPI_QPIC_SNAND
 +	bool "QPIC SNAND controller"
 +	depends on ARCH_QCOM || COMPILE_TEST
-+	depends on MTD
++	select MTD
 +	help
 +	  QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
 +	  QPIC controller supports both parallel nand and serial nand.
@@ -207,9 +245,11 @@ Change in [v1]
  config SPI_QUP
  	tristate "Qualcomm SPI controller with QUP interface"
  	depends on ARCH_QCOM || COMPILE_TEST
+diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
+index aea5e54de195..3309b7bb2445 100644
 --- a/drivers/spi/Makefile
 +++ b/drivers/spi/Makefile
-@@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx-
+@@ -115,6 +115,7 @@ obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx-platform.o
  obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o
  obj-$(CONFIG_SPI_QCOM_GENI)		+= spi-geni-qcom.o
  obj-$(CONFIG_SPI_QCOM_QSPI)		+= spi-qcom-qspi.o
@@ -217,9 +257,12 @@ Change in [v1]
  obj-$(CONFIG_SPI_QUP)			+= spi-qup.o
  obj-$(CONFIG_SPI_ROCKCHIP)		+= spi-rockchip.o
  obj-$(CONFIG_SPI_ROCKCHIP_SFC)		+= spi-rockchip-sfc.o
+diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
+new file mode 100644
+index 000000000000..1ba562a9369e
 --- /dev/null
 +++ b/drivers/spi/spi-qpic-snand.c
-@@ -0,0 +1,1634 @@
+@@ -0,0 +1,1633 @@
 +/*
 + * SPDX-License-Identifier: GPL-2.0
 + *
@@ -1422,9 +1465,9 @@ Change in [v1]
 +	return 0;
 +}
 +
-+static u32 qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode)
++static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode)
 +{
-+	u32 cmd = 0x0;
++	int cmd = 0x0;
 +
 +	switch (opcode) {
 +	case SPINAND_RESET:
@@ -1475,15 +1518,12 @@ Change in [v1]
 +static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
 +			       const struct spi_mem_op *op)
 +{
-+	struct qpic_snand_op s_op = {};
-+	u32 cmd;
++	int cmd;
 +
 +	cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
 +	if (cmd < 0)
 +		return cmd;
 +
-+	s_op.cmd_reg = cmd;
-+
 +	if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
 +		snandc->qspi->data_buf = (u8 *)op->data.buf.out;
 +
@@ -1497,9 +1537,11 @@ Change in [v1]
 +	u32 cmd;
 +	int ret, opcode;
 +
-+	cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
-+	if (cmd < 0)
-+		return cmd;
++	ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
++	if (ret < 0)
++		return ret;
++
++	cmd = ret;
 +
 +	s_op.cmd_reg = cmd;
 +	s_op.addr1_reg = op->addr.val;
@@ -1833,7 +1875,7 @@ Change in [v1]
 +
 +static const struct of_device_id qcom_snandc_of_match[] = {
 +	{
-+		.compatible = "qcom,spi-qpic-snand",
++		.compatible = "qcom,ipq9574-snand",
 +		.data = &ipq9574_snandc_props,
 +	},
 +	{}
@@ -1854,6 +1896,8 @@ Change in [v1]
 +MODULE_AUTHOR("Md Sadre Alam <[email protected]>");
 +MODULE_LICENSE("GPL");
 +
+diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
+index e79c79775eb8..7dba89654d6c 100644
 --- a/include/linux/mtd/nand-qpic-common.h
 +++ b/include/linux/mtd/nand-qpic-common.h
 @@ -322,6 +322,10 @@ struct nandc_regs {
@@ -1891,3 +1935,5 @@ Change in [v1]
  	struct list_head host_list;
  
  	union {
+-- 
+2.34.1

target/linux/qualcommbe/patches-6.6/105-01-clk-qcom-clk-alpha-pll-Add-NSS-HUAYRA-ALPHA-PLL-supp.patch

@@ -1,55 +0,0 @@
-From 4305650c92eef5921cc140c999eccbb6de1ab4b8 Mon Sep 17 00:00:00 2001
-From: Devi Priya <[email protected]>
-Date: Fri, 25 Oct 2024 09:25:14 +0530
-Subject: [PATCH 1/7] clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL
- support for ipq9574
-
-Add support for NSS Huayra alpha pll found on ipq9574 SoCs.
-Programming sequence is the same as that of Huayra type Alpha PLL,
-so we can re-use the same.
-
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Signed-off-by: Devi Priya <[email protected]>
-Signed-off-by: Manikanta Mylavarapu <[email protected]>
----
- drivers/clk/qcom/clk-alpha-pll.c | 11 +++++++++++
- drivers/clk/qcom/clk-alpha-pll.h |  1 +
- 2 files changed, 12 insertions(+)
-
-diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
-index f9105443d7db..c2e56e9403ff 100644
---- a/drivers/clk/qcom/clk-alpha-pll.c
-+++ b/drivers/clk/qcom/clk-alpha-pll.c
-@@ -267,6 +267,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
- 		[PLL_OFF_OPMODE] = 0x30,
- 		[PLL_OFF_STATUS] = 0x3c,
- 	},
-+	[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] =  {
-+		[PLL_OFF_L_VAL] = 0x04,
-+		[PLL_OFF_ALPHA_VAL] = 0x08,
-+		[PLL_OFF_TEST_CTL] = 0x0c,
-+		[PLL_OFF_TEST_CTL_U] = 0x10,
-+		[PLL_OFF_USER_CTL] = 0x14,
-+		[PLL_OFF_CONFIG_CTL] = 0x18,
-+		[PLL_OFF_CONFIG_CTL_U] = 0x1c,
-+		[PLL_OFF_STATUS] = 0x20,
-+	},
-+
- };
- EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
- 
-diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
-index 55eca04b23a1..c6d1b8429f95 100644
---- a/drivers/clk/qcom/clk-alpha-pll.h
-+++ b/drivers/clk/qcom/clk-alpha-pll.h
-@@ -32,6 +32,7 @@ enum {
- 	CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
- 	CLK_ALPHA_PLL_TYPE_STROMER,
- 	CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
-+	CLK_ALPHA_PLL_TYPE_NSS_HUAYRA,
- 	CLK_ALPHA_PLL_TYPE_MAX,
- };
- 
--- 
-2.45.2
-

target/linux/qualcommbe/patches-6.6/303-arm64-dts-qcom-add-partition-table-for-ipq9574-rdp-c.patch

@@ -106,7 +106,7 @@ index 9a8692377176..13b623603d37 100644
 +			partition@4d0000 {
 +				label = "0:rpm";
 +				reg = <0x4d0000 0x20000>;
-+				read-only;
++				// read-only;
 +			};
 +
 +			partition@4f0000 {