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@@ -1,125 +0,0 @@
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-From 9989fcd49c52500a2bf1f6d49411690dec45d2dc Mon Sep 17 00:00:00 2001
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-From: =?UTF-8?q?Marko=20M=C3=A4kel=C3=A4?= <[email protected]>
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-Date: Sat, 2 Aug 2025 12:47:08 +0300
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-Subject: [PATCH] clk: qcom: gcc-ipq6018: rework nss_port5 clock to multiple
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- conf
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-
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-Rework nss_port5 to use the new multiple configuration implementation
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-and correctly fix the clocks for this port under some corner case.
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-
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-In OpenWrt, this patch avoids intermittent dmesg errors of the form
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-nss_port5_rx_clk_src: rcg didn't update its configuration.
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-
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-This is a mechanical, straightforward port of
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-commit e88f03230dc07aa3293b6aeb078bd27370bb2594
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-("clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf")
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-to gcc-ipq6018, with two conflicts resolved: different frequency of the
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-P_XO clock source, and only 5 Ethernet ports.
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-
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-This was originally developed by JiaY-shi <[email protected]>.
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-
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-Link: https://lore.kernel.org/all/[email protected]/
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-Signed-off-by: Marko Mäkelä <[email protected]>
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-Tested-by: Marko Mäkelä <[email protected]>
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----
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- drivers/clk/qcom/gcc-ipq6018.c | 60 +++++++++++++++++++++-------------
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- 1 file changed, 38 insertions(+), 22 deletions(-)
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-
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---- a/drivers/clk/qcom/gcc-ipq6018.c
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-+++ b/drivers/clk/qcom/gcc-ipq6018.c
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-@@ -511,15 +511,23 @@ static struct clk_rcg2 apss_ahb_clk_src
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- },
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- };
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-
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--static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
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-- F(24000000, P_XO, 1, 0, 0),
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-- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
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-- F(25000000, P_UNIPHY0_RX, 5, 0, 0),
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-- F(78125000, P_UNIPHY1_RX, 4, 0, 0),
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-- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
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-- F(125000000, P_UNIPHY0_RX, 1, 0, 0),
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-- F(156250000, P_UNIPHY1_RX, 2, 0, 0),
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-- F(312500000, P_UNIPHY1_RX, 1, 0, 0),
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-+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
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-+ C(P_UNIPHY1_RX, 12.5, 0, 0),
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-+ C(P_UNIPHY0_RX, 5, 0, 0),
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-+};
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-+
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-+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
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-+ C(P_UNIPHY1_RX, 2.5, 0, 0),
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-+ C(P_UNIPHY0_RX, 1, 0, 0),
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-+};
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-+
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-+static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
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-+ FMS(24000000, P_XO, 1, 0, 0),
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-+ FM(25000000, ftbl_nss_port5_rx_clk_src_25),
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-+ FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
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-+ FM(125000000, ftbl_nss_port5_rx_clk_src_125),
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-+ FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
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-+ FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
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- { }
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- };
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-
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-@@ -547,26 +555,34 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32
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-
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- static struct clk_rcg2 nss_port5_rx_clk_src = {
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- .cmd_rcgr = 0x68060,
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-- .freq_tbl = ftbl_nss_port5_rx_clk_src,
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-+ .freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
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- .hid_width = 5,
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- .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
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- .clkr.hw.init = &(struct clk_init_data){
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- .name = "nss_port5_rx_clk_src",
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- .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
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- .num_parents = 7,
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-- .ops = &clk_rcg2_ops,
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-+ .ops = &clk_rcg2_fm_ops,
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- },
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- };
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-
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--static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
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-- F(24000000, P_XO, 1, 0, 0),
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-- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
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-- F(25000000, P_UNIPHY0_TX, 5, 0, 0),
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-- F(78125000, P_UNIPHY1_TX, 4, 0, 0),
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-- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
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-- F(125000000, P_UNIPHY0_TX, 1, 0, 0),
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-- F(156250000, P_UNIPHY1_TX, 2, 0, 0),
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-- F(312500000, P_UNIPHY1_TX, 1, 0, 0),
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-+static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
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-+ C(P_UNIPHY1_TX, 12.5, 0, 0),
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-+ C(P_UNIPHY0_TX, 5, 0, 0),
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-+};
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-+
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-+static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
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-+ C(P_UNIPHY1_TX, 2.5, 0, 0),
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-+ C(P_UNIPHY0_TX, 1, 0, 0),
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-+};
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-+
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-+static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
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-+ FMS(24000000, P_XO, 1, 0, 0),
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-+ FM(25000000, ftbl_nss_port5_tx_clk_src_25),
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-+ FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
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-+ FM(125000000, ftbl_nss_port5_tx_clk_src_125),
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-+ FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
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-+ FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
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- { }
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- };
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-
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-@@ -594,14 +610,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32
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-
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- static struct clk_rcg2 nss_port5_tx_clk_src = {
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- .cmd_rcgr = 0x68068,
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-- .freq_tbl = ftbl_nss_port5_tx_clk_src,
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-+ .freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
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- .hid_width = 5,
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- .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
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- .clkr.hw.init = &(struct clk_init_data){
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- .name = "nss_port5_tx_clk_src",
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- .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
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- .num_parents = 7,
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-- .ops = &clk_rcg2_ops,
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-+ .ops = &clk_rcg2_fm_ops,
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- },
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- };
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-
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