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@@ -0,0 +1,396 @@
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+--- a/arch/mips/alchemy/Kconfig
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++++ b/arch/mips/alchemy/Kconfig
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+@@ -134,3 +134,4 @@ config SOC_AU1X00
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_32BIT_KERNEL
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+ select SYS_SUPPORTS_APM_EMULATION
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++ select ARCH_REQUIRE_GPIOLIB
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+--- a/arch/mips/alchemy/common/gpio.c
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++++ b/arch/mips/alchemy/common/gpio.c
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+@@ -1,5 +1,5 @@
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+ /*
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+- * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <[email protected]>
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++ * Copyright (C) 2007-2008, OpenWrt.org, Florian Fainelli <[email protected]>
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+ * Architecture specific GPIO support
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+@@ -27,122 +27,222 @@
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+ * others have a second one : GPIO2
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+ */
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+
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++#include <linux/kernel.h>
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+ #include <linux/module.h>
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++#include <linux/types.h>
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++#include <linux/platform_device.h>
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++#include <linux/gpio.h>
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+
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+ #include <asm/mach-au1x00/au1000.h>
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+-#include <asm/gpio.h>
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++#include <asm/mach-au1x00/gpio.h>
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+
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+-#define gpio1 sys
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+-#if !defined(CONFIG_SOC_AU1000)
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++struct au1000_gpio_chip {
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++ struct gpio_chip chip;
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++ void __iomem *regbase;
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++};
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+
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+-static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE;
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++#if !defined(CONFIG_SOC_AU1000)
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+ #define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
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+
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+-static int au1xxx_gpio2_read(unsigned gpio)
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++/*
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++ * Return GPIO bank 2 level
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++ */
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++static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
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+ {
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+- gpio -= AU1XXX_GPIO_BASE;
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+- return ((gpio2->pinstate >> gpio) & 0x01);
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++ u32 mask = 1 << offset;
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++ struct au1000_gpio_chip *gpch;
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++
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++ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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++ return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
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+ }
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+
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+-static void au1xxx_gpio2_write(unsigned gpio, int value)
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++/*
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++ * Set output GPIO bank 2 level
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++ */
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++static void au1000_gpio2_set(struct gpio_chip *chip,
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++ unsigned offset, int value)
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+ {
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+- gpio -= AU1XXX_GPIO_BASE;
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+-
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+- gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
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++ u32 mask = (!!value) << offset;
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++ struct au1000_gpio_chip *gpch;
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++ unsigned long flags;
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++
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++ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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++
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++ local_irq_save(flags);
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++ writel((GPIO2_OUTPUT_ENABLE_MASK << offset) | mask,
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++ gpch->regbase + AU1000_GPIO2_OUT);
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++ local_irq_restore(flags);
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+ }
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+
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+-static int au1xxx_gpio2_direction_input(unsigned gpio)
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++/*
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++ * Set GPIO bank 2 direction to input
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++ */
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++static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
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+ {
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+- gpio -= AU1XXX_GPIO_BASE;
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+- gpio2->dir &= ~(0x01 << gpio);
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++ unsigned long flags;
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++ u32 mask = 1 << offset;
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++ u32 value;
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++ struct au1000_gpio_chip *gpch;
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++ void __iomem *gpdr;
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++
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++ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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++ gpdr = gpch->regbase + AU1000_GPIO2_DIR;
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++
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++ local_irq_save(flags);
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++ value = readl(gpdr);
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++ value &= ~mask;
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++ writel(value, gpdr);
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++ local_irq_restore(flags);
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++
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+ return 0;
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+ }
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+
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+-static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
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++/*
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++ * Set GPIO bank2 direction to output
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++ */
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++static int au1000_gpio2_direction_output(struct gpio_chip *chip,
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++ unsigned offset, int value)
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+ {
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+- gpio -= AU1XXX_GPIO_BASE;
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+- gpio2->dir |= 0x01 << gpio;
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+- gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
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++ unsigned long flags;
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++ u32 mask = 1 << offset;
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++ u32 tmp;
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++ struct au1000_gpio_chip *gpch;
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++ void __iomem *gpdr;
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++
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++ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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++ gpdr = gpch->regbase + AU1000_GPIO2_DIR;
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++
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++ local_irq_save(flags);
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++ tmp = readl(gpdr);
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++ tmp |= mask;
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++ writel(tmp, gpdr);
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++ mask = (!!value) << offset;
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++ writel((GPIO2_OUTPUT_ENABLE_MASK << offset) | mask,
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++ gpch->regbase + AU1000_GPIO2_OUT);
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++ local_irq_restore(flags);
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++
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+ return 0;
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+ }
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+-
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+ #endif /* !defined(CONFIG_SOC_AU1000) */
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+
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+-static int au1xxx_gpio1_read(unsigned gpio)
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++/*
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++ * Return GPIO bank 2 level
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++ */
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++static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
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+ {
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+- return (gpio1->pinstaterd >> gpio) & 0x01;
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++ u32 mask = 1 << offset;
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++ struct au1000_gpio_chip *gpch;
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++
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++ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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++ return readl(gpch->regbase + 0x0110) & mask;
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+ }
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+
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+-static void au1xxx_gpio1_write(unsigned gpio, int value)
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++/*
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++ * Set GPIO bank 1 level
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++ */
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++static void au1000_gpio1_set(struct gpio_chip *chip,
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++ unsigned offset, int value)
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+ {
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++ unsigned long flags;
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++ u32 mask = 1 << offset;
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++ struct au1000_gpio_chip *gpch;
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++
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++ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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++
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++ local_irq_save(flags);
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+ if (value)
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+- gpio1->outputset = (0x01 << gpio);
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++ writel(mask, gpch->regbase + 0x0108);
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+ else
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+- /* Output a zero */
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+- gpio1->outputclr = (0x01 << gpio);
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++ writel(mask, gpch->regbase + 0x010C);
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++ local_irq_restore(flags);
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+ }
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+
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+-static int au1xxx_gpio1_direction_input(unsigned gpio)
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++/*
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++ * Set GPIO bank 1 direction to input
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++ */
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++static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
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+ {
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+- gpio1->pininputen = (0x01 << gpio);
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+- return 0;
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+-}
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++ unsigned long flags;
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++ u32 mask = 1 << offset;
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++ u32 value;
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++ struct au1000_gpio_chip *gpch;
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++ void __iomem *gpdr;
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++
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++ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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++ gpdr = gpch->regbase + 0x0110;
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++
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++ local_irq_save(flags);
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++ value = readl(gpdr);
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++ value |= mask;
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++ writel(mask, gpdr);
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++ local_irq_restore(flags);
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+
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+-static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
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+-{
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+- gpio1->trioutclr = (0x01 & gpio);
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+- au1xxx_gpio1_write(gpio, value);
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+ return 0;
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+ }
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+
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+-int au1xxx_gpio_get_value(unsigned gpio)
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++/*
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++ * Set GPIO bank 1 direction to output
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++ */
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++static int au1000_gpio1_direction_output(struct gpio_chip *chip,
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++ unsigned offset, int value)
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+ {
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+- if (gpio >= AU1XXX_GPIO_BASE)
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+-#if defined(CONFIG_SOC_AU1000)
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+- return 0;
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+-#else
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+- return au1xxx_gpio2_read(gpio);
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+-#endif
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++ unsigned long flags;
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++ u32 mask = 1 << offset;
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++ u32 tmp;
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++ struct au1000_gpio_chip *gpch;
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++ void __iomem *gpdr;
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++
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++ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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++ gpdr = gpch->regbase + 0x0100;
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++
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++ local_irq_save(flags);
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++ tmp = readl(gpdr);
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++ writel(tmp, gpdr);
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++ if (value)
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++ writel(mask, gpch->regbase + 0x0108);
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+ else
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+- return au1xxx_gpio1_read(gpio);
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+-}
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+-EXPORT_SYMBOL(au1xxx_gpio_get_value);
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++ writel(mask, gpch->regbase + 0x0108);
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++ local_irq_restore(flags);
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+
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+-void au1xxx_gpio_set_value(unsigned gpio, int value)
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+-{
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+- if (gpio >= AU1XXX_GPIO_BASE)
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+-#if defined(CONFIG_SOC_AU1000)
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+- ;
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+-#else
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+- au1xxx_gpio2_write(gpio, value);
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+-#endif
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+- else
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+- au1xxx_gpio1_write(gpio, value);
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++ return 0;
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+ }
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+-EXPORT_SYMBOL(au1xxx_gpio_set_value);
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+
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+-int au1xxx_gpio_direction_input(unsigned gpio)
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+-{
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+- if (gpio >= AU1XXX_GPIO_BASE)
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+-#if defined(CONFIG_SOC_AU1000)
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+- return -ENODEV;
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+-#else
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+- return au1xxx_gpio2_direction_input(gpio);
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++struct au1000_gpio_chip au1000_gpio_chip[] = {
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++ [0] = {
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++ .regbase = (void __iomem *)SYS_BASE,
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++ .chip = {
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++ .label = "au1000-gpio1",
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++ .direction_input = au1000_gpio1_direction_input,
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++ .direction_output = au1000_gpio1_direction_output,
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++ .get = au1000_gpio1_get,
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++ .set = au1000_gpio1_set,
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++ .base = 0,
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++ .ngpio = 32,
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++ },
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++ },
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++#if !defined(CONFIG_SOC_AU1000)
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++ [1] = {
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++ .regbase = (void __iomem *)GPIO2_BASE,
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++ .chip = {
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++ .label = "au1000-gpio2",
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++ .direction_input = au1000_gpio2_direction_input,
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++ .direction_output = au1000_gpio2_direction_output,
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++ .get = au1000_gpio2_get,
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++ .set = au1000_gpio2_set,
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++ .base = AU1XXX_GPIO_BASE,
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++ .ngpio = 32,
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++ },
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++ },
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+ #endif
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++};
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+
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+- return au1xxx_gpio1_direction_input(gpio);
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+-}
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+-EXPORT_SYMBOL(au1xxx_gpio_direction_input);
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+-
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+-int au1xxx_gpio_direction_output(unsigned gpio, int value)
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++int __init au1000_gpio_init(void)
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+ {
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+- if (gpio >= AU1XXX_GPIO_BASE)
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+-#if defined(CONFIG_SOC_AU1000)
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+- return -ENODEV;
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+-#else
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+- return au1xxx_gpio2_direction_output(gpio, value);
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++ gpiochip_add(&au1000_gpio_chip[0].chip);
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++#if !defined(CONFIG_SOC_AU1000)
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++ gpiochip_add(&au1000_gpio_chip[1].chip);
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+ #endif
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+
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+- return au1xxx_gpio1_direction_output(gpio, value);
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++ return 0;
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+ }
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+-EXPORT_SYMBOL(au1xxx_gpio_direction_output);
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++arch_initcall(au1000_gpio_init);
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+--- a/arch/mips/include/asm/mach-au1x00/gpio.h
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++++ b/arch/mips/include/asm/mach-au1x00/gpio.h
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+@@ -1,69 +1,21 @@
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+ #ifndef _AU1XXX_GPIO_H_
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+ #define _AU1XXX_GPIO_H_
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+
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+-#include <linux/types.h>
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+-
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+ #define AU1XXX_GPIO_BASE 200
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+
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+-struct au1x00_gpio2 {
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+- u32 dir;
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+- u32 reserved;
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+- u32 output;
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+- u32 pinstate;
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+- u32 inten;
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+- u32 enable;
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+-};
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+-
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+-extern int au1xxx_gpio_get_value(unsigned gpio);
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+-extern void au1xxx_gpio_set_value(unsigned gpio, int value);
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+-extern int au1xxx_gpio_direction_input(unsigned gpio);
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+-extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
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+-
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+-
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+-/* Wrappers for the arch-neutral GPIO API */
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+-
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+-static inline int gpio_request(unsigned gpio, const char *label)
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+-{
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+- /* Not yet implemented */
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+- return 0;
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+-}
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+-
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+-static inline void gpio_free(unsigned gpio)
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+-{
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+- /* Not yet implemented */
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+-}
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+-
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+-static inline int gpio_direction_input(unsigned gpio)
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+-{
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+- return au1xxx_gpio_direction_input(gpio);
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+-}
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+-
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+-static inline int gpio_direction_output(unsigned gpio, int value)
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+-{
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+- return au1xxx_gpio_direction_output(gpio, value);
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+-}
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+-
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+-static inline int gpio_get_value(unsigned gpio)
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+-{
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+- return au1xxx_gpio_get_value(gpio);
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+-}
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+-
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+-static inline void gpio_set_value(unsigned gpio, int value)
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+-{
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+- au1xxx_gpio_set_value(gpio, value);
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+-}
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+-
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+-static inline int gpio_to_irq(unsigned gpio)
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+-{
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+- return gpio;
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+-}
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+-
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+-static inline int irq_to_gpio(unsigned irq)
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+-{
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+- return irq;
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+-}
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++#define AU1000_GPIO2_DIR 0x00
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++#define AU1000_GPIO2_RSVD 0x04
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++#define AU1000_GPIO2_OUT 0x08
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++#define AU1000_GPIO2_ST 0x0C
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++#define AU1000_GPIO2_INT 0x10
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++#define AU1000_GPIO2_EN 0x14
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++
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++#define gpio_get_value __gpio_get_value
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++#define gpio_set_value __gpio_set_value
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++
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++#define gpio_to_irq(gpio) NULL
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++#define irq_to_gpio(irq) NULL
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+
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+-/* For cansleep */
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+ #include <asm-generic/gpio.h>
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+
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+ #endif /* _AU1XXX_GPIO_H_ */
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Florian Fainelli