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@@ -0,0 +1,101 @@
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+From b11c5d1dc29e81326d1215011d19377737082aeb Mon Sep 17 00:00:00 2001
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+From: Daniel Schwierzeck <[email protected]>
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+Date: Wed, 1 Jul 2015 16:36:43 +0200
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+Subject: [PATCH] MIPS: change 'extern inline' to 'static inline'
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+
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+The kernel changed it a long time ago. Also this is now broken
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+on gcc-5.x.
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+
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+Reported-by: Andy Kennedy <[email protected]>
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+Signed-off-by: Daniel Schwierzeck <[email protected]>
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+---
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+ arch/mips/include/asm/io.h | 12 ++++++------
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+ arch/mips/include/asm/system.h | 6 +++---
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+ 2 files changed, 9 insertions(+), 9 deletions(-)
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+
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+diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
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+index 3fa37f5..a7ab087 100644
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+--- a/arch/mips/include/asm/io.h
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++++ b/arch/mips/include/asm/io.h
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+@@ -117,7 +117,7 @@ static inline void set_io_port_base(unsigned long base)
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+ * Change virtual addresses to physical addresses and vv.
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+ * These are trivial on the 1:1 Linux/MIPS mapping
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+ */
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+-extern inline phys_addr_t virt_to_phys(volatile void * address)
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++static inline phys_addr_t virt_to_phys(volatile void * address)
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+ {
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+ #ifndef CONFIG_64BIT
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+ return CPHYSADDR(address);
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+@@ -126,7 +126,7 @@ extern inline phys_addr_t virt_to_phys(volatile void * address)
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+ #endif
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+ }
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+
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+-extern inline void * phys_to_virt(unsigned long address)
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++static inline void * phys_to_virt(unsigned long address)
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+ {
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+ #ifndef CONFIG_64BIT
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+ return (void *)KSEG0ADDR(address);
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+@@ -138,7 +138,7 @@ extern inline void * phys_to_virt(unsigned long address)
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+ /*
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+ * IO bus memory addresses are also 1:1 with the physical address
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+ */
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+-extern inline unsigned long virt_to_bus(volatile void * address)
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++static inline unsigned long virt_to_bus(volatile void * address)
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+ {
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+ #ifndef CONFIG_64BIT
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+ return CPHYSADDR(address);
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+@@ -147,7 +147,7 @@ extern inline unsigned long virt_to_bus(volatile void * address)
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+ #endif
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+ }
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+
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+-extern inline void * bus_to_virt(unsigned long address)
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++static inline void * bus_to_virt(unsigned long address)
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+ {
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+ #ifndef CONFIG_64BIT
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+ return (void *)KSEG0ADDR(address);
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+@@ -165,12 +165,12 @@ extern unsigned long isa_slot_offset;
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+ extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
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+
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+ #if 0
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+-extern inline void *ioremap(unsigned long offset, unsigned long size)
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++static inline void *ioremap(unsigned long offset, unsigned long size)
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+ {
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+ return __ioremap(offset, size, _CACHE_UNCACHED);
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+ }
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+
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+-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
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++static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
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+ {
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+ return __ioremap(offset, size, _CACHE_UNCACHED);
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+ }
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+diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
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+index 7a28952..d56f73b 100644
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+--- a/arch/mips/include/asm/system.h
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++++ b/arch/mips/include/asm/system.h
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+@@ -22,7 +22,7 @@
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+ #include <linux/kernel.h>
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+ #endif
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+
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+-extern __inline__ void
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++static __inline__ void
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+ __sti(void)
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+ {
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+ __asm__ __volatile__(
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+@@ -46,7 +46,7 @@ __sti(void)
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+ * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
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+ * no nops at all.
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+ */
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+-extern __inline__ void
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++static __inline__ void
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+ __cli(void)
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+ {
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+ __asm__ __volatile__(
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+@@ -207,7 +207,7 @@ do { \
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+ * For 32 and 64 bit operands we can take advantage of ll and sc.
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+ * FIXME: This doesn't work for R3000 machines.
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+ */
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+-extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
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++static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
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+ {
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+ #ifdef CONFIG_CPU_HAS_LLSC
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+ unsigned long dummy;
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