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@@ -135,8 +135,7 @@
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+static void __init ap136_common_setup(void)
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+{
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+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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-
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--static int ap136_pci_plat_dev_init(struct pci_dev *dev)
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++
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+ ath79_register_m25p80(NULL);
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+
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+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
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@@ -151,7 +150,8 @@
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+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
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+
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+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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-+
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+
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+-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
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+ ath79_register_mdio(0, 0x0);
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+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
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+
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@@ -211,16 +211,16 @@
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+ /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
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+ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
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+ ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
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-
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-- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
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-- ath79_register_pci();
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++
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+ /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
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+ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
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+ ap136_ar8327_pad6_cfg.txclk_delay_en = true;
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+ ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
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+ ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
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+ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
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-+
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+
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+- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
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+- ath79_register_pci();
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+ ath79_eth0_pll_data.pll_1000 = 0x56000000;
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+ ath79_eth1_pll_data.pll_1000 = 0x03000101;
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+
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