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@@ -1,92 +0,0 @@
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-From 11aa9df4de06cc257327d783c5cb615989e87286 Mon Sep 17 00:00:00 2001
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-From: Maxime Ripard <[email protected]>
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-Date: Fri, 23 Jan 2015 15:18:27 +0100
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-Subject: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
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-
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-The NDDB register holds the data that are needed by the read and write
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-commands.
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-
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-However, during a read PIO access, the datasheet specifies that after each 32
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-bits read in that register, when BCH is enabled, we have to make sure that the
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-RDDREQ bit is set in the NDSR register.
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-
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-This fixes an issue that was seen on the Armada 385, and presumably other mvebu
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-SoCs, when a read on a newly erased page would end up in the driver reporting a
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-timeout from the NAND.
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-
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-Cc: <[email protected]> # v3.14
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-Signed-off-by: Maxime Ripard <[email protected]>
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----
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- drivers/mtd/nand/pxa3xx_nand.c | 45 ++++++++++++++++++++++++++++++++++++------
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- 1 file changed, 39 insertions(+), 6 deletions(-)
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-
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---- a/drivers/mtd/nand/pxa3xx_nand.c
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-+++ b/drivers/mtd/nand/pxa3xx_nand.c
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-@@ -23,6 +23,7 @@
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- #include <linux/mtd/partitions.h>
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- #include <linux/io.h>
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- #include <linux/irq.h>
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-+#include <linux/jiffies.h>
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- #include <linux/slab.h>
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- #include <linux/of.h>
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- #include <linux/of_device.h>
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-@@ -480,6 +481,38 @@ static void disable_int(struct pxa3xx_na
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- nand_writel(info, NDCR, ndcr | int_mask);
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- }
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-
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-+static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
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-+{
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-+ u32 *dst = (u32 *)data;
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-+
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-+ if (info->ecc_bch) {
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-+ while (len--) {
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-+ u32 timeout;
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-+
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-+ *dst++ = nand_readl(info, NDDB);
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-+
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-+ /*
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-+ * According to the datasheet, when reading
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-+ * from NDDB with BCH enabled, after each 32
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-+ * bits reads, we have to make sure that the
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-+ * NDSR.RDDREQ bit is set
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-+ */
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-+ timeout = jiffies + msecs_to_jiffies(5);
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-+ while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
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-+ if (!time_before(jiffies, timeout)) {
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-+ dev_err(&info->pdev->dev,
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-+ "Timeout on RDDREQ while draining the FIFO\n");
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-+ return;
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-+ }
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-+
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-+ cpu_relax();
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-+ }
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-+ }
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-+ } else {
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-+ __raw_readsl(info->mmio_base + NDDB, data, len);
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-+ }
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-+}
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-+
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- static void handle_data_pio(struct pxa3xx_nand_info *info)
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- {
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- unsigned int do_bytes = min(info->data_size, info->chunk_size);
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-@@ -496,14 +529,14 @@ static void handle_data_pio(struct pxa3x
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- DIV_ROUND_UP(info->oob_size, 4));
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- break;
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- case STATE_PIO_READING:
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-- __raw_readsl(info->mmio_base + NDDB,
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-- info->data_buff + info->data_buff_pos,
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-- DIV_ROUND_UP(do_bytes, 4));
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-+ drain_fifo(info,
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-+ info->data_buff + info->data_buff_pos,
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-+ DIV_ROUND_UP(do_bytes, 4));
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-
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- if (info->oob_size > 0)
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-- __raw_readsl(info->mmio_base + NDDB,
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-- info->oob_buff + info->oob_buff_pos,
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-- DIV_ROUND_UP(info->oob_size, 4));
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-+ drain_fifo(info,
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-+ info->oob_buff + info->oob_buff_pos,
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-+ DIV_ROUND_UP(info->oob_size, 4));
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- break;
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- default:
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- dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
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