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@@ -0,0 +1,425 @@
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+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
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+Subject: [PATCH] Revert "PCI: iproc: Add PAXC interface support"
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+MIME-Version: 1.0
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+Content-Type: text/plain; charset=UTF-8
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+Content-Transfer-Encoding: 8bit
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+
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+Adding PAXC support fixed all "invalid BAR" firmware bug messages but
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+also broke finding extra buses and attached devices. This affected
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+e.g. Netgear R8000 which has 2 (out of 3) BCM43602 cards connected to
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+the 2nd "PCIe Gen 2" controller. None of them is detected with PAXC
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+code.
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+
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+This reverts commit 943ebae781f519ecfecbfa1b997f15f59116e41d.
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+
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+Signed-off-by: Rafał Miłecki <[email protected]>
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+---
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+ drivers/pci/host/pcie-iproc-platform.c | 24 +---
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+ drivers/pci/host/pcie-iproc.c | 202 ++++++---------------------------
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+ drivers/pci/host/pcie-iproc.h | 19 ----
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+ 3 files changed, 40 insertions(+), 205 deletions(-)
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+
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+--- a/drivers/pci/host/pcie-iproc-platform.c
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++++ b/drivers/pci/host/pcie-iproc-platform.c
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+@@ -26,21 +26,8 @@
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+
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+ #include "pcie-iproc.h"
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+
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+-static const struct of_device_id iproc_pcie_of_match_table[] = {
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+- {
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+- .compatible = "brcm,iproc-pcie",
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+- .data = (int *)IPROC_PCIE_PAXB,
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+- }, {
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+- .compatible = "brcm,iproc-pcie-paxc",
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+- .data = (int *)IPROC_PCIE_PAXC,
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+- },
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+- { /* sentinel */ }
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+-};
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+-MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
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+-
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+ static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
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+ {
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+- const struct of_device_id *of_id;
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+ struct iproc_pcie *pcie;
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+ struct device_node *np = pdev->dev.of_node;
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+ struct resource reg;
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+@@ -48,16 +35,11 @@ static int iproc_pcie_pltfm_probe(struct
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+ LIST_HEAD(res);
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+ int ret;
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+
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+- of_id = of_match_device(iproc_pcie_of_match_table, &pdev->dev);
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+- if (!of_id)
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+- return -EINVAL;
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+-
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+ pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
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+ if (!pcie)
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+ return -ENOMEM;
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+
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+ pcie->dev = &pdev->dev;
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+- pcie->type = (enum iproc_pcie_type)of_id->data;
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+ platform_set_drvdata(pdev, pcie);
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+
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+ ret = of_address_to_resource(np, 0, ®);
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+@@ -133,6 +115,12 @@ static int iproc_pcie_pltfm_remove(struc
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+ return iproc_pcie_remove(pcie);
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+ }
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+
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++static const struct of_device_id iproc_pcie_of_match_table[] = {
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++ { .compatible = "brcm,iproc-pcie", },
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++ { /* sentinel */ }
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++};
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++MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
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++
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+ static struct platform_driver iproc_pcie_pltfm_driver = {
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+ .driver = {
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+ .name = "iproc-pcie",
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+--- a/drivers/pci/host/pcie-iproc.c
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++++ b/drivers/pci/host/pcie-iproc.c
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+@@ -30,16 +30,20 @@
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+
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+ #include "pcie-iproc.h"
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+
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++#define CLK_CONTROL_OFFSET 0x000
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+ #define EP_PERST_SOURCE_SELECT_SHIFT 2
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+ #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
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+ #define EP_MODE_SURVIVE_PERST_SHIFT 1
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+ #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
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+ #define RC_PCIE_RST_OUTPUT_SHIFT 0
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+ #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
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+-#define PAXC_RESET_MASK 0x7f
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+
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++#define CFG_IND_ADDR_OFFSET 0x120
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+ #define CFG_IND_ADDR_MASK 0x00001ffc
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+
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++#define CFG_IND_DATA_OFFSET 0x124
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++
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++#define CFG_ADDR_OFFSET 0x1f8
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+ #define CFG_ADDR_BUS_NUM_SHIFT 20
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+ #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
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+ #define CFG_ADDR_DEV_NUM_SHIFT 15
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+@@ -51,8 +55,12 @@
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+ #define CFG_ADDR_CFG_TYPE_SHIFT 0
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+ #define CFG_ADDR_CFG_TYPE_MASK 0x00000003
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+
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++#define CFG_DATA_OFFSET 0x1fc
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++
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++#define SYS_RC_INTX_EN 0x330
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+ #define SYS_RC_INTX_MASK 0xf
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+
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++#define PCIE_LINK_STATUS_OFFSET 0xf0c
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+ #define PCIE_PHYLINKUP_SHIFT 3
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+ #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
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+ #define PCIE_DL_ACTIVE_SHIFT 2
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+@@ -63,54 +71,12 @@
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+ #define OARR_SIZE_CFG_SHIFT 1
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+ #define OARR_SIZE_CFG BIT(OARR_SIZE_CFG_SHIFT)
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+
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+-#define MAX_NUM_OB_WINDOWS 2
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+-#define MAX_NUM_PAXC_PF 4
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+-
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+-#define IPROC_PCIE_REG_INVALID 0xffff
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++#define OARR_LO(window) (0xd20 + (window) * 8)
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++#define OARR_HI(window) (0xd24 + (window) * 8)
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++#define OMAP_LO(window) (0xd40 + (window) * 8)
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++#define OMAP_HI(window) (0xd44 + (window) * 8)
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+
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+-enum iproc_pcie_reg {
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+- IPROC_PCIE_CLK_CTRL = 0,
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+- IPROC_PCIE_CFG_IND_ADDR,
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+- IPROC_PCIE_CFG_IND_DATA,
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+- IPROC_PCIE_CFG_ADDR,
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+- IPROC_PCIE_CFG_DATA,
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+- IPROC_PCIE_INTX_EN,
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+- IPROC_PCIE_OARR_LO,
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+- IPROC_PCIE_OARR_HI,
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+- IPROC_PCIE_OMAP_LO,
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+- IPROC_PCIE_OMAP_HI,
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+- IPROC_PCIE_LINK_STATUS,
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+-};
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+-
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+-/* iProc PCIe PAXB registers */
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+-static const u16 iproc_pcie_reg_paxb[] = {
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+- [IPROC_PCIE_CLK_CTRL] = 0x000,
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+- [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
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+- [IPROC_PCIE_CFG_IND_DATA] = 0x124,
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+- [IPROC_PCIE_CFG_ADDR] = 0x1f8,
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+- [IPROC_PCIE_CFG_DATA] = 0x1fc,
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+- [IPROC_PCIE_INTX_EN] = 0x330,
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+- [IPROC_PCIE_OARR_LO] = 0xd20,
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+- [IPROC_PCIE_OARR_HI] = 0xd24,
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+- [IPROC_PCIE_OMAP_LO] = 0xd40,
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+- [IPROC_PCIE_OMAP_HI] = 0xd44,
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+- [IPROC_PCIE_LINK_STATUS] = 0xf0c,
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+-};
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+-
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+-/* iProc PCIe PAXC v1 registers */
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+-static const u16 iproc_pcie_reg_paxc[] = {
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+- [IPROC_PCIE_CLK_CTRL] = 0x000,
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+- [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
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+- [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
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+- [IPROC_PCIE_CFG_ADDR] = 0x1f8,
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+- [IPROC_PCIE_CFG_DATA] = 0x1fc,
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+- [IPROC_PCIE_INTX_EN] = IPROC_PCIE_REG_INVALID,
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+- [IPROC_PCIE_OARR_LO] = IPROC_PCIE_REG_INVALID,
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+- [IPROC_PCIE_OARR_HI] = IPROC_PCIE_REG_INVALID,
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+- [IPROC_PCIE_OMAP_LO] = IPROC_PCIE_REG_INVALID,
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+- [IPROC_PCIE_OMAP_HI] = IPROC_PCIE_REG_INVALID,
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+- [IPROC_PCIE_LINK_STATUS] = IPROC_PCIE_REG_INVALID,
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+-};
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++#define MAX_NUM_OB_WINDOWS 2
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+
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+ static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
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+ {
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+@@ -125,65 +91,6 @@ static inline struct iproc_pcie *iproc_d
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+ return pcie;
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+ }
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+
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+-static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
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+-{
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+- return !!(reg_offset == IPROC_PCIE_REG_INVALID);
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+-}
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+-
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+-static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
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+- enum iproc_pcie_reg reg)
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+-{
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+- return pcie->reg_offsets[reg];
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+-}
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+-
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+-static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
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+- enum iproc_pcie_reg reg)
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+-{
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+- u16 offset = iproc_pcie_reg_offset(pcie, reg);
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+-
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+- if (iproc_pcie_reg_is_invalid(offset))
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+- return 0;
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+-
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+- return readl(pcie->base + offset);
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+-}
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+-
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+-static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
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+- enum iproc_pcie_reg reg, u32 val)
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+-{
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+- u16 offset = iproc_pcie_reg_offset(pcie, reg);
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+-
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+- if (iproc_pcie_reg_is_invalid(offset))
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+- return;
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+-
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+- writel(val, pcie->base + offset);
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+-}
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+-
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+-static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie,
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+- enum iproc_pcie_reg reg,
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+- unsigned window, u32 val)
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+-{
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+- u16 offset = iproc_pcie_reg_offset(pcie, reg);
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+-
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+- if (iproc_pcie_reg_is_invalid(offset))
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+- return;
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+-
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+- writel(val, pcie->base + offset + (window * 8));
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+-}
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+-
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+-static inline bool iproc_pcie_device_is_valid(struct iproc_pcie *pcie,
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+- unsigned int slot,
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+- unsigned int fn)
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+-{
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+- if (slot > 0)
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+- return false;
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+-
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+- /* PAXC can only support limited number of functions */
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+- if (pcie->type == IPROC_PCIE_PAXC && fn >= MAX_NUM_PAXC_PF)
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+- return false;
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+-
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+- return true;
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+-}
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+-
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+ /**
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+ * Note access to the configuration registers are protected at the higher layer
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+ * by 'pci_lock' in drivers/pci/access.c
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+@@ -197,34 +104,28 @@ static void __iomem *iproc_pcie_map_cfg_
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+ unsigned fn = PCI_FUNC(devfn);
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+ unsigned busno = bus->number;
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+ u32 val;
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+- u16 offset;
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+-
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+- if (!iproc_pcie_device_is_valid(pcie, slot, fn))
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+- return NULL;
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+
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+ /* root complex access */
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+ if (busno == 0) {
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+- iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
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+- where & CFG_IND_ADDR_MASK);
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+- offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
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+- if (iproc_pcie_reg_is_invalid(offset))
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++ if (slot >= 1)
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+ return NULL;
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+- else
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+- return (pcie->base + offset);
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++ writel(where & CFG_IND_ADDR_MASK,
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++ pcie->base + CFG_IND_ADDR_OFFSET);
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++ return (pcie->base + CFG_IND_DATA_OFFSET);
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+ }
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+
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++ if (fn > 1)
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++ return NULL;
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++
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+ /* EP device access */
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+ val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
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+ (slot << CFG_ADDR_DEV_NUM_SHIFT) |
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+ (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
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+ (where & CFG_ADDR_REG_NUM_MASK) |
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+ (1 & CFG_ADDR_CFG_TYPE_MASK);
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+- iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
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+- offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
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+- if (iproc_pcie_reg_is_invalid(offset))
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+- return NULL;
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+- else
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+- return (pcie->base + offset);
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++ writel(val, pcie->base + CFG_ADDR_OFFSET);
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++
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++ return (pcie->base + CFG_DATA_OFFSET);
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+ }
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+
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+ static struct pci_ops iproc_pcie_ops = {
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+@@ -237,29 +138,18 @@ static void iproc_pcie_reset(struct ipro
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+ {
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+ u32 val;
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+
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+- if (pcie->type == IPROC_PCIE_PAXC) {
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+- val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
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+- val &= ~PAXC_RESET_MASK;
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+- iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
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+- udelay(100);
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+- val |= PAXC_RESET_MASK;
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+- iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
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+- udelay(100);
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+- return;
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+- }
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+-
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+ /*
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+ * Select perst_b signal as reset source. Put the device into reset,
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+ * and then bring it out of reset
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+ */
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+- val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
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++ val = readl(pcie->base + CLK_CONTROL_OFFSET);
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+ val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
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+ ~RC_PCIE_RST_OUTPUT;
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+- iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
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++ writel(val, pcie->base + CLK_CONTROL_OFFSET);
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+ udelay(250);
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+
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+ val |= RC_PCIE_RST_OUTPUT;
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+- iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
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++ writel(val, pcie->base + CLK_CONTROL_OFFSET);
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+ msleep(100);
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+ }
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+
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+@@ -270,14 +160,7 @@ static int iproc_pcie_check_link(struct
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+ u16 pos, link_status;
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+ bool link_is_active = false;
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+
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+- /*
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+- * PAXC connects to emulated endpoint devices directly and does not
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+- * have a Serdes. Therefore skip the link detection logic here.
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+- */
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+- if (pcie->type == IPROC_PCIE_PAXC)
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+- return 0;
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+-
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+- val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
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++ val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET);
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+ if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
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+ dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
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+ return -ENODEV;
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+@@ -338,7 +221,7 @@ static int iproc_pcie_check_link(struct
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+
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+ static void iproc_pcie_enable(struct iproc_pcie *pcie)
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+ {
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+- iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
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++ writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
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+ }
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+
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+ /**
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+@@ -389,15 +272,11 @@ static int iproc_pcie_setup_ob(struct ip
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+ axi_addr -= ob->axi_offset;
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+
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+ for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
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+- iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_LO, i,
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+- lower_32_bits(axi_addr) | OARR_VALID |
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+- (ob->set_oarr_size ? 1 : 0));
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+- iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_HI, i,
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+- upper_32_bits(axi_addr));
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+- iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_LO, i,
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+- lower_32_bits(pci_addr));
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+- iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_HI, i,
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+- upper_32_bits(pci_addr));
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++ writel(lower_32_bits(axi_addr) | OARR_VALID |
|
|
|
++ (ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i));
|
|
|
++ writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i));
|
|
|
++ writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i));
|
|
|
++ writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i));
|
|
|
+
|
|
|
+ size -= ob->window_size;
|
|
|
+ if (size == 0)
|
|
|
+@@ -481,19 +360,6 @@ int iproc_pcie_setup(struct iproc_pcie *
|
|
|
+ goto err_exit_phy;
|
|
|
+ }
|
|
|
+
|
|
|
+- switch (pcie->type) {
|
|
|
+- case IPROC_PCIE_PAXB:
|
|
|
+- pcie->reg_offsets = iproc_pcie_reg_paxb;
|
|
|
+- break;
|
|
|
+- case IPROC_PCIE_PAXC:
|
|
|
+- pcie->reg_offsets = iproc_pcie_reg_paxc;
|
|
|
+- break;
|
|
|
+- default:
|
|
|
+- dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
|
|
|
+- ret = -EINVAL;
|
|
|
+- goto err_power_off_phy;
|
|
|
+- }
|
|
|
+-
|
|
|
+ iproc_pcie_reset(pcie);
|
|
|
+
|
|
|
+ if (pcie->need_ob_cfg) {
|
|
|
+--- a/drivers/pci/host/pcie-iproc.h
|
|
|
++++ b/drivers/pci/host/pcie-iproc.h
|
|
|
+@@ -15,20 +15,6 @@
|
|
|
+ #define _PCIE_IPROC_H
|
|
|
+
|
|
|
+ /**
|
|
|
+- * iProc PCIe interface type
|
|
|
+- *
|
|
|
+- * PAXB is the wrapper used in root complex that can be connected to an
|
|
|
+- * external endpoint device.
|
|
|
+- *
|
|
|
+- * PAXC is the wrapper used in root complex dedicated for internal emulated
|
|
|
+- * endpoint devices.
|
|
|
+- */
|
|
|
+-enum iproc_pcie_type {
|
|
|
+- IPROC_PCIE_PAXB = 0,
|
|
|
+- IPROC_PCIE_PAXC,
|
|
|
+-};
|
|
|
+-
|
|
|
+-/**
|
|
|
+ * iProc PCIe outbound mapping
|
|
|
+ * @set_oarr_size: indicates the OARR size bit needs to be set
|
|
|
+ * @axi_offset: offset from the AXI address to the internal address used by
|
|
|
+@@ -45,10 +31,7 @@ struct iproc_msi;
|
|
|
+
|
|
|
+ /**
|
|
|
+ * iProc PCIe device
|
|
|
+- *
|
|
|
+ * @dev: pointer to device data structure
|
|
|
+- * @type: iProc PCIe interface type
|
|
|
+- * @reg_offsets: register offsets
|
|
|
+ * @base: PCIe host controller I/O register base
|
|
|
+ * @base_addr: PCIe host controller register base physical address
|
|
|
+ * @sysdata: Per PCI controller data (ARM-specific)
|
|
|
+@@ -61,8 +44,6 @@ struct iproc_msi;
|
|
|
+ */
|
|
|
+ struct iproc_pcie {
|
|
|
+ struct device *dev;
|
|
|
+- enum iproc_pcie_type type;
|
|
|
+- const u16 *reg_offsets;
|
|
|
+ void __iomem *base;
|
|
|
+ phys_addr_t base_addr;
|
|
|
+ #ifdef CONFIG_ARM
|
Rafał Miłecki