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@@ -0,0 +1,825 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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+/*
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+ * BCM6348 PCI Controller Driver
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+ *
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+ * Copyright (C) 2020 Álvaro Fernández Rojas <[email protected]>
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+ * Copyright (C) 2015 Jonas Gorski <[email protected]>
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+ * Copyright (C) 2008 Maxime Bizon <[email protected]>
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/init.h>
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+#include <linux/delay.h>
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+#include <linux/kernel.h>
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+#include <linux/memblock.h>
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+#include <linux/mm.h>
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+#include <linux/of_address.h>
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+#include <linux/of_gpio.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_pci.h>
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+#include <linux/of_platform.h>
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+#include <linux/pci.h>
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+#include <linux/reset.h>
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+#include <linux/types.h>
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+#include <linux/vmalloc.h>
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+
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+#include "../pci.h"
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+
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+#define CARDBUS_DUMMY_ID 0x6348
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+#define CARDBUS_PCI_IDSEL 0x8
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+#define FAKE_CB_BRIDGE_SLOT 0x1e
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+
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+#define BCMPCI_REG_TIMERS 0x40
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+#define REG_TIMER_TRDY_SHIFT 0
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+#define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
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+#define REG_TIMER_RETRY_SHIFT 8
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+#define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
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+
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+#define MPI_SP0_RANGE_REG 0x100
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+#define MPI_SP0_REMAP_REG 0x104
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+#define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
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+#define MPI_SP1_RANGE_REG 0x10C
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+#define MPI_SP1_REMAP_REG 0x110
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+#define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
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+
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+#define MPI_L2PCFG_REG 0x11c
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+#define MPI_L2PCFG_CFG_TYPE_SHIFT 0
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+#define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
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+#define MPI_L2PCFG_REG_SHIFT 2
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+#define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
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+#define MPI_L2PCFG_FUNC_SHIFT 8
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+#define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
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+#define MPI_L2PCFG_DEVNUM_SHIFT 11
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+#define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
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+#define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
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+#define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
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+
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+#define MPI_L2PMEMRANGE1_REG 0x120
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+#define MPI_L2PMEMBASE1_REG 0x124
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+#define MPI_L2PMEMREMAP1_REG 0x128
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+#define MPI_L2PMEMRANGE2_REG 0x12C
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+#define MPI_L2PMEMBASE2_REG 0x130
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+#define MPI_L2PMEMREMAP2_REG 0x134
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+#define MPI_L2PIORANGE_REG 0x138
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+#define MPI_L2PIOBASE_REG 0x13C
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+#define MPI_L2PIOREMAP_REG 0x140
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+#define MPI_L2P_BASE_MASK (0xffff8000)
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+#define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
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+#define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
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+
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+#define MPI_PCIMODESEL_REG 0x144
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+#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
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+#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
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+#define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
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+#define MPI_PCIMODESEL_PREFETCH_SHIFT 4
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+#define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
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+
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+#define MPI_LOCBUSCTL_REG 0x14c
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+#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
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+#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
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+
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+#define MPI_LOCINT_REG 0x150
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+#define MPI_LOCINT_MASK(x) (1 << (x + 16))
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+#define MPI_LOCINT_STAT(x) (1 << (x))
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+#define MPI_LOCINT_DIR_FAILED 6
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+#define MPI_LOCINT_EXT_PCI_INT 7
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+#define MPI_LOCINT_SERR 8
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+#define MPI_LOCINT_CSERR 9
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+
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+#define MPI_PCICFGCTL_REG 0x178
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+#define MPI_PCICFGCTL_CFGADDR_SHIFT 2
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+#define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
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+#define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
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+
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+#define MPI_PCICFGDATA_REG 0x17c
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+
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+#define PCMCIA_OFFSET 0x54
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+
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+#define PCMCIA_C1_REG 0x0
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+#define PCMCIA_C1_CD1_MASK (1 << 0)
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+#define PCMCIA_C1_CD2_MASK (1 << 1)
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+#define PCMCIA_C1_VS1_MASK (1 << 2)
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+#define PCMCIA_C1_VS2_MASK (1 << 3)
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+#define PCMCIA_C1_VS1OE_MASK (1 << 6)
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+#define PCMCIA_C1_VS2OE_MASK (1 << 7)
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+#define PCMCIA_C1_CBIDSEL_SHIFT (8)
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+#define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
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+#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
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+#define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
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+#define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
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+#define PCMCIA_C1_RESET_MASK (1 << 18)
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+
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+#ifdef CONFIG_CARDBUS
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+struct bcm6348_cb {
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+ u16 pci_command;
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+ u8 cb_latency;
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+ u8 subordinate_busn;
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+ u8 cardbus_busn;
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+ u8 pci_busn;
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+ int bus_assigned;
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+ u16 bridge_control;
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+
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+ u32 mem_base0;
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+ u32 mem_limit0;
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+ u32 mem_base1;
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+ u32 mem_limit1;
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+
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+ u32 io_base0;
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+ u32 io_limit0;
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+ u32 io_base1;
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+ u32 io_limit1;
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+};
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+#endif /* CONFIG_CARDBUS */
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+
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+struct bcm6348_pci {
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+ void __iomem *pci;
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+ void __iomem *pcmcia;
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+ void __iomem *io;
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+ int irq;
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+ struct reset_control *reset;
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+ bool remap;
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+#ifdef CONFIG_CARDBUS
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+ struct bcm6348_cb cb;
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+ int cb_bus;
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+#endif /* CONFIG_CARDBUS */
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+};
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+
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+static struct bcm6348_pci bcm6348_pci;
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+
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+extern int bmips_pci_irq;
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+
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+static u32 bcm6348_int_cfg_readl(u32 reg)
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+{
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+ struct bcm6348_pci *priv = &bcm6348_pci;
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+ u32 tmp;
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+
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+ tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
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+ tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
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+ __raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
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+ iob();
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+ return __raw_readl(priv->pci + MPI_PCICFGDATA_REG);
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+}
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+
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+static void bcm6348_int_cfg_writel(u32 val, u32 reg)
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+{
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+ struct bcm6348_pci *priv = &bcm6348_pci;
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+ u32 tmp;
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+
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+ tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
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+ tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
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+ __raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
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+ __raw_writel(val, priv->pci + MPI_PCICFGDATA_REG);
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+}
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+
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+/*
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+ * swizzle 32bits data to return only the needed part
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+ */
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+static int postprocess_read(u32 data, int where, unsigned int size)
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+{
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+ u32 ret = 0;
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+
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+ switch (size) {
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+ case 1:
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+ ret = (data >> ((where & 3) << 3)) & 0xff;
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+ break;
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+ case 2:
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+ ret = (data >> ((where & 3) << 3)) & 0xffff;
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+ break;
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+ case 4:
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+ ret = data;
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+ break;
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+ }
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+
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+ return ret;
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+}
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+
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+static int preprocess_write(u32 orig_data, u32 val, int where,
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+ unsigned int size)
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+{
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+ u32 ret = 0;
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+
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+ switch (size) {
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+ case 1:
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+ ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
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+ (val << ((where & 3) << 3));
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+ break;
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+ case 2:
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+ ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
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+ (val << ((where & 3) << 3));
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+ break;
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+ case 4:
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+ ret = val;
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+ break;
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+ }
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+
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+ return ret;
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+}
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+
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+static int bcm6348_setup_cfg_access(int type, unsigned int busn,
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+ unsigned int devfn, int where)
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+{
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+ struct bcm6348_pci *priv = &bcm6348_pci;
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+ unsigned int slot, func, reg;
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+ u32 val;
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+
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+ slot = PCI_SLOT(devfn);
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+ func = PCI_FUNC(devfn);
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+ reg = where >> 2;
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+
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+ /* sanity check */
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+ if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
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+ return 1;
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+
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+ if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
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+ return 1;
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+
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+ if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
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+ return 1;
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+
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+ /* ok, setup config access */
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+ val = (reg << MPI_L2PCFG_REG_SHIFT);
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+ val |= (func << MPI_L2PCFG_FUNC_SHIFT);
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+ val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
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+ val |= MPI_L2PCFG_CFG_USEREG_MASK;
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+ val |= MPI_L2PCFG_CFG_SEL_MASK;
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+ /* type 0 cycle for local bus, type 1 cycle for anything else */
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+ if (type != 0) {
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+ /* FIXME: how to specify bus ??? */
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+ val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
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+ }
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+ __raw_writel(val, priv->pci + MPI_L2PCFG_REG);
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+
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+ return 0;
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+}
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+
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+
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+static int bcm6348_do_cfg_read(int type, unsigned int busn,
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+ unsigned int devfn, int where, int size,
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+ u32 *val)
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+{
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+ struct bcm6348_pci *priv = &bcm6348_pci;
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+ u32 data;
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+
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+ /* two phase cycle, first we write address, then read data at
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+ * another location, caller already has a spinlock so no need
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+ * to add one here */
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+ if (bcm6348_setup_cfg_access(type, busn, devfn, where))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ iob();
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+ data = le32_to_cpu(__raw_readl(priv->io));
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+ /* restore IO space normal behaviour */
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+ __raw_writel(0, priv->pci + MPI_L2PCFG_REG);
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+
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+ *val = postprocess_read(data, where, size);
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static int bcm6348_do_cfg_write(int type, unsigned int busn,
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+ unsigned int devfn, int where, int size,
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+ u32 val)
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+{
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+ struct bcm6348_pci *priv = &bcm6348_pci;
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+ u32 data;
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+
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+ /* two phase cycle, first we write address, then write data to
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+ * another location, caller already has a spinlock so no need
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+ * to add one here */
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+ if (bcm6348_setup_cfg_access(type, busn, devfn, where))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ iob();
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+
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+ data = le32_to_cpu(__raw_readl(priv->io));
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+ data = preprocess_write(data, val, where, size);
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+
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+ __raw_writel(cpu_to_le32(data), priv->io);
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+ wmb();
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+ /* no way to know the access is done, we have to wait */
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+ udelay(500);
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+ /* restore IO space normal behaviour */
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+ __raw_writel(0, priv->pci + MPI_L2PCFG_REG);
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static int bcm6348_pci_read(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 *val)
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+{
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+ int type;
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+
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+ type = bus->parent ? 1 : 0;
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+
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+ if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ return bcm6348_do_cfg_read(type, bus->number, devfn,
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+ where, size, val);
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+}
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+
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+static int bcm6348_pci_write(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 val)
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+{
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+ int type;
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+
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+ type = bus->parent ? 1 : 0;
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+
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+ if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ return bcm6348_do_cfg_write(type, bus->number, devfn,
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+ where, size, val);
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+}
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+
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+static struct pci_ops bcm6348_pci_ops = {
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+ .read = bcm6348_pci_read,
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+ .write = bcm6348_pci_write,
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+};
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+
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+static struct resource bcm6348_pci_io_resource = {
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+ .name = "BCM6348 PCI IO space",
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+ .flags = IORESOURCE_IO,
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+};
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+static struct resource bcm6348_pci_mem_resource;
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+static struct resource bcm6348_pci_busn_resource;
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+
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+static struct pci_controller bcm6348_pci_controller = {
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+ .pci_ops = &bcm6348_pci_ops,
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+ .io_resource = &bcm6348_pci_io_resource,
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+ .mem_resource = &bcm6348_pci_mem_resource,
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+ .busn_resource = &bcm6348_pci_busn_resource,
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+};
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+
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+#ifdef CONFIG_CARDBUS
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+static int bcm6348_cb_bridge_read(int where, int size, u32 *val)
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+{
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+ struct bcm6348_cb *cb = &bcm6348_pci.cb;
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+ unsigned int reg;
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+ u32 data;
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+
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+ data = 0;
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+ reg = where >> 2;
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+ switch (reg) {
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+ case (PCI_VENDOR_ID >> 2):
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+ case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
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+ /* create dummy vendor/device id from our cpu id */
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+ data = (CARDBUS_DUMMY_ID << 16) | PCI_VENDOR_ID_BROADCOM;
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+ break;
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+
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+ case (PCI_COMMAND >> 2):
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+ data = (PCI_STATUS_DEVSEL_SLOW << 16);
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+ data |= cb->pci_command;
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+ break;
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+
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+ case (PCI_CLASS_REVISION >> 2):
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+ data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
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+ break;
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+
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+ case (PCI_CACHE_LINE_SIZE >> 2):
|
|
|
+ data = (PCI_HEADER_TYPE_CARDBUS << 16);
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_INTERRUPT_LINE >> 2):
|
|
|
+ /* bridge control */
|
|
|
+ data = (cb->bridge_control << 16);
|
|
|
+ /* pin:intA line:0xff */
|
|
|
+ data |= (0x1 << 8) | 0xff;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_PRIMARY_BUS >> 2):
|
|
|
+ data = (cb->cb_latency << 24);
|
|
|
+ data |= (cb->subordinate_busn << 16);
|
|
|
+ data |= (cb->cardbus_busn << 8);
|
|
|
+ data |= cb->pci_busn;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_MEMORY_BASE_0 >> 2):
|
|
|
+ data = cb->mem_base0;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_MEMORY_LIMIT_0 >> 2):
|
|
|
+ data = cb->mem_limit0;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_MEMORY_BASE_1 >> 2):
|
|
|
+ data = cb->mem_base1;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_MEMORY_LIMIT_1 >> 2):
|
|
|
+ data = cb->mem_limit1;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_IO_BASE_0 >> 2):
|
|
|
+ /* | 1 for 32bits io support */
|
|
|
+ data = cb->io_base0 | 0x1;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_IO_LIMIT_0 >> 2):
|
|
|
+ data = cb->io_limit0;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_IO_BASE_1 >> 2):
|
|
|
+ /* | 1 for 32bits io support */
|
|
|
+ data = cb->io_base1 | 0x1;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_IO_LIMIT_1 >> 2):
|
|
|
+ data = cb->io_limit1;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ *val = postprocess_read(data, where, size);
|
|
|
+ return PCIBIOS_SUCCESSFUL;
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * emulate configuration write access on a cardbus bridge
|
|
|
+ */
|
|
|
+static int bcm6348_cb_bridge_write(int where, int size, u32 val)
|
|
|
+{
|
|
|
+ struct bcm6348_cb *cb = &bcm6348_pci.cb;
|
|
|
+ unsigned int reg;
|
|
|
+ u32 data, tmp;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ ret = bcm6348_cb_bridge_read((where & ~0x3), 4, &data);
|
|
|
+ if (ret != PCIBIOS_SUCCESSFUL)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ data = preprocess_write(data, val, where, size);
|
|
|
+
|
|
|
+ reg = where >> 2;
|
|
|
+ switch (reg) {
|
|
|
+ case (PCI_COMMAND >> 2):
|
|
|
+ cb->pci_command = (data & 0xffff);
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_PRIMARY_BUS >> 2):
|
|
|
+ cb->cb_latency = (data >> 24) & 0xff;
|
|
|
+ cb->subordinate_busn = (data >> 16) & 0xff;
|
|
|
+ cb->cardbus_busn = (data >> 8) & 0xff;
|
|
|
+ cb->pci_busn = data & 0xff;
|
|
|
+ if (cb->cardbus_busn)
|
|
|
+ cb->bus_assigned = 1;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_INTERRUPT_LINE >> 2):
|
|
|
+ tmp = (data >> 16) & 0xffff;
|
|
|
+ /* Disable memory prefetch support */
|
|
|
+ tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
|
|
|
+ tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
|
|
|
+ cb->bridge_control = tmp;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_MEMORY_BASE_0 >> 2):
|
|
|
+ cb->mem_base0 = data;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_MEMORY_LIMIT_0 >> 2):
|
|
|
+ cb->mem_limit0 = data;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_MEMORY_BASE_1 >> 2):
|
|
|
+ cb->mem_base1 = data;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_MEMORY_LIMIT_1 >> 2):
|
|
|
+ cb->mem_limit1 = data;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_IO_BASE_0 >> 2):
|
|
|
+ cb->io_base0 = data;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_IO_LIMIT_0 >> 2):
|
|
|
+ cb->io_limit0 = data;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_IO_BASE_1 >> 2):
|
|
|
+ cb->io_base1 = data;
|
|
|
+ break;
|
|
|
+
|
|
|
+ case (PCI_CB_IO_LIMIT_1 >> 2):
|
|
|
+ cb->io_limit1 = data;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ return PCIBIOS_SUCCESSFUL;
|
|
|
+}
|
|
|
+
|
|
|
+static int bcm6348_cb_read(struct pci_bus *bus, unsigned int devfn,
|
|
|
+ int where, int size, u32 *val)
|
|
|
+{
|
|
|
+ struct bcm6348_pci *priv = &bcm6348_pci;
|
|
|
+ struct bcm6348_cb *cb = &priv->cb;
|
|
|
+
|
|
|
+ /* Snoop access to slot 0x1e on root bus, we fake a cardbus
|
|
|
+ * bridge at this location */
|
|
|
+ if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
|
|
|
+ priv->cb_bus = bus->number;
|
|
|
+ return bcm6348_cb_bridge_read(where, size, val);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* A configuration cycle for the device behind the cardbus
|
|
|
+ * bridge is actually done as a type 0 cycle on the primary
|
|
|
+ * bus. This means that only one device can be on the cardbus
|
|
|
+ * bus */
|
|
|
+ if (cb->bus_assigned &&
|
|
|
+ bus->number == cb->cardbus_busn &&
|
|
|
+ PCI_SLOT(devfn) == 0)
|
|
|
+ return bcm6348_do_cfg_read(0, 0,
|
|
|
+ PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
|
|
|
+ where, size, val);
|
|
|
+
|
|
|
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
+}
|
|
|
+
|
|
|
+static int bcm6348_cb_write(struct pci_bus *bus, unsigned int devfn,
|
|
|
+ int where, int size, u32 val)
|
|
|
+{
|
|
|
+ struct bcm6348_pci *priv = &bcm6348_pci;
|
|
|
+ struct bcm6348_cb *cb = &priv->cb;
|
|
|
+
|
|
|
+ if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
|
|
|
+ priv->cb_bus = bus->number;
|
|
|
+ return bcm6348_cb_bridge_write(where, size, val);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (cb->bus_assigned &&
|
|
|
+ bus->number == cb->cardbus_busn &&
|
|
|
+ PCI_SLOT(devfn) == 0)
|
|
|
+ return bcm6348_do_cfg_write(0, 0,
|
|
|
+ PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
|
|
|
+ where, size, val);
|
|
|
+
|
|
|
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
+}
|
|
|
+
|
|
|
+static struct pci_ops bcm6348_cb_ops = {
|
|
|
+ .read = bcm6348_cb_read,
|
|
|
+ .write = bcm6348_cb_write,
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * only one IO window, so it cannot be shared by PCI and cardbus, use
|
|
|
+ * fixup to choose and detect unhandled configuration
|
|
|
+ */
|
|
|
+static void bcm6348_pci_fixup(struct pci_dev *dev)
|
|
|
+{
|
|
|
+ struct bcm6348_pci *priv = &bcm6348_pci;
|
|
|
+ struct bcm6348_cb *cb = &priv->cb;
|
|
|
+ static int io_window = -1;
|
|
|
+ int i, found, new_io_window;
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ /* look for any io resource */
|
|
|
+ found = 0;
|
|
|
+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
|
|
+ if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
|
|
|
+ found = 1;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!found)
|
|
|
+ return;
|
|
|
+
|
|
|
+ /* skip our fake bus with only cardbus bridge on it */
|
|
|
+ if (dev->bus->number == priv->cb_bus)
|
|
|
+ return;
|
|
|
+
|
|
|
+ /* find on which bus the device is */
|
|
|
+ if (cb->bus_assigned &&
|
|
|
+ dev->bus->number == cb->cardbus_busn &&
|
|
|
+ PCI_SLOT(dev->devfn) == 0)
|
|
|
+ new_io_window = 1;
|
|
|
+ else
|
|
|
+ new_io_window = 0;
|
|
|
+
|
|
|
+ if (new_io_window == io_window)
|
|
|
+ return;
|
|
|
+
|
|
|
+ if (io_window != -1) {
|
|
|
+ pr_err("bcm63xx: both PCI and cardbus devices "
|
|
|
+ "need IO, which hardware cannot do\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ pr_info("bcm63xx: PCI IO window assigned to %s\n",
|
|
|
+ (new_io_window == 0) ? "PCI" : "cardbus");
|
|
|
+
|
|
|
+ val = __raw_readl(priv->pci + MPI_L2PIOREMAP_REG);
|
|
|
+ if (io_window)
|
|
|
+ val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
|
|
|
+ else
|
|
|
+ val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
|
|
|
+ __raw_writel(val, priv->pci + MPI_L2PIOREMAP_REG);
|
|
|
+
|
|
|
+ io_window = new_io_window;
|
|
|
+}
|
|
|
+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm6348_pci_fixup);
|
|
|
+
|
|
|
+static struct resource bcm6348_cb_io_resource = {
|
|
|
+ .name = "bcm6348 CB IO space",
|
|
|
+ .flags = IORESOURCE_IO,
|
|
|
+};
|
|
|
+static struct resource bcm6348_cb_mem_resource;
|
|
|
+
|
|
|
+static struct pci_controller bcm6348_cb_controller = {
|
|
|
+ .pci_ops = &bcm6348_cb_ops,
|
|
|
+ .io_resource = &bcm6348_cb_io_resource,
|
|
|
+ .mem_resource = &bcm6348_cb_mem_resource,
|
|
|
+};
|
|
|
+#endif /* CONFIG_CARDBUS */
|
|
|
+
|
|
|
+static void bcm6348_pci_setup(struct bcm6348_pci *priv)
|
|
|
+{
|
|
|
+ u32 val;
|
|
|
+
|
|
|
+ /* Setup local bus to PCI access (PCI memory) */
|
|
|
+ val = bcm6348_pci_mem_resource.start & MPI_L2P_BASE_MASK;
|
|
|
+ __raw_writel(val, priv->pci + MPI_L2PMEMBASE1_REG);
|
|
|
+ __raw_writel(~(resource_size(&bcm6348_pci_mem_resource) - 1),
|
|
|
+ priv->pci + MPI_L2PMEMRANGE1_REG);
|
|
|
+ __raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
|
|
|
+ priv->pci + MPI_L2PMEMREMAP1_REG);
|
|
|
+
|
|
|
+ /* Set Cardbus IDSEL (type 0 cfg access on primary bus for
|
|
|
+ * this IDSEL will be done on Cardbus instead) */
|
|
|
+ val = __raw_readl(priv->pcmcia + PCMCIA_C1_REG);
|
|
|
+ val &= ~PCMCIA_C1_CBIDSEL_MASK;
|
|
|
+ val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
|
|
|
+ __raw_writel(val, priv->pcmcia + PCMCIA_C1_REG);
|
|
|
+
|
|
|
+#ifdef CONFIG_CARDBUS
|
|
|
+ /* setup local bus to PCI access (Cardbus memory) */
|
|
|
+ val = bcm6348_cb_mem_resource.start & MPI_L2P_BASE_MASK;
|
|
|
+ __raw_writel(val, priv->pci + MPI_L2PMEMBASE2_REG);
|
|
|
+ __raw_writel(~(resource_size(&bcm6348_cb_mem_resource) - 1),
|
|
|
+ priv->pci + MPI_L2PMEMRANGE2_REG);
|
|
|
+ val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
|
|
|
+ __raw_writel(val, priv->pci + MPI_L2PMEMREMAP2_REG);
|
|
|
+#else
|
|
|
+ /* disable second access windows */
|
|
|
+ __raw_writel(0, priv->pci + MPI_L2PMEMREMAP2_REG);
|
|
|
+#endif
|
|
|
+
|
|
|
+ /* setup local bus to PCI access (IO memory), we have only 1
|
|
|
+ * IO window for both PCI and cardbus, but it cannot handle
|
|
|
+ * both at the same time, assume standard PCI for now, if
|
|
|
+ * cardbus card has IO zone, PCI fixup will change window to
|
|
|
+ * cardbus */
|
|
|
+ val = bcm6348_pci_io_resource.start & MPI_L2P_BASE_MASK;
|
|
|
+ __raw_writel(val, priv->pci + MPI_L2PIOBASE_REG);
|
|
|
+ __raw_writel(~(resource_size(&bcm6348_pci_io_resource) - 1),
|
|
|
+ priv->pci + MPI_L2PIORANGE_REG);
|
|
|
+ __raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
|
|
|
+ priv->pci + MPI_L2PIOREMAP_REG);
|
|
|
+
|
|
|
+ /* Enable PCI related GPIO pins */
|
|
|
+ __raw_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK,
|
|
|
+ priv->pci + MPI_LOCBUSCTL_REG);
|
|
|
+
|
|
|
+ /* Setup PCI to local bus access, used by PCI device to target
|
|
|
+ * local RAM while bus mastering */
|
|
|
+ bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
|
|
|
+ if (priv->remap)
|
|
|
+ val = MPI_SP0_REMAP_ENABLE_MASK;
|
|
|
+ else
|
|
|
+ val = 0;
|
|
|
+ __raw_writel(val, priv->pci + MPI_SP0_REMAP_REG);
|
|
|
+
|
|
|
+ bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_4);
|
|
|
+ __raw_writel(0, priv->pci + MPI_SP1_REMAP_REG);
|
|
|
+
|
|
|
+ /* Setup sp0 range to local RAM size */
|
|
|
+ __raw_writel(~(memblock_phys_mem_size() - 1),
|
|
|
+ priv->pci + MPI_SP0_RANGE_REG);
|
|
|
+ __raw_writel(0, priv->pci + MPI_SP1_RANGE_REG);
|
|
|
+
|
|
|
+ /* Change host bridge retry counter to infinite number of
|
|
|
+ * retries, needed for some broadcom wifi cards with Silicon
|
|
|
+ * Backplane bus where access to srom seems very slow */
|
|
|
+ val = bcm6348_int_cfg_readl(BCMPCI_REG_TIMERS);
|
|
|
+ val &= ~REG_TIMER_RETRY_MASK;
|
|
|
+ bcm6348_int_cfg_writel(val, BCMPCI_REG_TIMERS);
|
|
|
+
|
|
|
+ /* EEnable memory decoder and bus mastering */
|
|
|
+ val = bcm6348_int_cfg_readl(PCI_COMMAND);
|
|
|
+ val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
|
+ bcm6348_int_cfg_writel(val, PCI_COMMAND);
|
|
|
+
|
|
|
+ /* Enable read prefetching & disable byte swapping for bus
|
|
|
+ * mastering transfers */
|
|
|
+ val = __raw_readl(priv->pci + MPI_PCIMODESEL_REG);
|
|
|
+ val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
|
|
|
+ val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
|
|
|
+ val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
|
|
|
+ val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
|
|
|
+ __raw_writel(val, priv->pci + MPI_PCIMODESEL_REG);
|
|
|
+
|
|
|
+ /* Enable pci interrupt */
|
|
|
+ val = __raw_readl(priv->pci + MPI_LOCINT_REG);
|
|
|
+ val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
|
|
|
+ __raw_writel(val, priv->pci + MPI_LOCINT_REG);
|
|
|
+}
|
|
|
+
|
|
|
+static int bcm6348_pci_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+ struct device_node *np = dev->of_node;
|
|
|
+ struct bcm6348_pci *priv = &bcm6348_pci;
|
|
|
+ struct resource *res;
|
|
|
+
|
|
|
+ of_pci_check_probe_only();
|
|
|
+
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pci");
|
|
|
+ priv->pci = devm_ioremap_resource(dev, res);
|
|
|
+ if (IS_ERR(priv->pci))
|
|
|
+ return PTR_ERR(priv->pci);
|
|
|
+
|
|
|
+ priv->pcmcia = priv->pci + PCMCIA_OFFSET;
|
|
|
+
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pci-io");
|
|
|
+ if (!res)
|
|
|
+ return -EINVAL;
|
|
|
+#ifdef CONFIG_CARDBUS
|
|
|
+ bcm6348_pci_io_resource.start = res->start;
|
|
|
+ bcm6348_pci_io_resource.end = res->end - (resource_size(res) >> 1);
|
|
|
+ bcm6348_cb_io_resource.start = res->start + (resource_size(res) >> 1);
|
|
|
+ bcm6348_cb_io_resource.end = res->end;
|
|
|
+#else
|
|
|
+ bcm6348_pci_io_resource.start = res->start;
|
|
|
+ bcm6348_pci_io_resource.end = res->end;
|
|
|
+#endif
|
|
|
+
|
|
|
+ priv->irq = platform_get_irq(pdev, 0);
|
|
|
+ if (!priv->irq)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ bmips_pci_irq = priv->irq;
|
|
|
+
|
|
|
+ priv->reset = devm_reset_control_get(dev, "pci");
|
|
|
+ if (IS_ERR(priv->reset))
|
|
|
+ return PTR_ERR(priv->reset);
|
|
|
+
|
|
|
+ priv->remap = of_property_read_bool(np, "brcm,remap");
|
|
|
+
|
|
|
+ reset_control_reset(priv->reset);
|
|
|
+
|
|
|
+ pci_load_of_ranges(&bcm6348_pci_controller, np);
|
|
|
+ if (!bcm6348_pci_mem_resource.start)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ of_pci_parse_bus_range(np, &bcm6348_pci_busn_resource);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Configuration accesses are done through IO space, remap 4
|
|
|
+ * first bytes to access it from CPU.
|
|
|
+ *
|
|
|
+ * This means that no IO access from CPU should happen while
|
|
|
+ * we do a configuration cycle, but there's no way we can add
|
|
|
+ * a spinlock for each io access, so this is currently kind of
|
|
|
+ * broken on SMP.
|
|
|
+ */
|
|
|
+ priv->io = ioremap(bcm6348_pci_io_resource.start, sizeof(u32));
|
|
|
+ if (!priv->io)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ bcm6348_pci_setup(priv);
|
|
|
+
|
|
|
+ register_pci_controller(&bcm6348_pci_controller);
|
|
|
+
|
|
|
+#ifdef CONFIG_CARDBUS
|
|
|
+ priv->cb_bus = -1;
|
|
|
+ register_pci_controller(&bcm6348_cb_controller);
|
|
|
+#endif /* CONFIG_CARDBUS */
|
|
|
+
|
|
|
+ /* Mark memory space used for IO mapping as reserved */
|
|
|
+ request_mem_region(bcm6348_pci_io_resource.start,
|
|
|
+ resource_size(&bcm6348_pci_io_resource),
|
|
|
+ "BCM6348 PCI IO space");
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct of_device_id bcm6348_pci_of_match[] = {
|
|
|
+ { .compatible = "brcm,bcm6348-pci", },
|
|
|
+ { /* sentinel */ }
|
|
|
+};
|
|
|
+
|
|
|
+static struct platform_driver bcm6348_pci_driver = {
|
|
|
+ .probe = bcm6348_pci_probe,
|
|
|
+ .driver = {
|
|
|
+ .name = "bcm6348-pci",
|
|
|
+ .of_match_table = bcm6348_pci_of_match,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+int __init bcm6348_pci_init(void)
|
|
|
+{
|
|
|
+ int ret = platform_driver_register(&bcm6348_pci_driver);
|
|
|
+ if (ret)
|
|
|
+ pr_err("pci-bcm6348: Error registering platform driver!\n");
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+late_initcall_sync(bcm6348_pci_init);
|
Álvaro Fernández Rojas