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@@ -196,17 +196,6 @@
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#define RTL931X_RMA_CTRL_1 (0x8804)
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#define RTL931X_RMA_CTRL_2 (0x8808)
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-/* Advanced SMI control for clause 45 PHYs */
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-#define RTL930X_SMI_MAC_TYPE_CTRL (0xCA04)
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-#define RTL930X_SMI_PORT24_27_ADDR_CTRL (0xCB90)
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-#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
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-#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
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-
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-#define RTL930X_SMI_10GPHY_POLLING_REG0_CFG (0xCBB4)
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-#define RTL930X_SMI_10GPHY_POLLING_REG9_CFG (0xCBB8)
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-#define RTL930X_SMI_10GPHY_POLLING_REG10_CFG (0xCBBC)
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-#define RTL930X_SMI_PRVTE_POLLING_CTRL (0xCA10)
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-
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/* Chip configuration registers of the RTL9310 */
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#define RTL931X_MEM_ENCAP_INIT (0x4854)
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#define RTL931X_MEM_MIB_INIT (0x7E18)
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@@ -216,9 +205,6 @@
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#define RTL931X_MEM_ALE_INIT_2 (0x82E4)
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#define RTL931X_MDX_CTRL_RSVD (0x0fcc)
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#define RTL931X_PS_SOC_CTRL (0x13f8)
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-#define RTL931X_SMI_10GPHY_POLLING_SEL2 (0xCF8)
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-#define RTL931X_SMI_10GPHY_POLLING_SEL3 (0xCFC)
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-#define RTL931X_SMI_10GPHY_POLLING_SEL4 (0xD00)
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/* shared CPU tag definitions for RTL930X/RTL931X */
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#define RTL93XX_CPU_TAG1_FWD_MASK GENMASK(11, 8)
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