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@@ -0,0 +1,697 @@
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+From 980da78179592a3f5f99168bc5af415835aa8c13 Mon Sep 17 00:00:00 2001
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+From: Hauke Mehrtens <[email protected]>
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+Date: Sun, 24 Jul 2011 20:20:36 +0200
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+Subject: [PATCH 15/26] ssb: add serial flash support
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+
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+
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+Signed-off-by: Hauke Mehrtens <[email protected]>
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+---
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+ drivers/ssb/Kconfig | 6 +
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+ drivers/ssb/Makefile | 1 +
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+ drivers/ssb/driver_chipcommon_sflash.c | 556 +++++++++++++++++++++++++++++
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+ drivers/ssb/driver_mipscore.c | 6 +
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+ drivers/ssb/ssb_private.h | 4 +
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+ include/linux/ssb/ssb_driver_chipcommon.h | 30 ++-
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+ 6 files changed, 601 insertions(+), 2 deletions(-)
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+ create mode 100644 drivers/ssb/driver_chipcommon_sflash.c
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+
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+--- a/drivers/ssb/Kconfig
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++++ b/drivers/ssb/Kconfig
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+@@ -137,6 +137,12 @@ config SSB_DRIVER_MIPS
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+
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+ If unsure, say N
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+
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++config SSB_SFLASH
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++ bool
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++ depends on SSB_DRIVER_MIPS
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++ default y
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++
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++
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+ # Assumption: We are on embedded, if we compile the MIPS core.
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+ config SSB_EMBEDDED
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+ bool
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+--- a/drivers/ssb/Makefile
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++++ b/drivers/ssb/Makefile
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+@@ -11,6 +11,7 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
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+ # built-in drivers
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+ ssb-y += driver_chipcommon.o
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+ ssb-y += driver_chipcommon_pmu.o
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++ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
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+ ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
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+ ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
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+ ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
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+--- /dev/null
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++++ b/drivers/ssb/driver_chipcommon_sflash.c
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+@@ -0,0 +1,556 @@
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++/*
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++ * Broadcom SiliconBackplane chipcommon serial flash interface
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++ *
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++ * Copyright 2011, Jonas Gorski <[email protected]>
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++ * Copyright 2010, Broadcom Corporation
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++ *
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++ * Licensed under the GNU/GPL. See COPYING for details.
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++ */
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++
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++#include <linux/ssb/ssb.h>
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++#include <linux/ssb/ssb_driver_chipcommon.h>
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++#include <linux/delay.h>
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++
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++#include "ssb_private.h"
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++
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++#define NUM_RETRIES 3
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++
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++
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++/* Issue a serial flash command */
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++static inline void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
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++{
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++ chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
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++ SSB_CHIPCO_FLASHCTL_START | opcode);
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++ while (chipco_read32(cc, SSB_CHIPCO_FLASHCTL)
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++ & SSB_CHIPCO_FLASHCTL_BUSY)
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++ ;
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++}
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++
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++
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++static inline void ssb_sflash_write_u8(struct ssb_chipcommon *cc,
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++ u32 offset, u8 byte)
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++{
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++ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, offset);
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++ chipco_write32(cc, SSB_CHIPCO_FLASHDATA, byte);
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++}
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++
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++/* Initialize serial flash access */
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++int ssb_sflash_init(struct ssb_chipcommon *cc)
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++{
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++ u32 id, id2;
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++
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++ memset(&cc->sflash, 0, sizeof(struct ssb_sflash));
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++
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++ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
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++ case SSB_CHIPCO_FLASHT_STSER:
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++ /* Probe for ST chips */
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++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
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++ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
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++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
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++ id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
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++ cc->sflash.blocksize = 64 * 1024;
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++ switch (id) {
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++ case 0x11:
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++ /* ST M25P20 2 Mbit Serial Flash */
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++ cc->sflash.numblocks = 4;
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++ break;
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++ case 0x12:
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++ /* ST M25P40 4 Mbit Serial Flash */
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++ cc->sflash.numblocks = 8;
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++ break;
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++ case 0x13:
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++ /* ST M25P80 8 Mbit Serial Flash */
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++ cc->sflash.numblocks = 16;
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++ break;
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++ case 0x14:
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++ /* ST M25P16 16 Mbit Serial Flash */
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++ cc->sflash.numblocks = 32;
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++ break;
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++ case 0x15:
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++ /* ST M25P32 32 Mbit Serial Flash */
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++ cc->sflash.numblocks = 64;
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++ break;
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++ case 0x16:
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++ /* ST M25P64 64 Mbit Serial Flash */
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++ cc->sflash.numblocks = 128;
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++ break;
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++ case 0x17:
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++ /* ST M25FL128 128 Mbit Serial Flash */
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++ cc->sflash.numblocks = 256;
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++ break;
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++ case 0xbf:
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++ /* All of the following flashes are SST with
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++ * 4KB subsectors. Others should be added but
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++ * We'll have to revamp the way we identify them
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++ * since RES is not eough to disambiguate them.
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++ */
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++ cc->sflash.blocksize = 4 * 1024;
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++ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
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++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
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++ id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
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++ switch (id2) {
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++ case 1:
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++ /* SST25WF512 512 Kbit Serial Flash */
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++ case 0x48:
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++ /* SST25VF512 512 Kbit Serial Flash */
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++ cc->sflash.numblocks = 16;
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++ break;
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++ case 2:
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++ /* SST25WF010 1 Mbit Serial Flash */
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++ case 0x49:
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++ /* SST25VF010 1 Mbit Serial Flash */
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++ cc->sflash.numblocks = 32;
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++ break;
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++ case 3:
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++ /* SST25WF020 2 Mbit Serial Flash */
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++ case 0x43:
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++ /* SST25VF020 2 Mbit Serial Flash */
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++ cc->sflash.numblocks = 64;
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++ break;
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++ case 4:
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++ /* SST25WF040 4 Mbit Serial Flash */
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++ case 0x44:
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++ /* SST25VF040 4 Mbit Serial Flash */
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++ case 0x8d:
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++ /* SST25VF040B 4 Mbit Serial Flash */
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++ cc->sflash.numblocks = 128;
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++ break;
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++ case 5:
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++ /* SST25WF080 8 Mbit Serial Flash */
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++ case 0x8e:
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++ /* SST25VF080B 8 Mbit Serial Flash */
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++ cc->sflash.numblocks = 256;
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++ break;
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++ case 0x41:
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++ /* SST25VF016 16 Mbit Serial Flash */
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++ cc->sflash.numblocks = 512;
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++ break;
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++ case 0x4a:
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++ /* SST25VF032 32 Mbit Serial Flash */
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++ cc->sflash.numblocks = 1024;
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++ break;
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++ case 0x4b:
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++ /* SST25VF064 64 Mbit Serial Flash */
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++ cc->sflash.numblocks = 2048;
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++ break;
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++ }
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++ break;
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++ }
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++ break;
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++
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++ case SSB_CHIPCO_FLASHT_ATSER:
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++ /* Probe for Atmel chips */
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++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
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++ id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
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++ switch (id) {
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++ case 0xc:
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++ /* Atmel AT45DB011 1Mbit Serial Flash */
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++ cc->sflash.blocksize = 256;
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++ cc->sflash.numblocks = 512;
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++ break;
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++ case 0x14:
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++ /* Atmel AT45DB021 2Mbit Serial Flash */
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++ cc->sflash.blocksize = 256;
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++ cc->sflash.numblocks = 1024;
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++ break;
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++ case 0x1c:
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++ /* Atmel AT45DB041 4Mbit Serial Flash */
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++ cc->sflash.blocksize = 256;
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++ cc->sflash.numblocks = 2048;
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++ break;
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++ case 0x24:
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++ /* Atmel AT45DB081 8Mbit Serial Flash */
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++ cc->sflash.blocksize = 256;
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++ cc->sflash.numblocks = 4096;
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++ break;
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++ case 0x2c:
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++ /* Atmel AT45DB161 16Mbit Serial Flash */
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++ cc->sflash.blocksize = 512;
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++ cc->sflash.numblocks = 4096;
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++ break;
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++ case 0x34:
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++ /* Atmel AT45DB321 32Mbit Serial Flash */
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++ cc->sflash.blocksize = 512;
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++ cc->sflash.numblocks = 8192;
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++ break;
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++ case 0x3c:
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++ /* Atmel AT45DB642 64Mbit Serial Flash */
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++ cc->sflash.blocksize = 1024;
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++ cc->sflash.numblocks = 8192;
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++ break;
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++ }
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++ break;
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++ }
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++
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++ cc->sflash.size = cc->sflash.blocksize * cc->sflash.numblocks;
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++
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++ return cc->sflash.size ? 0 : -ENODEV;
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++}
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++
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++/* Read len bytes starting at offset into buf. Returns number of bytes read. */
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++int ssb_sflash_read(struct ssb_chipcommon *cc, u32 offset, u32 len,
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++ u8 *buf)
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++{
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++ u8 *from, *to;
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++ u32 cnt, i;
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++
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++ if (!len)
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++ return 0;
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++
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++ if ((offset + len) > cc->sflash.size)
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++ return -EINVAL;
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++
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++ if ((len >= 4) && (offset & 3))
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++ cnt = 4 - (offset & 3);
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++ else if ((len >= 4) && ((u32)buf & 3))
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++ cnt = 4 - ((u32)buf & 3);
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++ else
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++ cnt = len;
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++
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++
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++ if (cc->dev->id.revision == 12)
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++ from = (u8 *)KSEG1ADDR(SSB_FLASH2 + offset);
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++ else
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++ from = (u8 *)KSEG0ADDR(SSB_FLASH2 + offset);
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++
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++ to = (u8 *)buf;
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++
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++ if (cnt < 4) {
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++ for (i = 0; i < cnt; i++) {
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++ *to = readb(from);
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++ from++;
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++ to++;
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++ }
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++ return cnt;
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++ }
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++
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++ while (cnt >= 4) {
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++ *(u32 *)to = readl(from);
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++ from += 4;
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++ to += 4;
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++ cnt -= 4;
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++ }
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++
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++ return len - cnt;
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++}
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++
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++/* Poll for command completion. Returns zero when complete. */
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++int ssb_sflash_poll(struct ssb_chipcommon *cc, u32 offset)
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++{
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++ if (offset >= cc->sflash.size)
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++ return -22;
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++
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++ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
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++ case SSB_CHIPCO_FLASHT_STSER:
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++ /* Check for ST Write In Progress bit */
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++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RDSR);
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++ return chipco_read32(cc, SSB_CHIPCO_FLASHDATA)
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++ & SSB_CHIPCO_FLASHSTA_ST_WIP;
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++ case SSB_CHIPCO_FLASHT_ATSER:
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++ /* Check for Atmel Ready bit */
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++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
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++ return !(chipco_read32(cc, SSB_CHIPCO_FLASHDATA)
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++ & SSB_CHIPCO_FLASHSTA_AT_READY);
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++ }
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++
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++ return 0;
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++}
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++
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++
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++static int sflash_st_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
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++ const u8 *buf)
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++{
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++ struct ssb_bus *bus = cc->dev->bus;
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++ int ret = 0;
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++ bool is4712b0 = (bus->chip_id == 0x4712) && (bus->chip_rev == 3);
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++ u32 mask;
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++
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++
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++ /* Enable writes */
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++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_WREN);
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++ if (is4712b0) {
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++ mask = 1 << 14;
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++ ssb_sflash_write_u8(cc, offset, *buf++);
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++ /* Set chip select */
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++ chipco_set32(cc, SSB_CHIPCO_GPIOOUT, mask);
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++ /* Issue a page program with the first byte */
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++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_PP);
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++ ret = 1;
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++ offset++;
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++ len--;
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++ while (len > 0) {
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++ if ((offset & 255) == 0) {
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++ /* Page boundary, drop cs and return */
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++ chipco_mask32(cc, SSB_CHIPCO_GPIOOUT, ~mask);
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++ udelay(1);
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++ if (!ssb_sflash_poll(cc, offset)) {
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++ /* Flash rejected command */
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++ return -EAGAIN;
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++ }
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++ return ret;
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++ } else {
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++ /* Write single byte */
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++ ssb_sflash_cmd(cc, *buf++);
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++ }
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++ ret++;
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++ offset++;
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++ len--;
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++ }
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++ /* All done, drop cs */
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++ chipco_mask32(cc, SSB_CHIPCO_GPIOOUT, ~mask);
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++ udelay(1);
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++ if (!ssb_sflash_poll(cc, offset)) {
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++ /* Flash rejected command */
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++ return -EAGAIN;
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++ }
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++ } else if (cc->dev->id.revision >= 20) {
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++ ssb_sflash_write_u8(cc, offset, *buf++);
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++ /* Issue a page program with CSA bit set */
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++ ssb_sflash_cmd(cc,
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++ SSB_CHIPCO_FLASHCTL_ST_CSA |
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++ SSB_CHIPCO_FLASHCTL_ST_PP);
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++ ret = 1;
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++ offset++;
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++ len--;
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++ while (len > 0) {
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++ if ((offset & 255) == 0) {
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++ /* Page boundary, poll droping cs and return */
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++ chipco_write32(cc, SSB_CHIPCO_FLASHCTL, 0);
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++ udelay(1);
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++ if (!ssb_sflash_poll(cc, offset)) {
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++ /* Flash rejected command */
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++ return -EAGAIN;
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++ }
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++ return ret;
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++ } else {
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++ /* Write single byte */
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++ ssb_sflash_cmd(cc,
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++ SSB_CHIPCO_FLASHCTL_ST_CSA |
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++ *buf++);
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++ }
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++ ret++;
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++ offset++;
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++ len--;
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++ }
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++ /* All done, drop cs & poll */
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++ chipco_write32(cc, SSB_CHIPCO_FLASHCTL, 0);
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++ udelay(1);
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++ if (!ssb_sflash_poll(cc, offset)) {
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++ /* Flash rejected command */
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++ return -EAGAIN;
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++ }
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++ } else {
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++ ret = 1;
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++ ssb_sflash_write_u8(cc, offset, *buf);
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++ /* Page program */
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++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_PP);
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++ }
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++ return ret;
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++}
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++
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++static int sflash_at_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
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++ const u8 *buf)
|
|
|
++{
|
|
|
++ struct ssb_sflash *sfl = &cc->sflash;
|
|
|
++ u32 page, byte, mask;
|
|
|
++ int ret = 0;
|
|
|
++ mask = sfl->blocksize - 1;
|
|
|
++ page = (offset & ~mask) << 1;
|
|
|
++ byte = offset & mask;
|
|
|
++ /* Read main memory page into buffer 1 */
|
|
|
++ if (byte || (len < sfl->blocksize)) {
|
|
|
++ int i = 100;
|
|
|
++ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, page);
|
|
|
++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD);
|
|
|
++ /* 250 us for AT45DB321B */
|
|
|
++ while (i > 0 && ssb_sflash_poll(cc, offset)) {
|
|
|
++ udelay(10);
|
|
|
++ i--;
|
|
|
++ }
|
|
|
++ BUG_ON(!ssb_sflash_poll(cc, offset));
|
|
|
++ }
|
|
|
++ /* Write into buffer 1 */
|
|
|
++ for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
|
|
|
++ ssb_sflash_write_u8(cc, byte++, *buf++);
|
|
|
++ ssb_sflash_cmd(cc,
|
|
|
++ SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE);
|
|
|
++ }
|
|
|
++ /* Write buffer 1 into main memory page */
|
|
|
++ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, page);
|
|
|
++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM);
|
|
|
++
|
|
|
++ return ret;
|
|
|
++}
|
|
|
++
|
|
|
++/* Write len bytes starting at offset into buf. Returns number of bytes
|
|
|
++ * written. Caller should poll for completion.
|
|
|
++ */
|
|
|
++int ssb_sflash_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
|
|
++ const u8 *buf)
|
|
|
++{
|
|
|
++ struct ssb_sflash *sfl;
|
|
|
++ int ret = 0, tries = NUM_RETRIES;
|
|
|
++
|
|
|
++ if (!len)
|
|
|
++ return 0;
|
|
|
++
|
|
|
++ if ((offset + len) > cc->sflash.size)
|
|
|
++ return -EINVAL;
|
|
|
++
|
|
|
++ sfl = &cc->sflash;
|
|
|
++ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
|
|
|
++ case SSB_CHIPCO_FLASHT_STSER:
|
|
|
++ do {
|
|
|
++ ret = sflash_st_write(cc, offset, len, buf);
|
|
|
++ tries--;
|
|
|
++ } while (ret == -EAGAIN && tries > 0);
|
|
|
++
|
|
|
++ if (ret == -EAGAIN && tries == 0) {
|
|
|
++ pr_info("ST Flash rejected write\n");
|
|
|
++ ret = -EIO;
|
|
|
++ }
|
|
|
++ break;
|
|
|
++ case SSB_CHIPCO_FLASHT_ATSER:
|
|
|
++ ret = sflash_at_write(cc, offset, len, buf);
|
|
|
++ break;
|
|
|
++ }
|
|
|
++
|
|
|
++ return ret;
|
|
|
++}
|
|
|
++
|
|
|
++/* Erase a region. Returns number of bytes scheduled for erasure.
|
|
|
++ * Caller should poll for completion.
|
|
|
++ */
|
|
|
++int ssb_sflash_erase(struct ssb_chipcommon *cc, u32 offset)
|
|
|
++{
|
|
|
++ struct ssb_sflash *sfl;
|
|
|
++
|
|
|
++ if (offset >= cc->sflash.size)
|
|
|
++ return -EINVAL;
|
|
|
++
|
|
|
++ sfl = &cc->sflash;
|
|
|
++ switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
|
|
|
++ case SSB_CHIPCO_FLASHT_STSER:
|
|
|
++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_WREN);
|
|
|
++ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, offset);
|
|
|
++ /* Newer flashes have "sub-sectors" which can be erased independently
|
|
|
++ * with a new command: ST_SSE. The ST_SE command erases 64KB just as
|
|
|
++ * before.
|
|
|
++ */
|
|
|
++ ssb_sflash_cmd(cc, (sfl->blocksize < (64 * 1024)) ? SSB_CHIPCO_FLASHCTL_ST_SSE : SSB_CHIPCO_FLASHCTL_ST_SE);
|
|
|
++ return sfl->blocksize;
|
|
|
++ case SSB_CHIPCO_FLASHT_ATSER:
|
|
|
++ chipco_write32(cc, SSB_CHIPCO_FLASHADDR, offset << 1);
|
|
|
++ ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE);
|
|
|
++ return sfl->blocksize;
|
|
|
++ }
|
|
|
++
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++/*
|
|
|
++ * writes the appropriate range of flash, a NULL buf simply erases
|
|
|
++ * the region of flash
|
|
|
++ */
|
|
|
++int ssb_sflash_commit(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
|
|
++ const u8 *buf)
|
|
|
++{
|
|
|
++ struct ssb_sflash *sfl;
|
|
|
++ u8 *block = NULL, *cur_ptr, *blk_ptr;
|
|
|
++ u32 blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
|
|
|
++ u32 blk_offset, blk_len, copied;
|
|
|
++ int bytes, ret = 0;
|
|
|
++
|
|
|
++ /* Check address range */
|
|
|
++ if (len <= 0)
|
|
|
++ return 0;
|
|
|
++
|
|
|
++ sfl = &cc->sflash;
|
|
|
++ if ((offset + len) > sfl->size)
|
|
|
++ return -EINVAL;
|
|
|
++
|
|
|
++ blocksize = sfl->blocksize;
|
|
|
++ mask = blocksize - 1;
|
|
|
++
|
|
|
++ /* Allocate a block of mem */
|
|
|
++ block = kmalloc(blocksize, GFP_KERNEL);
|
|
|
++ if (!block)
|
|
|
++ return -ENOMEM;
|
|
|
++
|
|
|
++ while (len) {
|
|
|
++ /* Align offset */
|
|
|
++ cur_offset = offset & ~mask;
|
|
|
++ cur_length = blocksize;
|
|
|
++ cur_ptr = block;
|
|
|
++
|
|
|
++ remainder = blocksize - (offset & mask);
|
|
|
++ if (len < remainder)
|
|
|
++ cur_retlen = len;
|
|
|
++ else
|
|
|
++ cur_retlen = remainder;
|
|
|
++
|
|
|
++ /* buf == NULL means erase only */
|
|
|
++ if (buf) {
|
|
|
++ /* Copy existing data into holding block if necessary */
|
|
|
++ if ((offset & mask) || (len < blocksize)) {
|
|
|
++ blk_offset = cur_offset;
|
|
|
++ blk_len = cur_length;
|
|
|
++ blk_ptr = cur_ptr;
|
|
|
++
|
|
|
++ /* Copy entire block */
|
|
|
++ while (blk_len) {
|
|
|
++ copied = ssb_sflash_read(cc,
|
|
|
++ blk_offset,
|
|
|
++ blk_len, blk_ptr);
|
|
|
++ blk_offset += copied;
|
|
|
++ blk_len -= copied;
|
|
|
++ blk_ptr += copied;
|
|
|
++ }
|
|
|
++ }
|
|
|
++
|
|
|
++ /* Copy input data into holding block */
|
|
|
++ memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
|
|
|
++ }
|
|
|
++
|
|
|
++ /* Erase block */
|
|
|
++ ret = ssb_sflash_erase(cc, cur_offset);
|
|
|
++ if (ret < 0)
|
|
|
++ goto done;
|
|
|
++
|
|
|
++ while (ssb_sflash_poll(cc, cur_offset));
|
|
|
++
|
|
|
++ /* buf == NULL means erase only */
|
|
|
++ if (!buf) {
|
|
|
++ offset += cur_retlen;
|
|
|
++ len -= cur_retlen;
|
|
|
++ continue;
|
|
|
++ }
|
|
|
++
|
|
|
++ /* Write holding block */
|
|
|
++ while (cur_length > 0) {
|
|
|
++ bytes = ssb_sflash_write(cc, cur_offset,
|
|
|
++ cur_length, cur_ptr);
|
|
|
++
|
|
|
++ if (bytes < 0) {
|
|
|
++ ret = bytes;
|
|
|
++ goto done;
|
|
|
++ }
|
|
|
++
|
|
|
++ while (ssb_sflash_poll(cc, cur_offset))
|
|
|
++ ;
|
|
|
++
|
|
|
++ cur_offset += bytes;
|
|
|
++ cur_length -= bytes;
|
|
|
++ cur_ptr += bytes;
|
|
|
++ }
|
|
|
++
|
|
|
++ offset += cur_retlen;
|
|
|
++ len -= cur_retlen;
|
|
|
++ buf += cur_retlen;
|
|
|
++ }
|
|
|
++
|
|
|
++ ret = len;
|
|
|
++done:
|
|
|
++ kfree(block);
|
|
|
++ return ret;
|
|
|
++}
|
|
|
+--- a/drivers/ssb/driver_mipscore.c
|
|
|
++++ b/drivers/ssb/driver_mipscore.c
|
|
|
+@@ -193,7 +193,13 @@ static void ssb_mips_flash_detect(struct
|
|
|
+ switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
|
|
|
+ case SSB_CHIPCO_FLASHT_STSER:
|
|
|
+ case SSB_CHIPCO_FLASHT_ATSER:
|
|
|
++#ifdef CONFIG_SSB_SFLASH
|
|
|
++ pr_info("found serial flash.\n");
|
|
|
++ bus->chipco.flash_type = SSB_SFLASH;
|
|
|
++ ssb_sflash_init(&bus->chipco);
|
|
|
++#else
|
|
|
+ pr_info("serial flash not supported.\n");
|
|
|
++#endif /* CONFIG_SSB_SFLASH */
|
|
|
+ break;
|
|
|
+ case SSB_CHIPCO_FLASHT_PARA:
|
|
|
+ pr_info("found parallel flash.\n");
|
|
|
+--- a/drivers/ssb/ssb_private.h
|
|
|
++++ b/drivers/ssb/ssb_private.h
|
|
|
+@@ -192,6 +192,10 @@ extern int ssb_devices_freeze(struct ssb
|
|
|
+ extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
|
|
|
+
|
|
|
+
|
|
|
++#ifdef CONFIG_SSB_SFLASH
|
|
|
++/* driver_chipcommon_sflash.c */
|
|
|
++int ssb_sflash_init(struct ssb_chipcommon *cc);
|
|
|
++#endif /* CONFIG_SSB_SFLASH */
|
|
|
+
|
|
|
+ /* b43_pci_bridge.c */
|
|
|
+ #ifdef CONFIG_SSB_B43_PCI_BRIDGE
|
|
|
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
|
|
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
|
|
+@@ -503,8 +503,10 @@
|
|
|
+ #define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */
|
|
|
+ #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
|
|
|
+ #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
|
|
|
+-#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
|
|
|
+-#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
|
|
|
++#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00D9 /* Deep Power-down */
|
|
|
++#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
|
|
|
++#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
|
|
|
++#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
|
|
|
+
|
|
|
+ /* Status register bits for ST flashes */
|
|
|
+ #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
|
|
|
+@@ -585,6 +587,7 @@ struct ssb_chipcommon_pmu {
|
|
|
+ #ifdef CONFIG_SSB_DRIVER_MIPS
|
|
|
+ enum ssb_flash_type {
|
|
|
+ SSB_PFLASH,
|
|
|
++ SSB_SFLASH,
|
|
|
+ };
|
|
|
+
|
|
|
+ struct ssb_pflash {
|
|
|
+@@ -592,6 +595,14 @@ struct ssb_pflash {
|
|
|
+ u32 window;
|
|
|
+ u32 window_size;
|
|
|
+ };
|
|
|
++
|
|
|
++#ifdef CONFIG_SSB_SFLASH
|
|
|
++struct ssb_sflash {
|
|
|
++ u32 blocksize; /* Block size */
|
|
|
++ u32 numblocks; /* Number of blocks */
|
|
|
++ u32 size; /* Total size in bytes */
|
|
|
++};
|
|
|
++#endif /* CONFIG_SSB_SFLASH */
|
|
|
+ #endif /* CONFIG_SSB_DRIVER_MIPS */
|
|
|
+
|
|
|
+ struct ssb_chipcommon {
|
|
|
+@@ -605,6 +616,9 @@ struct ssb_chipcommon {
|
|
|
+ enum ssb_flash_type flash_type;
|
|
|
+ union {
|
|
|
+ struct ssb_pflash pflash;
|
|
|
++#ifdef CONFIG_SSB_SFLASH
|
|
|
++ struct ssb_sflash sflash;
|
|
|
++#endif /* CONFIG_SSB_SFLASH */
|
|
|
+ };
|
|
|
+ #endif /* CONFIG_SSB_DRIVER_MIPS */
|
|
|
+ };
|
|
|
+@@ -666,6 +680,18 @@ extern int ssb_chipco_serial_init(struct
|
|
|
+ struct ssb_serial_port *ports);
|
|
|
+ #endif /* CONFIG_SSB_SERIAL */
|
|
|
+
|
|
|
++#ifdef CONFIG_SSB_SFLASH
|
|
|
++/* Chipcommon sflash support. */
|
|
|
++int ssb_sflash_read(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
|
|
++ u8 *buf);
|
|
|
++int ssb_sflash_poll(struct ssb_chipcommon *cc, u32 offset);
|
|
|
++int ssb_sflash_write(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
|
|
++ const u8 *buf);
|
|
|
++int ssb_sflash_erase(struct ssb_chipcommon *cc, u32 offset);
|
|
|
++int ssb_sflash_commit(struct ssb_chipcommon *cc, u32 offset, u32 len,
|
|
|
++ const u8 *buf);
|
|
|
++#endif /* CONFIG_SSB_SFLASH */
|
|
|
++
|
|
|
+ /* PMU support */
|
|
|
+ extern void ssb_pmu_init(struct ssb_chipcommon *cc);
|
|
|
+
|