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@@ -356,7 +356,6 @@
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+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
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+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
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+ .flags = IORESOURCE_MEM
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+ .flags = IORESOURCE_MEM
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+ },
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+ },
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-+ { },
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+};
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+};
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+
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+
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+static struct plat_serial8250_port laguna_uart_data[] = {
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+static struct plat_serial8250_port laguna_uart_data[] = {
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@@ -388,6 +387,7 @@
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+ .uartclk = 24000000,
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+ .uartclk = 24000000,
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+ .type = PORT_16550A,
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+ .type = PORT_16550A,
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+ },
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+ },
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++ { },
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+};
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+};
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+
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+
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+static struct platform_device laguna_uart = {
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+static struct platform_device laguna_uart = {
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