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@@ -1,6 +1,6 @@
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--- a/arch/mips/include/asm/r4kcache.h
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+++ b/arch/mips/include/asm/r4kcache.h
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-@@ -25,6 +25,38 @@
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+@@ -26,6 +26,38 @@
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extern void (*r4k_blast_dcache)(void);
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extern void (*r4k_blast_icache)(void);
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@@ -39,7 +39,7 @@
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/*
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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-@@ -98,6 +130,7 @@ static inline void flush_icache_line_ind
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+@@ -99,6 +131,7 @@ static inline void flush_icache_line_ind
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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__dflush_prologue
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@@ -47,7 +47,7 @@
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cache_op(Index_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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-@@ -125,6 +158,7 @@ static inline void flush_icache_line(uns
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+@@ -126,6 +159,7 @@ static inline void flush_icache_line(uns
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static inline void flush_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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@@ -55,7 +55,7 @@
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cache_op(Hit_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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-@@ -132,6 +166,7 @@ static inline void flush_dcache_line(uns
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+@@ -133,6 +167,7 @@ static inline void flush_dcache_line(uns
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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@@ -63,7 +63,7 @@
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cache_op(Hit_Invalidate_D, addr);
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__dflush_epilogue
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}
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-@@ -205,6 +240,7 @@ static inline int protected_flush_icache
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+@@ -206,6 +241,7 @@ static inline int protected_flush_icache
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#ifdef CONFIG_EVA
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return protected_cachee_op(Hit_Invalidate_I, addr);
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#else
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@@ -71,7 +71,7 @@
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return protected_cache_op(Hit_Invalidate_I, addr);
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#endif
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}
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-@@ -218,6 +254,7 @@ static inline int protected_flush_icache
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+@@ -219,6 +255,7 @@ static inline int protected_flush_icache
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*/
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static inline int protected_writeback_dcache_line(unsigned long addr)
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{
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@@ -79,7 +79,7 @@
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#ifdef CONFIG_EVA
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return protected_cachee_op(Hit_Writeback_Inv_D, addr);
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#else
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-@@ -575,8 +612,51 @@ static inline void invalidate_tcache_pag
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+@@ -576,8 +613,51 @@ static inline void invalidate_tcache_pag
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: "r" (base), \
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"i" (op));
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@@ -132,7 +132,7 @@
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static inline void extra##blast_##pfx##cache##lsize(void) \
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{ \
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unsigned long start = INDEX_BASE; \
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-@@ -588,6 +668,7 @@ static inline void extra##blast_##pfx##c
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+@@ -589,6 +669,7 @@ static inline void extra##blast_##pfx##c
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\
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__##pfx##flush_prologue \
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\
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@@ -140,7 +140,7 @@
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws, indexop); \
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-@@ -602,6 +683,7 @@ static inline void extra##blast_##pfx##c
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+@@ -603,6 +684,7 @@ static inline void extra##blast_##pfx##c
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\
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__##pfx##flush_prologue \
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\
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@@ -148,7 +148,7 @@
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do { \
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cache##lsize##_unroll32(start, hitop); \
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start += lsize * 32; \
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-@@ -620,6 +702,8 @@ static inline void extra##blast_##pfx##c
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+@@ -621,6 +703,8 @@ static inline void extra##blast_##pfx##c
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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@@ -157,7 +157,7 @@
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__##pfx##flush_prologue \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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-@@ -629,26 +713,26 @@ static inline void extra##blast_##pfx##c
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+@@ -630,26 +714,26 @@ static inline void extra##blast_##pfx##c
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__##pfx##flush_epilogue \
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}
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@@ -204,7 +204,7 @@
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#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
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static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
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-@@ -677,53 +761,23 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
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+@@ -678,53 +762,23 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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/* build blast_xxx_range, protected_blast_xxx_range */
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@@ -266,7 +266,7 @@
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} \
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\
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__##pfx##flush_epilogue \
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-@@ -731,8 +785,8 @@ static inline void prot##extra##blast_##
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+@@ -732,8 +786,8 @@ static inline void prot##extra##blast_##
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#ifndef CONFIG_EVA
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@@ -277,7 +277,7 @@
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#else
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-@@ -769,14 +823,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
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+@@ -770,15 +824,15 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
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__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
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#endif
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@@ -298,7 +298,8 @@
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+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
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+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
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- #endif /* _ASM_R4KCACHE_H */
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+ /* Currently, this is very specific to Loongson-3 */
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+ #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \
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--- a/arch/mips/include/asm/stackframe.h
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+++ b/arch/mips/include/asm/stackframe.h
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@@ -428,6 +428,10 @@
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@@ -396,7 +397,7 @@
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if (dc_lsize == 0)
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r4k_blast_dcache = (void *)cache_noop;
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else if (dc_lsize == 16)
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-@@ -957,6 +969,8 @@ static void local_r4k_flush_cache_sigtra
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+@@ -986,6 +998,8 @@ static void local_r4k_flush_cache_sigtra
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}
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R4600_HIT_CACHEOP_WAR_IMPL;
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@@ -405,7 +406,7 @@
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if (!cpu_has_ic_fills_f_dc) {
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if (dc_lsize)
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vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
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-@@ -1851,6 +1865,17 @@ static void coherency_setup(void)
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+@@ -1880,6 +1894,17 @@ static void coherency_setup(void)
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* silly idea of putting something else there ...
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*/
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switch (current_cpu_type()) {
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@@ -423,7 +424,7 @@
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case CPU_R4000PC:
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case CPU_R4000SC:
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case CPU_R4000MC:
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-@@ -1897,6 +1922,15 @@ void r4k_cache_init(void)
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+@@ -1926,6 +1951,15 @@ void r4k_cache_init(void)
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extern void build_copy_page(void);
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struct cpuinfo_mips *c = ¤t_cpu_data;
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@@ -439,7 +440,7 @@
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probe_pcache();
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probe_vcache();
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setup_scache();
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-@@ -1974,7 +2008,15 @@ void r4k_cache_init(void)
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+@@ -2004,7 +2038,15 @@ void r4k_cache_init(void)
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*/
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local_r4k___flush_cache_all(NULL);
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