qualcommax: 6.6: remove completely

Remove all 6.6 only patches, config etc.

Signed-off-by: Robert Marko <[email protected]>

target/linux/qualcommax/config-6.6

@@ -1,583 +0,0 @@
-CONFIG_64BIT=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_FORCE_MAX_ORDER=10
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_ERRATUM_1165522=y
-CONFIG_ARM64_ERRATUM_1286807=y
-CONFIG_ARM64_ERRATUM_2051678=y
-CONFIG_ARM64_ERRATUM_2054223=y
-CONFIG_ARM64_ERRATUM_2067961=y
-CONFIG_ARM64_ERRATUM_2077057=y
-CONFIG_ARM64_ERRATUM_2658417=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
-CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
-CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_MHU_V2 is not set
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
-CONFIG_AT803X_PHY=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_PM=y
-CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
-CONFIG_CAVIUM_TX2_ERRATUM_219=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_COREDUMP=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_THERMAL=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MITIGATIONS=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRC8=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_QCE=y
-CONFIG_CRYPTO_DEV_QCE_AEAD=y
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
-CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
-CONFIG_CRYPTO_DEV_QCE_SHA=y
-CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
-CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_GF128MUL=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEV_COREDUMP=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FUJITSU_ERRATUM_010001=y
-CONFIG_FUNCTION_ALIGNMENT=4
-CONFIG_FUNCTION_ALIGNMENT_4B=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-# CONFIG_I2C_QCOM_CCI is not set
-CONFIG_I2C_QUP=y
-CONFIG_IIO=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IPQ5018_PHY is not set
-CONFIG_IPQ_APSS_6018=y
-CONFIG_IPQ_APSS_PLL=y
-# CONFIG_IPQ_CMN_PLL is not set
-# CONFIG_IPQ_GCC_4019 is not set
-# CONFIG_IPQ_GCC_5018 is not set
-# CONFIG_IPQ_GCC_5332 is not set
-# CONFIG_IPQ_GCC_6018 is not set
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_IPQ_GCC_9574 is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_KPSS_XCC is not set
-CONFIG_LEDS_TLC591XX=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_IPQ4019=y
-# CONFIG_MFD_QCOM_RPM is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MSM=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMU_LAZY_TLB_REFCOUNT=y
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MSM_GCC_8916 is not set
-# CONFIG_MSM_GCC_8917 is not set
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8976 is not set
-# CONFIG_MSM_GCC_8994 is not set
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_GCC_8998 is not set
-# CONFIG_MSM_GPUCC_8998 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-# CONFIG_MSM_MMCC_8998 is not set
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_QCOM=y
-CONFIG_MTD_QCOMSMEM_PARTS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_EGRESS=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_INGRESS=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_XGRESS=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_LAYOUT_ASCII_ENV=y
-CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y
-CONFIG_NVMEM_QCOM_QFPROM=y
-# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_U_BOOT_ENV=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PER_VMA_LOCK=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_EDP is not set
-# CONFIG_PHY_QCOM_EUSB2_REPEATER is not set
-# CONFIG_PHY_QCOM_IPQ4019_USB is not set
-# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_QCOM_M31_USB is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-CONFIG_PHY_QCOM_QMP=y
-CONFIG_PHY_QCOM_QMP_COMBO=y
-CONFIG_PHY_QCOM_QMP_PCIE=y
-CONFIG_PHY_QCOM_QMP_PCIE_8996=y
-CONFIG_PHY_QCOM_QMP_UFS=y
-CONFIG_PHY_QCOM_QMP_USB=y
-# CONFIG_PHY_QCOM_QMP_USB_LEGACY is not set
-CONFIG_PHY_QCOM_QUSB2=y
-# CONFIG_PHY_QCOM_SGMII_ETH is not set
-# CONFIG_PHY_QCOM_SNPS_EUSB2 is not set
-# CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP is not set
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_IPQ5018 is not set
-# CONFIG_PINCTRL_IPQ5332 is not set
-# CONFIG_PINCTRL_IPQ6018 is not set
-# CONFIG_PINCTRL_IPQ8074 is not set
-# CONFIG_PINCTRL_IPQ9574 is not set
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_MSM8916 is not set
-# CONFIG_PINCTRL_MSM8976 is not set
-# CONFIG_PINCTRL_MSM8994 is not set
-# CONFIG_PINCTRL_MSM8996 is not set
-# CONFIG_PINCTRL_MSM8998 is not set
-# CONFIG_PINCTRL_QCM2290 is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_QCS404 is not set
-# CONFIG_PINCTRL_QDU1000 is not set
-# CONFIG_PINCTRL_SA8775P is not set
-# CONFIG_PINCTRL_SC7180 is not set
-# CONFIG_PINCTRL_SC8280XP is not set
-# CONFIG_PINCTRL_SDM660 is not set
-# CONFIG_PINCTRL_SDM670 is not set
-# CONFIG_PINCTRL_SDM845 is not set
-# CONFIG_PINCTRL_SDX75 is not set
-# CONFIG_PINCTRL_SM6350 is not set
-# CONFIG_PINCTRL_SM6375 is not set
-# CONFIG_PINCTRL_SM7150 is not set
-# CONFIG_PINCTRL_SM8150 is not set
-# CONFIG_PINCTRL_SM8250 is not set
-# CONFIG_PINCTRL_SM8450 is not set
-# CONFIG_PINCTRL_SM8550 is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_OPP=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_MSM is not set
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCA807X_PHY=y
-CONFIG_QCA808X_PHY=y
-# CONFIG_QCM_DISPCC_2290 is not set
-# CONFIG_QCM_GCC_2290 is not set
-# CONFIG_QCOM_A53PLL is not set
-# CONFIG_QCOM_AOSS_QMP is not set
-CONFIG_QCOM_APCS_IPC=y
-# CONFIG_QCOM_APM is not set
-# CONFIG_QCOM_APR is not set
-CONFIG_QCOM_BAM_DMA=y
-# CONFIG_QCOM_CLK_APCC_MSM8996 is not set
-# CONFIG_QCOM_CLK_APCS_MSM8916 is not set
-# CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
-# CONFIG_QCOM_EBI2 is not set
-# CONFIG_QCOM_FASTRPC is not set
-# CONFIG_QCOM_GENI_SE is not set
-# CONFIG_QCOM_GSBI is not set
-# CONFIG_QCOM_HFPLL is not set
-# CONFIG_QCOM_ICC_BWMON is not set
-# CONFIG_QCOM_IPCC is not set
-# CONFIG_QCOM_LLCC is not set
-CONFIG_QCOM_MDT_LOADER=y
-# CONFIG_QCOM_MPM is not set
-CONFIG_QCOM_NET_PHYLIB=y
-# CONFIG_QCOM_OCMEM is not set
-# CONFIG_QCOM_PDC is not set
-CONFIG_QCOM_PIL_INFO=y
-# CONFIG_QCOM_Q6V5_ADSP is not set
-CONFIG_QCOM_Q6V5_COMMON=y
-# CONFIG_QCOM_Q6V5_MPD is not set
-# CONFIG_QCOM_Q6V5_MSS is not set
-# CONFIG_QCOM_Q6V5_PAS is not set
-CONFIG_QCOM_Q6V5_WCSS=y
-# CONFIG_QCOM_RAMP_CTRL is not set
-# CONFIG_QCOM_RMTFS_MEM is not set
-# CONFIG_QCOM_RPMH is not set
-# CONFIG_QCOM_RPM_MASTER_STATS is not set
-CONFIG_QCOM_RPROC_COMMON=y
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-# CONFIG_QCOM_SMD_RPM is not set
-CONFIG_QCOM_SMEM=y
-CONFIG_QCOM_SMEM_STATE=y
-CONFIG_QCOM_SMP2P=y
-# CONFIG_QCOM_SMSM is not set
-CONFIG_QCOM_SOCINFO=y
-# CONFIG_QCOM_SPM is not set
-# CONFIG_QCOM_STATS is not set
-# CONFIG_QCOM_SYSMON is not set
-CONFIG_QCOM_TSENS=y
-# CONFIG_QCOM_WCNSS_CTRL is not set
-# CONFIG_QCOM_WCNSS_PIL is not set
-CONFIG_QCOM_WDT=y
-# CONFIG_QCS_GCC_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_QCS_TURING_404 is not set
-# CONFIG_QDU_GCC_1000 is not set
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_CPR3 is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
-CONFIG_RELOCATABLE=y
-CONFIG_REMOTEPROC=y
-CONFIG_REMOTEPROC_CDEV=y
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPMSG=y
-CONFIG_RPMSG_CHAR=y
-# CONFIG_RPMSG_CTRL is not set
-# CONFIG_RPMSG_NS is not set
-CONFIG_RPMSG_QCOM_GLINK=y
-CONFIG_RPMSG_QCOM_GLINK_RPM=y
-CONFIG_RPMSG_QCOM_GLINK_SMEM=y
-CONFIG_RPMSG_QCOM_SMD=y
-# CONFIG_RPMSG_TTY is not set
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SA_GCC_8775P is not set
-# CONFIG_SA_GPUCC_8775P is not set
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_SMT=y
-CONFIG_SCHED_THERMAL_PRESSURE=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-# CONFIG_SC_CAMCC_7280 is not set
-# CONFIG_SC_DISPCC_7180 is not set
-# CONFIG_SC_DISPCC_8280XP is not set
-# CONFIG_SC_GCC_7180 is not set
-# CONFIG_SC_GCC_8280XP is not set
-# CONFIG_SC_GPUCC_7180 is not set
-# CONFIG_SC_LPASSCC_7280 is not set
-# CONFIG_SC_LPASSCC_8280XP is not set
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-# CONFIG_SC_LPASS_CORECC_7280 is not set
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-# CONFIG_SDM_CAMCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_GCC_660 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-# CONFIG_SDX_GCC_75 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-# CONFIG_SM_CAMCC_6350 is not set
-# CONFIG_SM_CAMCC_8450 is not set
-# CONFIG_SM_GCC_7150 is not set
-# CONFIG_SM_GCC_8150 is not set
-# CONFIG_SM_GCC_8250 is not set
-# CONFIG_SM_GCC_8450 is not set
-# CONFIG_SM_GCC_8550 is not set
-# CONFIG_SM_GPUCC_6115 is not set
-# CONFIG_SM_GPUCC_6125 is not set
-# CONFIG_SM_GPUCC_6350 is not set
-# CONFIG_SM_GPUCC_6375 is not set
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-# CONFIG_SM_GPUCC_8350 is not set
-# CONFIG_SM_GPUCC_8450 is not set
-# CONFIG_SM_GPUCC_8550 is not set
-# CONFIG_SM_TCSRCC_8550 is not set
-# CONFIG_SM_VIDEOCC_8150 is not set
-# CONFIG_SM_VIDEOCC_8250 is not set
-# CONFIG_SM_VIDEOCC_8350 is not set
-# CONFIG_SM_VIDEOCC_8450 is not set
-# CONFIG_SM_VIDEOCC_8550 is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_QPIC_SNAND is not set
-CONFIG_SPI_QUP=y
-CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_ANCHOR=y
-# CONFIG_VIRTIO_BLK is not set
-# CONFIG_VIRTIO_NET is not set
-CONFIG_VMAP_STACK=y
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y

target/linux/qualcommax/patches-6.6/0001-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch

@@ -1,29 +0,0 @@
-From 93e161c8f4b9b051e5e746814138cb5520b4b897 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Fri, 1 Sep 2023 20:10:04 +0200
-Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ8174 family
-
-IPQ8174 (Oak) family is part of the IPQ8074 family, but the ID-s for it
-are missing so lets add them.
-
-Signed-off-by: Robert Marko <[email protected]>
-Reviewed-by: Kathiravan T <[email protected]>
-Acked-by: Conor Dooley <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- include/dt-bindings/arm/qcom,ids.h | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/include/dt-bindings/arm/qcom,ids.h
-+++ b/include/dt-bindings/arm/qcom,ids.h
-@@ -203,6 +203,9 @@
- #define QCOM_ID_SM6125			394
- #define QCOM_ID_IPQ8070A		395
- #define QCOM_ID_IPQ8071A		396
-+#define QCOM_ID_IPQ8172			397
-+#define QCOM_ID_IPQ8173			398
-+#define QCOM_ID_IPQ8174			399
- #define QCOM_ID_IPQ6018			402
- #define QCOM_ID_IPQ6028			403
- #define QCOM_ID_SDM429W			416

target/linux/qualcommax/patches-6.6/0002-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch

@@ -1,123 +0,0 @@
-From 47e161a7873b0891f4e01a69a839f6161d816ea8 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Wed, 25 Oct 2023 14:57:57 +0530
-Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ6018
-
-IPQ6018 SoC series comes in multiple SKU-s, and not all of them support
-high frequency OPP points.
-
-SoC itself does however have a single bit in QFPROM to indicate the CPU
-speed-bin.
-That bit is used to indicate frequency limit of 1.5GHz, but that alone is
-not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to
-limit it further.
-
-IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device
-will get created by NVMEM CPUFreq driver.
-
-Signed-off-by: Robert Marko <[email protected]>
-[ Viresh: Fixed rebase conflict. ]
-Signed-off-by: Viresh Kumar <[email protected]>
----
- drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
- drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++
- 2 files changed, 59 insertions(+)
-
---- a/drivers/cpufreq/cpufreq-dt-platdev.c
-+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -177,6 +177,7 @@ static const struct of_device_id blockli
- 	{ .compatible = "ti,am625", },
- 	{ .compatible = "ti,am62a7", },
- 
-+	{ .compatible = "qcom,ipq6018", },
- 	{ .compatible = "qcom,ipq8064", },
- 	{ .compatible = "qcom,apq8064", },
- 	{ .compatible = "qcom,msm8974", },
---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
-@@ -30,6 +30,8 @@
- 
- #include <dt-bindings/arm/qcom,ids.h>
- 
-+#define IPQ6000_VERSION	BIT(2)
-+
- struct qcom_cpufreq_drv;
- 
- struct qcom_cpufreq_match_data {
-@@ -207,6 +209,57 @@ len_error:
- 	return ret;
- }
- 
-+static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
-+					     struct nvmem_cell *speedbin_nvmem,
-+					     char **pvs_name,
-+					     struct qcom_cpufreq_drv *drv)
-+{
-+	u32 msm_id;
-+	int ret;
-+	u8 *speedbin;
-+	*pvs_name = NULL;
-+
-+	ret = qcom_smem_get_soc_id(&msm_id);
-+	if (ret)
-+		return ret;
-+
-+	speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
-+	if (IS_ERR(speedbin))
-+		return PTR_ERR(speedbin);
-+
-+	switch (msm_id) {
-+	case QCOM_ID_IPQ6005:
-+	case QCOM_ID_IPQ6010:
-+	case QCOM_ID_IPQ6018:
-+	case QCOM_ID_IPQ6028:
-+		/* Fuse Value    Freq    BIT to set
-+		 * ---------------------------------
-+		 *   2’b0     No Limit     BIT(0)
-+		 *   2’b1     1.5 GHz      BIT(1)
-+		 */
-+		drv->versions = 1 << (unsigned int)(*speedbin);
-+		break;
-+	case QCOM_ID_IPQ6000:
-+		/*
-+		 * IPQ6018 family only has one bit to advertise the CPU
-+		 * speed-bin, but that is not enough for IPQ6000 which
-+		 * is only rated up to 1.2GHz.
-+		 * So for IPQ6000 manually set BIT(2) based on SMEM ID.
-+		 */
-+		drv->versions = IPQ6000_VERSION;
-+		break;
-+	default:
-+		dev_err(cpu_dev,
-+			"SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
-+			msm_id);
-+		drv->versions = IPQ6000_VERSION;
-+		break;
-+	}
-+
-+	kfree(speedbin);
-+	return 0;
-+}
-+
- static const struct qcom_cpufreq_match_data match_data_kryo = {
- 	.get_version = qcom_cpufreq_kryo_name_version,
- };
-@@ -221,6 +274,10 @@ static const struct qcom_cpufreq_match_d
- 	.genpd_names = qcs404_genpd_names,
- };
- 
-+static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
-+	.get_version = qcom_cpufreq_ipq6018_name_version,
-+};
-+
- static int qcom_cpufreq_probe(struct platform_device *pdev)
- {
- 	struct qcom_cpufreq_drv *drv;
-@@ -353,6 +410,7 @@ static const struct of_device_id qcom_cp
- 	{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
- 	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
- 	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
-+	{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
- 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
- 	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
- 	{ .compatible = "qcom,msm8974", .data = &match_data_krait },

target/linux/qualcommax/patches-6.6/0003-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch

@@ -1,113 +0,0 @@
-From 0b9cd949136f1b63f7aa9424b6e583a1ab261e36 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Fri, 13 Oct 2023 19:20:02 +0200
-Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
-
-IPQ8074 comes in 3 families:
-* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
-* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz
-* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
-
-So, in order to be able to share one OPP table lets add support for IPQ8074
-family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
-
-IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
-will get created by NVMEM CPUFreq driver.
-
-Signed-off-by: Robert Marko <[email protected]>
-Acked-by: Konrad Dybcio <[email protected]>
-[ Viresh: Fixed rebase conflict. ]
-Signed-off-by: Viresh Kumar <[email protected]>
----
- drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
- drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++
- 2 files changed, 49 insertions(+)
-
---- a/drivers/cpufreq/cpufreq-dt-platdev.c
-+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -179,6 +179,7 @@ static const struct of_device_id blockli
- 
- 	{ .compatible = "qcom,ipq6018", },
- 	{ .compatible = "qcom,ipq8064", },
-+	{ .compatible = "qcom,ipq8074", },
- 	{ .compatible = "qcom,apq8064", },
- 	{ .compatible = "qcom,msm8974", },
- 	{ .compatible = "qcom,msm8960", },
---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
-@@ -32,6 +32,11 @@
- 
- #define IPQ6000_VERSION	BIT(2)
- 
-+enum ipq8074_versions {
-+	IPQ8074_HAWKEYE_VERSION = 0,
-+	IPQ8074_ACORN_VERSION,
-+};
-+
- struct qcom_cpufreq_drv;
- 
- struct qcom_cpufreq_match_data {
-@@ -260,6 +265,44 @@ static int qcom_cpufreq_ipq6018_name_ver
- 	return 0;
- }
- 
-+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
-+					     struct nvmem_cell *speedbin_nvmem,
-+					     char **pvs_name,
-+					     struct qcom_cpufreq_drv *drv)
-+{
-+	u32 msm_id;
-+	int ret;
-+	*pvs_name = NULL;
-+
-+	ret = qcom_smem_get_soc_id(&msm_id);
-+	if (ret)
-+		return ret;
-+
-+	switch (msm_id) {
-+	case QCOM_ID_IPQ8070A:
-+	case QCOM_ID_IPQ8071A:
-+	case QCOM_ID_IPQ8172:
-+	case QCOM_ID_IPQ8173:
-+	case QCOM_ID_IPQ8174:
-+		drv->versions = BIT(IPQ8074_ACORN_VERSION);
-+		break;
-+	case QCOM_ID_IPQ8072A:
-+	case QCOM_ID_IPQ8074A:
-+	case QCOM_ID_IPQ8076A:
-+	case QCOM_ID_IPQ8078A:
-+		drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
-+		break;
-+	default:
-+		dev_err(cpu_dev,
-+			"SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
-+			msm_id);
-+		drv->versions = BIT(IPQ8074_ACORN_VERSION);
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
- static const struct qcom_cpufreq_match_data match_data_kryo = {
- 	.get_version = qcom_cpufreq_kryo_name_version,
- };
-@@ -278,6 +321,10 @@ static const struct qcom_cpufreq_match_d
- 	.get_version = qcom_cpufreq_ipq6018_name_version,
- };
- 
-+static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
-+	.get_version = qcom_cpufreq_ipq8074_name_version,
-+};
-+
- static int qcom_cpufreq_probe(struct platform_device *pdev)
- {
- 	struct qcom_cpufreq_drv *drv;
-@@ -412,6 +459,7 @@ static const struct of_device_id qcom_cp
- 	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
- 	{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
- 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
-+	{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
- 	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
- 	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
- 	{ .compatible = "qcom,msm8960", .data = &match_data_krait },

target/linux/qualcommax/patches-6.6/0004-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch

@@ -1,43 +0,0 @@
-From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001
-From: Kathiravan Thirumoorthy <[email protected]>
-Date: Thu, 14 Sep 2023 12:29:57 +0530
-Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock
- provider
-
-While the kernel is booting up, APSS PLL will be running at 800MHz with
-GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
-configured and select the rate based on the opp table and the source will
-be changed to APSS_PLL_EARLY.
-
-Without this patch, CPU Freq driver reports that CPU is running at 24MHz
-instead of the 800MHz.
-
-Reviewed-by: Konrad Dybcio <[email protected]>
-Tested-by: Robert Marko <[email protected]>
-Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
----
- drivers/clk/qcom/apss-ipq6018.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/clk/qcom/apss-ipq6018.c
-+++ b/drivers/clk/qcom/apss-ipq6018.c
-@@ -20,16 +20,19 @@
- 
- enum {
- 	P_XO,
-+	P_GPLL0,
- 	P_APSS_PLL_EARLY,
- };
- 
- static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
- 	{ .fw_name = "xo" },
-+	{ .fw_name = "gpll0" },
- 	{ .fw_name = "pll" },
- };
- 
- static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
- 	{ P_XO, 0 },
-+	{ P_GPLL0, 4 },
- 	{ P_APSS_PLL_EARLY, 5 },
- };
- 

target/linux/qualcommax/patches-6.6/0005-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch

@@ -1,32 +0,0 @@
-From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001
-From: Kathiravan Thirumoorthy <[email protected]>
-Date: Thu, 14 Sep 2023 12:29:58 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock
- provider for mailbox
-
-While the kernel is booting up, APSS PLL will be running at 800MHz with
-GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
-configured to the rate based on the opp table and the source also will
-be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
-with this inclusion, CPU Freq correctly reports that CPU is running at
-800MHz rather than 24MHz.
-
-Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -723,8 +723,8 @@
- 			compatible = "qcom,ipq8074-apcs-apps-global",
- 				     "qcom,ipq6018-apcs-apps-global";
- 			reg = <0x0b111000 0x1000>;
--			clocks = <&a53pll>, <&xo>;
--			clock-names = "pll", "xo";
-+			clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
-+			clock-names = "pll", "xo", "gpll0";
- 
- 			#clock-cells = <1>;
- 			#mbox-cells = <1>;

target/linux/qualcommax/patches-6.6/0006-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch

@@ -1,35 +0,0 @@
-From 0133c7af3aa0420778d106cb90db708cfa45f2c6 Mon Sep 17 00:00:00 2001
-From: Kathiravan Thirumoorthy <[email protected]>
-Date: Thu, 14 Sep 2023 12:29:59 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock
- provider for mailbox
-
-While the kernel is booting up, APSS clock / CPU clock will be running
-at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
-APSS PLL will be configured to the rate based on the opp table and the
-source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
-consume the GPLL0, with this inclusion, CPU Freq correctly reports that
-CPU is running at 800MHz rather than 24MHz.
-
-Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-[bjorn: Updated commit message, as requested by Kathiravan]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -620,8 +620,8 @@
- 			compatible = "qcom,ipq6018-apcs-apps-global";
- 			reg = <0x0 0x0b111000 0x0 0x1000>;
- 			#clock-cells = <1>;
--			clocks = <&a53pll>, <&xo>;
--			clock-names = "pll", "xo";
-+			clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
-+			clock-names = "pll", "xo", "gpll0";
- 			#mbox-cells = <1>;
- 		};
- 

target/linux/qualcommax/patches-6.6/0007-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch

@@ -1,57 +0,0 @@
-From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Sat, 21 Oct 2023 13:55:18 +0200
-Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock
-
-QUP6 I2C clock is listed in the dt bindings but it was never included in
-the GCC driver.
-So lets add support for it, it is marked as criticial as it is used by RPM
-to communicate to the external PMIC over I2C so this clock must not be
-disabled.
-
-Signed-off-by: Robert Marko <[email protected]>
-Reviewed-by: Kathiravan Thirumoorthy <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq6018.c
-+++ b/drivers/clk/qcom/gcc-ipq6018.c
-@@ -2121,6 +2121,26 @@ static struct clk_branch gcc_blsp1_qup5_
- 	},
- };
- 
-+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
-+	.halt_reg = 0x07010,
-+	.clkr = {
-+		.enable_reg = 0x07010,
-+		.enable_mask = BIT(0),
-+		.hw.init = &(struct clk_init_data){
-+			.name = "gcc_blsp1_qup6_i2c_apps_clk",
-+			.parent_hws = (const struct clk_hw *[]){
-+					&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
-+			.num_parents = 1,
-+			/*
-+			 * RPM uses QUP6 I2C to communicate with the external
-+			 * PMIC so it must not be disabled.
-+			 */
-+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+			.ops = &clk_branch2_ops,
-+		},
-+	},
-+};
-+
- static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
- 	.halt_reg = 0x0700c,
- 	.clkr = {
-@@ -4277,6 +4297,7 @@ static struct clk_regmap *gcc_ipq6018_cl
- 	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
- 	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
- 	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
-+	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
- 	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
- 	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
- 	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,

target/linux/qualcommax/patches-6.6/0008-v6.8-arm64-dts-qcom-ipq6018-use-CPUFreq-NVMEM.patch

@@ -1,85 +0,0 @@
-From 83afcf14edb9217e58837eb119da96d734a4b3b1 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Sat, 21 Oct 2023 14:00:07 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM
-
-IPQ6018 comes in multiple SKU-s and some of them dont support all of the
-OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
-supported OPP-s based on the SoC dynamically.
-
-As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
-goes up to 1.5GHz and is marked as such via an eFuse.
-
-Signed-off-by: Robert Marko <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
- 1 file changed, 13 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -96,42 +96,49 @@
- 	};
- 
- 	cpu_opp_table: opp-table-cpu {
--		compatible = "operating-points-v2";
-+		compatible = "operating-points-v2-kryo-cpu";
-+		nvmem-cells = <&cpu_speed_bin>;
- 		opp-shared;
- 
- 		opp-864000000 {
- 			opp-hz = /bits/ 64 <864000000>;
- 			opp-microvolt = <725000>;
-+			opp-supported-hw = <0xf>;
- 			clock-latency-ns = <200000>;
- 		};
- 
- 		opp-1056000000 {
- 			opp-hz = /bits/ 64 <1056000000>;
- 			opp-microvolt = <787500>;
-+			opp-supported-hw = <0xf>;
- 			clock-latency-ns = <200000>;
- 		};
- 
- 		opp-1320000000 {
- 			opp-hz = /bits/ 64 <1320000000>;
- 			opp-microvolt = <862500>;
-+			opp-supported-hw = <0x3>;
- 			clock-latency-ns = <200000>;
- 		};
- 
- 		opp-1440000000 {
- 			opp-hz = /bits/ 64 <1440000000>;
- 			opp-microvolt = <925000>;
-+			opp-supported-hw = <0x3>;
- 			clock-latency-ns = <200000>;
- 		};
- 
- 		opp-1608000000 {
- 			opp-hz = /bits/ 64 <1608000000>;
- 			opp-microvolt = <987500>;
-+			opp-supported-hw = <0x1>;
- 			clock-latency-ns = <200000>;
- 		};
- 
- 		opp-1800000000 {
- 			opp-hz = /bits/ 64 <1800000000>;
- 			opp-microvolt = <1062500>;
-+			opp-supported-hw = <0x1>;
- 			clock-latency-ns = <200000>;
- 		};
- 	};
-@@ -322,6 +329,11 @@
- 			reg = <0x0 0x000a4000 0x0 0x2000>;
- 			#address-cells = <1>;
- 			#size-cells = <1>;
-+
-+			cpu_speed_bin: cpu-speed-bin@135 {
-+				reg = <0x135 0x1>;
-+				bits = <7 1>;
-+			};
- 		};
- 
- 		prng: qrng@e3000 {

target/linux/qualcommax/patches-6.6/0009-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch

@@ -1,81 +0,0 @@
-From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <[email protected]>
-Date: Sun, 3 Dec 2023 23:39:14 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node
-
-Add node to support all the QUP UART node controller inside of IPQ6018.
-Some routers use these bus to connect Bluetooth chips.
-
-Signed-off-by: Chukun Pan <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++
- 1 file changed, 50 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -459,6 +459,26 @@
- 			qcom,ee = <0>;
- 		};
- 
-+		blsp1_uart1: serial@78af000 {
-+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+			reg = <0x0 0x78af000 0x0 0x200>;
-+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
-+			status = "disabled";
-+		};
-+
-+		blsp1_uart2: serial@78b0000 {
-+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+			reg = <0x0 0x78b0000 0x0 0x200>;
-+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
-+			status = "disabled";
-+		};
-+
- 		blsp1_uart3: serial@78b1000 {
- 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- 			reg = <0x0 0x078b1000 0x0 0x200>;
-@@ -467,6 +487,36 @@
- 				 <&gcc GCC_BLSP1_AHB_CLK>;
- 			clock-names = "core", "iface";
- 			status = "disabled";
-+		};
-+
-+		blsp1_uart4: serial@78b2000 {
-+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+			reg = <0x0 0x078b2000 0x0 0x200>;
-+			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
-+			status = "disabled";
-+		};
-+
-+		blsp1_uart5: serial@78b3000 {
-+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+			reg = <0x0 0x78b3000 0x0 0x200>;
-+			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
-+			status = "disabled";
-+		};
-+
-+		blsp1_uart6: serial@78b4000 {
-+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+			reg = <0x0 0x078b4000 0x0 0x200>;
-+			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
-+			status = "disabled";
- 		};
- 
- 		blsp1_spi1: spi@78b5000 {

target/linux/qualcommax/patches-6.6/0010-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch

@@ -1,95 +0,0 @@
-From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001
-From: Krishna Kurapati <[email protected]>
-Date: Fri, 26 Jan 2024 00:29:18 +0530
-Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
-
-On several QUSB2 Targets, the hs_phy_irq mentioned is actually
-qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
-to qusb2_phy for such targets.
-
-In actuality, the hs_phy_irq is also present in these targets, but
-kept in for debug purposes in hw test environments. This is not
-triggered by default and its functionality is mutually exclusive
-to that of qusb2_phy interrupt.
-
-Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
-Add missing ss_phy_irq on some targets which allows for remote
-wakeup to work on a Super Speed link.
-
-Also modify order of interrupts in accordance to bindings update.
-Since driver looks up for interrupts by name and not by index, it
-is safe to modify order of these interrupts in the DT.
-
-Signed-off-by: Krishna Kurapati <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
- arch/arm64/boot/dts/qcom/msm8953.dtsi |  7 +++++--
- arch/arm64/boot/dts/qcom/msm8996.dtsi |  8 ++++++--
- arch/arm64/boot/dts/qcom/msm8998.dtsi |  7 +++++--
- arch/arm64/boot/dts/qcom/sdm630.dtsi  | 17 +++++++++++++----
- arch/arm64/boot/dts/qcom/sm6115.dtsi  |  9 +++++++--
- arch/arm64/boot/dts/qcom/sm6125.dtsi  |  9 +++++++--
- 8 files changed, 70 insertions(+), 14 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -431,6 +431,12 @@
- 					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
- 			assigned-clock-rates = <133330000>,
- 					       <24000000>;
-+
-+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "pwr_event",
-+					  "qusb2_phy";
-+
- 			resets = <&gcc GCC_USB1_BCR>;
- 			status = "disabled";
- 
-@@ -629,6 +635,13 @@
- 					       <133330000>,
- 					       <24000000>;
- 
-+			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "pwr_event",
-+					  "qusb2_phy",
-+					  "ss_phy_irq";
-+
- 			resets = <&gcc GCC_USB0_BCR>;
- 			status = "disabled";
- 
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -632,6 +632,13 @@
- 						<133330000>,
- 						<19200000>;
- 
-+			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "pwr_event",
-+					  "qusb2_phy",
-+					  "ss_phy_irq";
-+
- 			power-domains = <&gcc USB0_GDSC>;
- 
- 			resets = <&gcc GCC_USB0_BCR>;
-@@ -675,6 +682,13 @@
- 						<133330000>,
- 						<19200000>;
- 
-+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "pwr_event",
-+					  "qusb2_phy",
-+					  "ss_phy_irq";
-+
- 			power-domains = <&gcc USB1_GDSC>;
- 
- 			resets = <&gcc GCC_USB1_BCR>;

target/linux/qualcommax/patches-6.6/0011-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch

@@ -1,32 +0,0 @@
-From c3dc3d079d191c9149496b3c7fe1ece909386d93 Mon Sep 17 00:00:00 2001
-From: Vignesh Viswanathan <[email protected]>
-Date: Tue, 5 Sep 2023 15:25:35 +0530
-Subject: [PATCH] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible
-
-IPQ6018 has 32 tcsr_mutex hwlock registers with stride 0x1000.
-The compatible string qcom,ipq6018-tcsr-mutex is mapped to
-of_msm8226_tcsr_mutex which has 32 locks configured with stride of 0x80
-and doesn't match the HW present in IPQ6018.
-
-Remove IPQ6018 specific compatible string so that it fallsback to
-of_tcsr_mutex data which maps to the correct configuration for IPQ6018.
-
-Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs")
-Signed-off-by: Vignesh Viswanathan <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- drivers/hwspinlock/qcom_hwspinlock.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/drivers/hwspinlock/qcom_hwspinlock.c
-+++ b/drivers/hwspinlock/qcom_hwspinlock.c
-@@ -115,7 +115,6 @@ static const struct of_device_id qcom_hw
- 	{ .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex },
- 	{ .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
- 	{ .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
--	{ .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
- 	{ .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
- 	{ .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
- 	{ .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },

target/linux/qualcommax/patches-6.6/0012-v6.9-arm64-dts-qcom-ipq6018-add-tsens-node.patch

@@ -1,34 +0,0 @@
-From 0b17197055b528da22e9385200e61b847b499d48 Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <[email protected]>
-Date: Thu, 25 Jan 2024 11:04:11 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add tsens node
-
-IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add
-node for it.
-
-Signed-off-by: Mantas Pucka <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -343,6 +343,16 @@
- 			clock-names = "core";
- 		};
- 
-+		tsens: thermal-sensor@4a9000 {
-+			compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens";
-+			reg = <0x0 0x004a9000 0x0 0x1000>,
-+			      <0x0 0x004a8000 0x0 0x1000>;
-+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "combined";
-+			#qcom,sensors = <16>;
-+			#thermal-sensor-cells = <1>;
-+		};
-+
- 		cryptobam: dma-controller@704000 {
- 			compatible = "qcom,bam-v1.7.0";
- 			reg = <0x0 0x00704000 0x0 0x20000>;

target/linux/qualcommax/patches-6.6/0013-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch

@@ -1,180 +0,0 @@
-From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <[email protected]>
-Date: Thu, 25 Jan 2024 11:04:12 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones
-
-Add thermal zones to make use of thermal sensors data. For CPU zone,
-add cooling device that uses CPU frequency scaling.
-
-Signed-off-by: Mantas Pucka <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++
- 1 file changed, 121 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -9,6 +9,7 @@
- #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
- #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
- #include <dt-bindings/clock/qcom,apss-ipq.h>
-+#include <dt-bindings/thermal/thermal.h>
- 
- / {
- 	#address-cells = <2>;
-@@ -43,6 +44,7 @@
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
- 			cpu-supply = <&ipq6018_s2>;
-+			#cooling-cells = <2>;
- 		};
- 
- 		CPU1: cpu@1 {
-@@ -55,6 +57,7 @@
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
- 			cpu-supply = <&ipq6018_s2>;
-+			#cooling-cells = <2>;
- 		};
- 
- 		CPU2: cpu@2 {
-@@ -67,6 +70,7 @@
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
- 			cpu-supply = <&ipq6018_s2>;
-+			#cooling-cells = <2>;
- 		};
- 
- 		CPU3: cpu@3 {
-@@ -79,6 +83,7 @@
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
- 			cpu-supply = <&ipq6018_s2>;
-+			#cooling-cells = <2>;
- 		};
- 
- 		L2_0: l2-cache {
-@@ -890,6 +895,122 @@
- 		};
- 	};
- 
-+	thermal-zones {
-+		nss-top-thermal {
-+			polling-delay-passive = <250>;
-+			polling-delay = <1000>;
-+			thermal-sensors = <&tsens 4>;
-+
-+			trips {
-+				nss-top-critical {
-+					temperature = <125000>;
-+					hysteresis = <1000>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		nss-thermal {
-+			polling-delay-passive = <250>;
-+			polling-delay = <1000>;
-+			thermal-sensors = <&tsens 5>;
-+
-+			trips {
-+				nss-critical {
-+					temperature = <125000>;
-+					hysteresis = <1000>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		wcss-phya0-thermal {
-+			polling-delay-passive = <250>;
-+			polling-delay = <1000>;
-+			thermal-sensors = <&tsens 7>;
-+
-+			trips {
-+				wcss-phya0-critical {
-+					temperature = <125000>;
-+					hysteresis = <1000>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		wcss-phya1-thermal {
-+			polling-delay-passive = <250>;
-+			polling-delay = <1000>;
-+			thermal-sensors = <&tsens 8>;
-+
-+			trips {
-+				wcss-phya1-critical {
-+					temperature = <125000>;
-+					hysteresis = <1000>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		cpu-thermal {
-+			polling-delay-passive = <250>;
-+			polling-delay = <1000>;
-+			thermal-sensors = <&tsens 13>;
-+
-+			trips {
-+				cpu-critical {
-+					temperature = <125000>;
-+					hysteresis = <1000>;
-+					type = "critical";
-+				};
-+
-+				cpu_alert: cpu-passive {
-+					temperature = <110000>;
-+					hysteresis = <1000>;
-+					type = "passive";
-+				};
-+			};
-+
-+			cooling-maps {
-+				map0 {
-+					trip = <&cpu_alert>;
-+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+				};
-+			};
-+		};
-+
-+		lpass-thermal {
-+			polling-delay-passive = <250>;
-+			polling-delay = <1000>;
-+			thermal-sensors = <&tsens 14>;
-+
-+			trips {
-+				lpass-critical {
-+					temperature = <125000>;
-+					hysteresis = <1000>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		ddrss-top-thermal {
-+			polling-delay-passive = <250>;
-+			polling-delay = <1000>;
-+			thermal-sensors = <&tsens 15>;
-+
-+			trips {
-+				ddrss-top-critical {
-+					temperature = <125000>;
-+					hysteresis = <1000>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+	};
-+
- 	timer {
- 		compatible = "arm,armv8-timer";
- 		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

target/linux/qualcommax/patches-6.6/0014-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch

@@ -1,50 +0,0 @@
-From fd712118aa1aa758da1fd1546b3f8a1b00e42cbc Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <[email protected]>
-Date: Tue, 23 Jan 2024 11:26:09 +0200
-Subject: [PATCH] clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi
- operation
-
-Without it system hangs upon wifi firmware load. It should be enabled by
-remoteproc/wifi driver. Bindings already exist for it, so add it based
-on vendor code.
-
-Signed-off-by: Mantas Pucka <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- drivers/clk/qcom/gcc-ipq6018.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq6018.c
-+++ b/drivers/clk/qcom/gcc-ipq6018.c
-@@ -3524,6 +3524,22 @@ static struct clk_branch gcc_prng_ahb_cl
- 	},
- };
- 
-+static struct clk_branch gcc_qdss_at_clk = {
-+	.halt_reg = 0x29024,
-+	.clkr = {
-+		.enable_reg = 0x29024,
-+		.enable_mask = BIT(0),
-+		.hw.init = &(struct clk_init_data){
-+			.name = "gcc_qdss_at_clk",
-+			.parent_hws = (const struct clk_hw *[]){
-+				&qdss_at_clk_src.clkr.hw },
-+			.num_parents = 1,
-+			.flags = CLK_SET_RATE_PARENT,
-+			.ops = &clk_branch2_ops,
-+		},
-+	},
-+};
-+
- static struct clk_branch gcc_qdss_dap_clk = {
- 	.halt_reg = 0x29084,
- 	.clkr = {
-@@ -4363,6 +4379,7 @@ static struct clk_regmap *gcc_ipq6018_cl
- 	[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
- 	[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
- 	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
-+	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
- 	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
- 	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
- 	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,

target/linux/qualcommax/patches-6.6/0015-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch

@@ -1,58 +0,0 @@
-From 62a5df451ab911421da96655fcc4d1e269ff6e2f Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <[email protected]>
-Date: Tue, 23 Jan 2024 18:09:20 +0200
-Subject: [PATCH] phy: qcom-qmp-usb: fix serdes init sequence for IPQ6018
-
-Commit 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
-noted that IPQ6018 init is identical to IPQ8074. Yet downstream uses
-separate serdes init sequence for IPQ6018. Since already existing IPQ9574
-serdes init sequence is identical, just reuse it and fix failing USB3 mode
-in IPQ6018.
-
-Fixes: 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
-Signed-off-by: Mantas Pucka <[email protected]>
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Vinod Koul <[email protected]>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++++++++++++++++-
- 1 file changed, 19 insertions(+), 1 deletion(-)
-
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -1314,6 +1314,26 @@ static const struct qmp_usb_offsets qmp_
- 	.rx		= 0x1000,
- };
- 
-+static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
-+	.lanes			= 1,
-+
-+	.serdes_tbl		= ipq9574_usb3_serdes_tbl,
-+	.serdes_tbl_num		= ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
-+	.tx_tbl			= msm8996_usb3_tx_tbl,
-+	.tx_tbl_num		= ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+	.rx_tbl			= ipq8074_usb3_rx_tbl,
-+	.rx_tbl_num		= ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+	.pcs_tbl		= ipq8074_usb3_pcs_tbl,
-+	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+	.clk_list		= msm8996_phy_clk_l,
-+	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
-+	.reset_list		= msm8996_usb3phy_reset_l,
-+	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+	.vreg_list		= qmp_phy_vreg_l,
-+	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
-+	.regs			= qmp_v3_usb3phy_regs_layout,
-+};
-+
- static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
- 	.lanes			= 1,
- 
-@@ -2239,7 +2259,7 @@ err_node_put:
- static const struct of_device_id qmp_usb_of_match_table[] = {
- 	{
- 		.compatible = "qcom,ipq6018-qmp-usb3-phy",
--		.data = &ipq8074_usb3phy_cfg,
-+		.data = &ipq6018_usb3phy_cfg,
- 	}, {
- 		.compatible = "qcom,ipq8074-qmp-usb3-phy",
- 		.data = &ipq8074_usb3phy_cfg,

target/linux/qualcommax/patches-6.6/0016-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch

@@ -1,38 +0,0 @@
-From 6a25e70214fde6dcf900271c819c8d7fe7b9a4b0 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Thu, 23 Nov 2023 13:12:54 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP4 SPI node
-
-Add node to support the QUP4 SPI controller inside of IPQ8074.
-Some devices use this bus to communicate to a Bluetooth controller.
-
-Signed-off-by: Robert Marko <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -536,6 +536,20 @@
- 			status = "disabled";
- 		};
- 
-+		blsp1_spi4: spi@78b8000 {
-+			compatible = "qcom,spi-qup-v2.2.1";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x78b8000 0x600>;
-+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
-+			dmas = <&blsp_dma 18>, <&blsp_dma 19>;
-+			dma-names = "tx", "rx";
-+			status = "disabled";
-+		};
-+
- 		blsp1_i2c5: i2c@78b9000 {
- 			compatible = "qcom,i2c-qup-v2.2.1";
- 			#address-cells = <1>;

target/linux/qualcommax/patches-6.6/0017-v6.9-arm64-dts-qcom-ipq8074-Remove-unused-gpio-from-QPIC-.patch

@@ -1,32 +0,0 @@
-From 5f78d9213ae753e2242b0f6a5d4a5e98e55ddc76 Mon Sep 17 00:00:00 2001
-From: Paweł Owoc <[email protected]>
-Date: Wed, 13 Mar 2024 11:27:06 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins
-
-gpio16 will only be used for LCD support, as its NAND/LCDC data[8]
-so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8
-or 16-bit with only 8-bit one being supported in our case so that pin
-is unused.
-
-It should be dropped from the default NAND pinctrl configuration
-as its unused and only needed for LCD.
-
-Signed-off-by: Paweł Owoc <[email protected]>
-Reviewed-by: Kathiravan Thirumoorthy <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -372,7 +372,7 @@
- 				       "gpio5", "gpio6", "gpio7",
- 				       "gpio8", "gpio10", "gpio11",
- 				       "gpio12", "gpio13", "gpio14",
--				       "gpio15", "gpio16", "gpio17";
-+				       "gpio15", "gpio17";
- 				function = "qpic";
- 				drive-strength = <8>;
- 				bias-disable;

target/linux/qualcommax/patches-6.6/0018-v6.7-arm64-dts-qcom-ipq5018-add-watchdog.patch

@@ -1,31 +0,0 @@
-From 9cbaee8379e620f82112002f973adde19679df31 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Wed, 16 Aug 2023 18:14:00 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq5018: add watchdog
-
-Add the required DT node for watchdog operation.
-
-Signed-off-by: Robert Marko <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -181,6 +181,13 @@
- 			};
- 		};
- 
-+		watchdog: watchdog@b017000 {
-+			compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt";
-+			reg = <0x0b017000 0x40>;
-+			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
-+			clocks = <&sleep_clk>;
-+		};
-+
- 		timer@b120000 {
- 			compatible = "arm,armv7-timer-mem";
- 			reg = <0x0b120000 0x1000>;

target/linux/qualcommax/patches-6.6/0019-v6.7-dt-bindings-firmware-qcom-scm-support-indicating-SDI-default-state.patch

@@ -1,41 +0,0 @@
-From 92dab9ea5f389c12828283146c60054642453a91 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Wed, 16 Aug 2023 18:45:38 +0200
-Subject: [PATCH] dt-bindings: firmware: qcom,scm: support indicating SDI
- default state
-
-IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that
-means that WDT being asserted or just trying to reboot will hang the board
-in the debug mode and only pulling the power and repowering will help.
-Some IPQ4019 boards like Google WiFI have it enabled as well.
-
-So, lets add a boolean property to indicate that SDI is enabled by default
-and thus needs to be disabled by the kernel.
-
-Signed-off-by: Robert Marko <[email protected]>
-Acked-by: Mukesh Ojha <[email protected]>
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
-Reviewed-by: Brian Norris <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
-+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
-@@ -89,6 +89,14 @@ properties:
-       protocol to handle sleeping SCM calls.
-     maxItems: 1
- 
-+  qcom,sdi-enabled:
-+    description:
-+      Indicates that the SDI (Secure Debug Image) has been enabled by TZ
-+      by default and it needs to be disabled.
-+      If not disabled WDT assertion or reboot will cause the board to hang
-+      in the debug mode.
-+    type: boolean
-+
-   qcom,dload-mode:
-     $ref: /schemas/types.yaml#/definitions/phandle-array
-     items:

target/linux/qualcommax/patches-6.6/0020-v6.7-firmware-qcom-scm-disable-SDI-if-required.patch

@@ -1,83 +0,0 @@
-From ff4aa3bc98258a240b9bbab53fd8d2fb8184c485 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Wed, 16 Aug 2023 18:45:39 +0200
-Subject: [PATCH] firmware: qcom_scm: disable SDI if required
-
-IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that
-means that WDT being asserted or just trying to reboot will hang the board
-in the debug mode and only pulling the power and repowering will help.
-Some IPQ4019 boards like Google WiFI have it enabled as well.
-
-Luckily, SDI can be disabled via an SCM call.
-
-So, lets use the boolean DT property to identify boards that have SDI
-enabled by default and use the SCM call to disable SDI during SCM probe.
-It is important to disable it as soon as possible as we might have a WDT
-assertion at any time which would then leave the board in debug mode,
-thus disabling it during SCM removal is not enough.
-
-Signed-off-by: Robert Marko <[email protected]>
-Reviewed-by: Guru Das Srinagesh <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- drivers/firmware/qcom_scm.c | 30 ++++++++++++++++++++++++++++++
- drivers/firmware/qcom_scm.h |  1 +
- 2 files changed, 31 insertions(+)
-
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -410,6 +410,29 @@ int qcom_scm_set_remote_state(u32 state,
- }
- EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state);
- 
-+static int qcom_scm_disable_sdi(void)
-+{
-+	int ret;
-+	struct qcom_scm_desc desc = {
-+		.svc = QCOM_SCM_SVC_BOOT,
-+		.cmd = QCOM_SCM_BOOT_SDI_CONFIG,
-+		.args[0] = 1, /* Disable watchdog debug */
-+		.args[1] = 0, /* Disable SDI */
-+		.arginfo = QCOM_SCM_ARGS(2),
-+		.owner = ARM_SMCCC_OWNER_SIP,
-+	};
-+	struct qcom_scm_res res;
-+
-+	ret = qcom_scm_clk_enable();
-+	if (ret)
-+		return ret;
-+	ret = qcom_scm_call(__scm->dev, &desc, &res);
-+
-+	qcom_scm_clk_disable();
-+
-+	return ret ? : res.result[0];
-+}
-+
- static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
- {
- 	struct qcom_scm_desc desc = {
-@@ -1474,6 +1497,13 @@ static int qcom_scm_probe(struct platfor
- 
- 	__get_convention();
- 
-+
-+	/*
-+	 * Disable SDI if indicated by DT that it is enabled by default.
-+	 */
-+	if (of_property_read_bool(pdev->dev.of_node, "qcom,sdi-enabled"))
-+		qcom_scm_disable_sdi();
-+
- 	/*
- 	 * If requested enable "download mode", from this point on warmboot
- 	 * will cause the boot stages to enter download mode, unless
---- a/drivers/firmware/qcom_scm.h
-+++ b/drivers/firmware/qcom_scm.h
-@@ -80,6 +80,7 @@ extern int scm_legacy_call(struct device
- #define QCOM_SCM_SVC_BOOT		0x01
- #define QCOM_SCM_BOOT_SET_ADDR		0x01
- #define QCOM_SCM_BOOT_TERMINATE_PC	0x02
-+#define QCOM_SCM_BOOT_SDI_CONFIG	0x09
- #define QCOM_SCM_BOOT_SET_DLOAD_MODE	0x10
- #define QCOM_SCM_BOOT_SET_ADDR_MC	0x11
- #define QCOM_SCM_BOOT_SET_REMOTE_STATE	0x0a

target/linux/qualcommax/patches-6.6/0021-v6.7-dt-bindings-qcom-scm-document-IPQ5018-compatible.patch

@@ -1,25 +0,0 @@
-From f6aa7386bc40b552eea8ec1b1d2168afe3b31110 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Wed, 16 Aug 2023 18:45:40 +0200
-Subject: [PATCH] dt-bindings: firmware: qcom,scm: document IPQ5018 compatible
-
-It seems that IPQ5018 compatible was never documented in the bindings.
-
-Signed-off-by: Robert Marko <[email protected]>
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
-+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
-@@ -24,6 +24,7 @@ properties:
-           - qcom,scm-apq8064
-           - qcom,scm-apq8084
-           - qcom,scm-ipq4019
-+          - qcom,scm-ipq5018
-           - qcom,scm-ipq5332
-           - qcom,scm-ipq6018
-           - qcom,scm-ipq806x

target/linux/qualcommax/patches-6.6/0022-v6.7-arm64-dts-qcom-IPQ5018-indicate-that-SDI-shoud-be-disabled.patch

@@ -1,26 +0,0 @@
-From 79796e87215db9587d6c66ec6f6781e091bc6464 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Wed, 16 Aug 2023 18:45:41 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq5018: indicate that SDI should be
- disabled
-
-Now that SCM has support for indicating that SDI has been enabled by
-default, lets set the property so SCM disables it during probing.
-
-Signed-off-by: Robert Marko <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -57,6 +57,7 @@
- 	firmware {
- 		scm {
- 			compatible = "qcom,scm-ipq5018", "qcom,scm";
-+			qcom,sdi-enabled;
- 		};
- 	};
- 

target/linux/qualcommax/patches-6.6/0023-v6.7-dt-bindings-phy-qcom-m31-Add-IPQ5018-compatible.patch

@@ -1,28 +0,0 @@
-From 1852dfaacd3f4358bbfca134b63a02bbb30c1136 Mon Sep 17 00:00:00 2001
-From: Nitheesh Sekar <[email protected]>
-Date: Mon, 4 Sep 2023 12:06:32 +0530
-Subject: [PATCH] dt-bindings: phy: qcom,m31: Add IPQ5018 compatible
-
-IPQ5332 qcom,m31 phy driver can support IPQ5018.
-
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
-Signed-off-by: Nitheesh Sekar <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Vinod Koul <[email protected]>
----
- .../devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml       | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
-+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml
-@@ -17,7 +17,9 @@ description:
- properties:
-   compatible:
-     items:
--      - const: qcom,ipq5332-usb-hsphy
-+      - enum:
-+          - qcom,ipq5018-usb-hsphy
-+          - qcom,ipq5332-usb-hsphy
- 
-   "#phy-cells":
-     const: 0

target/linux/qualcommax/patches-6.6/0024-v6.7-phy-qcom-m31-Add-compatible-phy-init-sequence-for-IPQ5018.patch

@@ -1,89 +0,0 @@
-From 68320e35f8cb1987b4ad34347fc7033832da99e3 Mon Sep 17 00:00:00 2001
-From: Nitheesh Sekar <[email protected]>
-Date: Mon, 4 Sep 2023 12:06:33 +0530
-Subject: [PATCH] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018
-
-Add phy init sequence and compatible string for IPQ5018
-chipset.
-
-Signed-off-by: Nitheesh Sekar <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Vinod Koul <[email protected]>
----
- drivers/phy/qualcomm/phy-qcom-m31.c | 51 +++++++++++++++++++++++++++++
- 1 file changed, 51 insertions(+)
-
---- a/drivers/phy/qualcomm/phy-qcom-m31.c
-+++ b/drivers/phy/qualcomm/phy-qcom-m31.c
-@@ -82,6 +82,50 @@ struct m31_priv_data {
- 	unsigned int			nregs;
- };
- 
-+static const struct m31_phy_regs m31_ipq5018_regs[] = {
-+	{
-+		.off = USB_PHY_CFG0,
-+		.val = UTMI_PHY_OVERRIDE_EN
-+	},
-+	{
-+		.off = USB_PHY_UTMI_CTRL5,
-+		.val = POR_EN,
-+		.delay = 15
-+	},
-+	{
-+		.off = USB_PHY_FSEL_SEL,
-+		.val = FREQ_SEL
-+	},
-+	{
-+		.off = USB_PHY_HS_PHY_CTRL_COMMON0,
-+		.val = COMMONONN | FSEL | RETENABLEN
-+	},
-+	{
-+		.off = USB_PHY_REFCLK_CTRL,
-+		.val = CLKCORE
-+	},
-+	{
-+		.off = USB_PHY_UTMI_CTRL5,
-+		.val = POR_EN
-+	},
-+	{
-+		.off = USB_PHY_HS_PHY_CTRL2,
-+		.val = USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN
-+	},
-+	{
-+		.off = USB_PHY_UTMI_CTRL5,
-+		.val = 0x0
-+	},
-+	{
-+		.off = USB_PHY_HS_PHY_CTRL2,
-+		.val = USB2_SUSPEND_N | USB2_UTMI_CLK_EN
-+	},
-+	{
-+		.off = USB_PHY_CFG0,
-+		.val = 0x0
-+	},
-+};
-+
- static struct m31_phy_regs m31_ipq5332_regs[] = {
- 	{
- 		USB_PHY_CFG0,
-@@ -267,6 +311,12 @@ static int m31usb_phy_probe(struct platf
- 	return PTR_ERR_OR_ZERO(phy_provider);
- }
- 
-+static const struct m31_priv_data m31_ipq5018_data = {
-+	.ulpi_mode = false,
-+	.regs = m31_ipq5018_regs,
-+	.nregs = ARRAY_SIZE(m31_ipq5018_regs),
-+};
-+
- static const struct m31_priv_data m31_ipq5332_data = {
- 	.ulpi_mode = false,
- 	.regs = m31_ipq5332_regs,
-@@ -274,6 +324,7 @@ static const struct m31_priv_data m31_ip
- };
- 
- static const struct of_device_id m31usb_phy_id_table[] = {
-+	{ .compatible = "qcom,ipq5018-usb-hsphy", .data = &m31_ipq5018_data },
- 	{ .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data },
- 	{ },
- };

target/linux/qualcommax/patches-6.6/0025-v6.7-dt-bindings-usb-dwc3-Add-IPQ5018-compatible.patch

@@ -1,41 +0,0 @@
-From 3865a64284cc4845c61cf3dc6c7246349d80cc49 Mon Sep 17 00:00:00 2001
-From: Nitheesh Sekar <[email protected]>
-Date: Thu, 31 Aug 2023 08:35:03 +0530
-Subject: [PATCH] dt-bindings: usb: dwc3: Add IPQ5018 compatible
-
-Document the IPQ5018 dwc3 compatible.
-
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
-Signed-off-by: Nitheesh Sekar <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Greg Kroah-Hartman <[email protected]>
----
- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
-+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
-@@ -14,6 +14,7 @@ properties:
-     items:
-       - enum:
-           - qcom,ipq4019-dwc3
-+          - qcom,ipq5018-dwc3
-           - qcom,ipq5332-dwc3
-           - qcom,ipq6018-dwc3
-           - qcom,ipq8064-dwc3
-@@ -238,6 +239,7 @@ allOf:
-         compatible:
-           contains:
-             enum:
-+              - qcom,ipq5018-dwc3
-               - qcom,ipq5332-dwc3
-               - qcom,msm8994-dwc3
-               - qcom,qcs404-dwc3
-@@ -411,6 +413,7 @@ allOf:
-         compatible:
-           contains:
-             enum:
-+              - qcom,ipq5018-dwc3
-               - qcom,ipq5332-dwc3
-               - qcom,sdm660-dwc3
-     then:

target/linux/qualcommax/patches-6.6/0026-v6.8-arm64-dts-qcom-ipq5018-Add-USB-related-nodes.patch

@@ -1,86 +0,0 @@
-From e7166f2774aafefd29ff26ffbbb7f6d40ac8ea1c Mon Sep 17 00:00:00 2001
-From: Nitheesh Sekar <[email protected]>
-Date: Mon, 4 Sep 2023 12:06:34 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add USB related nodes
-
-Add USB phy and controller nodes.
-
-Co-developed-by: Amandeep Singh <[email protected]>
-Signed-off-by: Amandeep Singh <[email protected]>
-Signed-off-by: Nitheesh Sekar <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -94,6 +94,19 @@
- 		#size-cells = <1>;
- 		ranges = <0 0 0 0xffffffff>;
- 
-+		usbphy0: phy@5b000 {
-+			compatible = "qcom,ipq5018-usb-hsphy";
-+			reg = <0x0005b000 0x120>;
-+
-+			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
-+
-+			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
-+
-+			#phy-cells = <0>;
-+
-+			status = "disabled";
-+		};
-+
- 		tlmm: pinctrl@1000000 {
- 			compatible = "qcom,ipq5018-tlmm";
- 			reg = <0x01000000 0x300000>;
-@@ -156,6 +169,47 @@
- 			status = "disabled";
- 		};
- 
-+		usb: usb@8af8800 {
-+			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
-+			reg = <0x08af8800 0x400>;
-+
-+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "hs_phy_irq";
-+
-+			clocks = <&gcc GCC_USB0_MASTER_CLK>,
-+				 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-+				 <&gcc GCC_USB0_SLEEP_CLK>,
-+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-+			clock-names = "core",
-+				      "iface",
-+				      "sleep",
-+				      "mock_utmi";
-+
-+			resets = <&gcc GCC_USB0_BCR>;
-+
-+			qcom,select-utmi-as-pipe-clk;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+			ranges;
-+
-+			status = "disabled";
-+
-+			usb_dwc: usb@8a00000 {
-+				compatible = "snps,dwc3";
-+				reg = <0x08a00000 0xe000>;
-+				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-+				clock-names = "ref";
-+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-+				phy-names = "usb2-phy";
-+				phys = <&usbphy0>;
-+				tx-fifo-resize;
-+				snps,is-utmi-l1-suspend;
-+				snps,hird-threshold = /bits/ 8 <0x0>;
-+				snps,dis_u2_susphy_quirk;
-+				snps,dis_u3_susphy_quirk;
-+			};
-+		};
-+
- 		intc: interrupt-controller@b000000 {
- 			compatible = "qcom,msm-qgic2";
- 			reg = <0x0b000000 0x1000>,  /* GICD */

target/linux/qualcommax/patches-6.6/0027-v6.8-arm64-dts-qcom-ipq5018-add-QUP1-SPI-controller.patch

@@ -1,56 +0,0 @@
-From a1f42e08f0f04b72a6597f080db4bfbb3737910c Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Wed, 4 Oct 2023 21:12:30 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq5018: add QUP1 SPI controller
-
-Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018.
-
-Signed-off-by: Robert Marko <[email protected]>
-Reviewed-by: Kathiravan Thirumoorthy <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-[bjorn: Padded address to 8 digits, fixed node sort order]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -159,6 +159,16 @@
- 			status = "disabled";
- 		};
- 
-+		blsp_dma: dma-controller@7884000 {
-+			compatible = "qcom,bam-v1.7.0";
-+			reg = <0x07884000 0x1d000>;
-+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "bam_clk";
-+			#dma-cells = <1>;
-+			qcom,ee = <0>;
-+		};
-+
- 		blsp1_uart1: serial@78af000 {
- 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- 			reg = <0x078af000 0x200>;
-@@ -169,6 +179,20 @@
- 			status = "disabled";
- 		};
- 
-+		blsp1_spi1: spi@78b5000 {
-+			compatible = "qcom,spi-qup-v2.2.1";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x078b5000 0x600>;
-+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
-+			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
-+			dma-names = "tx", "rx";
-+			status = "disabled";
-+		};
-+
- 		usb: usb@8af8800 {
- 			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
- 			reg = <0x08af8800 0x400>;

target/linux/qualcommax/patches-6.6/0028-v6.8-dt-bindings-clock-qcom-a53pll-add-IPQ5018-compatible.patch

@@ -1,25 +0,0 @@
-From 4d45d56e17348c6b6bb2bce126a4a5ea97b19900 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Mon, 25 Sep 2023 15:58:24 +0530
-Subject: [PATCH] dt-bindings: clock: qcom,a53pll: add IPQ5018 compatible
-
-Add IPQ5018 compatible to A53 PLL bindings.
-
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- Documentation/devicetree/bindings/clock/qcom,a53pll.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
-+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
-@@ -16,6 +16,7 @@ description:
- properties:
-   compatible:
-     enum:
-+      - qcom,ipq5018-a53pll
-       - qcom,ipq5332-a53pll
-       - qcom,ipq6018-a53pll
-       - qcom,ipq8074-a53pll

target/linux/qualcommax/patches-6.6/0029-v6.8-clk-qcom-apss-ipq-pll-add-support-for-IPQ5018.patch

@@ -1,62 +0,0 @@
-From 50492f929486c044b43cb3e2c0e040aa9b61ea2b Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Mon, 25 Sep 2023 15:58:25 +0530
-Subject: [PATCH] clk: qcom: apss-ipq-pll: add support for IPQ5018
-
-IPQ5018 APSS PLL is of type Stromer. Reuse Stromer Plus PLL offsets,
-add configuration values and the compatible.
-
-Co-developed-by: Sricharan Ramabadhran <[email protected]>
-Signed-off-by: Sricharan Ramabadhran <[email protected]>
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- drivers/clk/qcom/apss-ipq-pll.c | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
---- a/drivers/clk/qcom/apss-ipq-pll.c
-+++ b/drivers/clk/qcom/apss-ipq-pll.c
-@@ -73,6 +73,20 @@ static struct clk_alpha_pll ipq_pll_stro
- 	},
- };
- 
-+static const struct alpha_pll_config ipq5018_pll_config = {
-+	.l = 0x32,
-+	.config_ctl_val = 0x4001075b,
-+	.config_ctl_hi_val = 0x304,
-+	.main_output_mask = BIT(0),
-+	.aux_output_mask = BIT(1),
-+	.early_output_mask = BIT(3),
-+	.alpha_en_mask = BIT(24),
-+	.status_val = 0x3,
-+	.status_mask = GENMASK(10, 8),
-+	.lock_det = BIT(2),
-+	.test_ctl_hi_val = 0x00400003,
-+};
-+
- static const struct alpha_pll_config ipq5332_pll_config = {
- 	.l = 0x2d,
- 	.config_ctl_val = 0x4001075b,
-@@ -129,6 +143,12 @@ struct apss_pll_data {
- 	const struct alpha_pll_config *pll_config;
- };
- 
-+static const struct apss_pll_data ipq5018_pll_data = {
-+	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
-+	.pll = &ipq_pll_stromer_plus,
-+	.pll_config = &ipq5018_pll_config,
-+};
-+
- static struct apss_pll_data ipq5332_pll_data = {
- 	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
- 	.pll = &ipq_pll_stromer_plus,
-@@ -195,6 +215,7 @@ static int apss_ipq_pll_probe(struct pla
- }
- 
- static const struct of_device_id apss_ipq_pll_match_table[] = {
-+	{ .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data },
- 	{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
- 	{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
- 	{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },

target/linux/qualcommax/patches-6.6/0030-v6.8-arm64-dts-qcom-ipq5018-enable-the-CPUFreq-support.patch

@@ -1,98 +0,0 @@
-From 3e4b53e04281ed3d9c7a4329c027097265c04d54 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Mon, 25 Sep 2023 15:58:26 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq5018: enable the CPUFreq support
-
-Add the APCS, A53 PLL, cpu-opp-table nodes to set
-the CPU frequency at 800MHz (idle) or 1.008GHz.
-
-Co-developed-by: Sricharan Ramabadhran <[email protected]>
-Signed-off-by: Sricharan Ramabadhran <[email protected]>
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
- 1 file changed, 40 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -5,6 +5,7 @@
-  * Copyright (c) 2023 The Linux Foundation. All rights reserved.
-  */
- 
-+#include <dt-bindings/clock/qcom,apss-ipq.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
- #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
-@@ -36,6 +37,8 @@
- 			reg = <0x0>;
- 			enable-method = "psci";
- 			next-level-cache = <&L2_0>;
-+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
- 		CPU1: cpu@1 {
-@@ -44,6 +47,8 @@
- 			reg = <0x1>;
- 			enable-method = "psci";
- 			next-level-cache = <&L2_0>;
-+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
- 		L2_0: l2-cache {
-@@ -54,6 +59,25 @@
- 		};
- 	};
- 
-+	cpu_opp_table: opp-table-cpu {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		/*
-+		opp-800000000 {
-+			opp-hz = /bits/ 64 <800000000>;
-+			opp-microvolt = <1100000>;
-+			clock-latency-ns = <200000>;
-+		};
-+		*/
-+
-+		opp-1008000000 {
-+			opp-hz = /bits/ 64 <1008000000>;
-+			opp-microvolt = <1100000>;
-+			clock-latency-ns = <200000>;
-+		};
-+	};
-+
- 	firmware {
- 		scm {
- 			compatible = "qcom,scm-ipq5018", "qcom,scm";
-@@ -267,6 +291,24 @@
- 			clocks = <&sleep_clk>;
- 		};
- 
-+		apcs_glb: mailbox@b111000 {
-+			compatible = "qcom,ipq5018-apcs-apps-global",
-+				     "qcom,ipq6018-apcs-apps-global";
-+			reg = <0x0b111000 0x1000>;
-+			#clock-cells = <1>;
-+			clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
-+			clock-names = "pll", "xo", "gpll0";
-+			#mbox-cells = <1>;
-+		};
-+
-+		a53pll: clock@b116000 {
-+			compatible = "qcom,ipq5018-a53pll";
-+			reg = <0x0b116000 0x40>;
-+			#clock-cells = <0>;
-+			clocks = <&xo_board_clk>;
-+			clock-names = "xo";
-+		};
-+
- 		timer@b120000 {
- 			compatible = "arm,armv7-timer-mem";
- 			reg = <0x0b120000 0x1000>;

target/linux/qualcommax/patches-6.6/0031-v6.8-arm64-dts-qcom-ipq5018-add-few-more-reserved-memory-regions.patch

@@ -1,66 +0,0 @@
-From a427dd16e61f3d145bc24f0ed09692fc25931250 Mon Sep 17 00:00:00 2001
-From: Kathiravan Thirumoorthy <[email protected]>
-Date: Wed, 25 Oct 2023 22:12:12 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq5018: add few more reserved memory
- regions
-
-Like all other IPQ SoCs, bootloader will collect the system RAM contents
-upon crash for the post morterm analysis. If we don't reserve the memory
-region used by bootloader, obviously linux will consume it and upon next
-boot on crash, bootloader will be loaded in the same region, which will
-lead to loose some of the data, sometimes we may miss out critical
-information. So lets reserve the region used by the bootloader.
-
-Similarly SBL copies some data into the reserved region and it will be
-used in the crash scenario. So reserve 1MB for SBL as well.
-
-While at it, enable the SMEM support along with TCSR mutex.
-
-Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -106,6 +106,24 @@
- 		#size-cells = <2>;
- 		ranges;
- 
-+		bootloader@4a800000 {
-+			reg = <0x0 0x4a800000 0x0 0x200000>;
-+			no-map;
-+		};
-+
-+		sbl@4aa00000 {
-+			reg = <0x0 0x4aa00000 0x0 0x100000>;
-+			no-map;
-+		};
-+
-+		smem@4ab00000 {
-+			compatible = "qcom,smem";
-+			reg = <0x0 0x4ab00000 0x0 0x100000>;
-+			no-map;
-+
-+			hwlocks = <&tcsr_mutex 3>;
-+		};
-+
- 		tz_region: tz@4ac00000 {
- 			reg = <0x0 0x4ac00000 0x0 0x200000>;
- 			no-map;
-@@ -166,6 +184,12 @@
- 			#power-domain-cells = <1>;
- 		};
- 
-+		tcsr_mutex: hwlock@1905000 {
-+			compatible = "qcom,tcsr-mutex";
-+			reg = <0x01905000 0x20000>;
-+			#hwlock-cells = <1>;
-+		};
-+
- 		sdhc_1: mmc@7804000 {
- 			compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
- 			reg = <0x7804000 0x1000>;

target/linux/qualcommax/patches-6.6/0032-v6.10-clk-qcom-apss-ipq-pll-use-stromer-ops-for-IPQ5018-to-fix-boot-failure.patch

@@ -1,83 +0,0 @@
-From: Gabor Juhos <[email protected]>
-Subject: [PATCH] clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure
-Date: Fri, 15 Mar 2024 17:16:41 +0100
-
-Booting v6.8 results in a hang on various IPQ5018 based boards.
-Investigating the problem showed that the hang happens when the
-clk_alpha_pll_stromer_plus_set_rate() function tries to write
-into the PLL_MODE register of the APSS PLL.
-
-Checking the downstream code revealed that it uses [1] stromer
-specific operations for IPQ5018, whereas in the current code
-the stromer plus specific operations are used.
-
-The ops in the 'ipq_pll_stromer_plus' clock definition can't be
-changed since that is needed for IPQ5332, so add a new alpha pll
-clock declaration which uses the correct stromer ops and use this
-new clock for IPQ5018 to avoid the boot failure.
-
-Also, change pll_type in 'ipq5018_pll_data' to
-CLK_ALPHA_PLL_TYPE_STROMER to better reflect that it is a Stromer
-PLL and change the apss_ipq_pll_probe() function accordingly.
-
-1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c#L67
-
-Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018")
-Signed-off-by: Gabor Juhos <[email protected]>
----
- drivers/clk/qcom/apss-ipq-pll.c | 30 +++++++++++++++++++++++++++---
- 1 file changed, 27 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/apss-ipq-pll.c
-+++ b/drivers/clk/qcom/apss-ipq-pll.c
-@@ -55,6 +55,29 @@ static struct clk_alpha_pll ipq_pll_huay
- 	},
- };
- 
-+static struct clk_alpha_pll ipq_pll_stromer = {
-+	.offset = 0x0,
-+	/*
-+	 * Reuse CLK_ALPHA_PLL_TYPE_STROMER_PLUS register offsets.
-+	 * Although this is a bit confusing, but the offset values
-+	 * are correct nevertheless.
-+	 */
-+	.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
-+	.flags = SUPPORTS_DYNAMIC_UPDATE,
-+	.clkr = {
-+		.enable_reg = 0x0,
-+		.enable_mask = BIT(0),
-+		.hw.init = &(const struct clk_init_data) {
-+			.name = "a53pll",
-+			.parent_data = &(const struct clk_parent_data) {
-+				.fw_name = "xo",
-+			},
-+			.num_parents = 1,
-+			.ops = &clk_alpha_pll_stromer_ops,
-+		},
-+	},
-+};
-+
- static struct clk_alpha_pll ipq_pll_stromer_plus = {
- 	.offset = 0x0,
- 	.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
-@@ -144,8 +167,8 @@ struct apss_pll_data {
- };
- 
- static const struct apss_pll_data ipq5018_pll_data = {
--	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
--	.pll = &ipq_pll_stromer_plus,
-+	.pll_type = CLK_ALPHA_PLL_TYPE_STROMER,
-+	.pll = &ipq_pll_stromer,
- 	.pll_config = &ipq5018_pll_config,
- };
- 
-@@ -203,7 +226,8 @@ static int apss_ipq_pll_probe(struct pla
- 
- 	if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
- 		clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
--	else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
-+	else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER ||
-+		 data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
- 		clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
- 
- 	ret = devm_clk_register_regmap(dev, &data->pll->clkr);

target/linux/qualcommax/patches-6.6/0033-v6.10-clk-qcom-apss-ipq-pll-fix-PLL-rate-for-IPQ5018.patch

@@ -1,32 +0,0 @@
-From: Gabor Juhos <[email protected]>
-Subject: [PATCH] clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
-Date: Tue, 26 Mar 2024 14:34:11 +0100
-
-According to ipq5018.dtsi, the maximum supported rate by the
-CPU is 1.008 GHz on the IPQ5018 platform, however the current
-configuration of the PLL results in 1.2 GHz rate.
-
-Change the 'L' value in the PLL configuration to limit the
-rate to 1.008 GHz. The downstream kernel also uses the same
-value [1]. Also add a comment to indicate the desired
-frequency.
-
-[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c?ref_type=heads#L151
-
-Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018")
-Signed-off-by: Gabor Juhos <[email protected]>
----
- drivers/clk/qcom/apss-ipq-pll.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/apss-ipq-pll.c
-+++ b/drivers/clk/qcom/apss-ipq-pll.c
-@@ -97,7 +97,7 @@ static struct clk_alpha_pll ipq_pll_stro
- };
- 
- static const struct alpha_pll_config ipq5018_pll_config = {
--	.l = 0x32,
-+	.l = 0x2a,
- 	.config_ctl_val = 0x4001075b,
- 	.config_ctl_hi_val = 0x304,
- 	.main_output_mask = BIT(0),

target/linux/qualcommax/patches-6.6/0034-v6.11-clk-qcom-gcc-ipq6018-update-sdcc-max-clock-frequency.patch

@@ -1,26 +0,0 @@
-From f2743ae3ff84579981ac513f512b9df945d109c0 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <[email protected]>
-Date: Thu, 20 Jun 2024 23:01:21 +0800
-Subject: [PATCH] clk: qcom: gcc-ipq6018: update sdcc max clock frequency
-
-The mmc controller of the IPQ6018 does not support HS400 mode.
-So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).
-
-Signed-off-by: Chukun Pan <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- drivers/clk/qcom/gcc-ipq6018.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/gcc-ipq6018.c
-+++ b/drivers/clk/qcom/gcc-ipq6018.c
-@@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_a
- 	F(96000000, P_GPLL2, 12, 0, 0),
- 	F(177777778, P_GPLL0, 4.5, 0, 0),
- 	F(192000000, P_GPLL2, 6, 0, 0),
--	F(384000000, P_GPLL2, 3, 0, 0),
-+	F(200000000, P_GPLL0, 4, 0, 0),
- 	{ }
- };
- 

target/linux/qualcommax/patches-6.6/0035-v6.11-arm64-dts-qcom-ipq6018-add-sdhci-node.patch

@@ -1,47 +0,0 @@
-From 5db216f6e1f85394e79dca74ceceb83b2f8566b5 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <[email protected]>
-Date: Thu, 20 Jun 2024 23:01:22 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add sdhci node
-
-Add node to support mmc controller inside of IPQ6018.
-This controller supports both eMMC and SD cards.
-
-Tested with:
-  eMMC (HS200)
-  SD Card (SDR50/SDR104)
-
-Signed-off-by: Chukun Pan <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -470,6 +470,25 @@
- 			};
- 		};
- 
-+		sdhc: mmc@7804000 {
-+			compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
-+			reg = <0x0 0x07804000 0x0 0x1000>,
-+			      <0x0 0x07805000 0x0 0x1000>;
-+			reg-names = "hc", "cqhci";
-+
-+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "hc_irq", "pwr_irq";
-+
-+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
-+				 <&gcc GCC_SDCC1_APPS_CLK>,
-+				 <&xo>;
-+			clock-names = "iface", "core", "xo";
-+			resets = <&gcc GCC_SDCC1_BCR>;
-+			max-frequency = <192000000>;
-+			status = "disabled";
-+		};
-+
- 		blsp_dma: dma-controller@7884000 {
- 			compatible = "qcom,bam-v1.7.0";
- 			reg = <0x0 0x07884000 0x0 0x2b000>;

target/linux/qualcommax/patches-6.6/0036-v6.13-arm64-dts-qcom-ipq-change-labels-to-lower-case.patch

@@ -1,381 +0,0 @@
-From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <[email protected]>
-Date: Tue, 22 Oct 2024 17:47:26 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case
-
-DTS coding style expects labels to be lowercase.  No functional impact.
-Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
-
-Signed-off-by: Krzysztof Kozlowski <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++---
- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++-----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++-------
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++-----
- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++--------------
- 5 files changed, 61 insertions(+), 61 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -31,27 +31,27 @@
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 
--		CPU0: cpu@0 {
-+		cpu0: cpu@0 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			reg = <0x0>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
--		CPU1: cpu@1 {
-+		cpu1: cpu@1 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			reg = <0x1>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
--		L2_0: l2-cache {
-+		l2_0: l2-cache {
- 			compatible = "cache";
- 			cache-level = <2>;
- 			cache-size = <0x80000>;
---- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
-@@ -30,47 +30,47 @@
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 
--		CPU0: cpu@0 {
-+		cpu0: cpu@0 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			reg = <0x0>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
--		CPU1: cpu@1 {
-+		cpu1: cpu@1 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			reg = <0x1>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
--		CPU2: cpu@2 {
-+		cpu2: cpu@2 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			reg = <0x2>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
--		CPU3: cpu@3 {
-+		cpu3: cpu@3 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			reg = <0x3>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
--		L2_0: l2-cache {
-+		l2_0: l2-cache {
- 			compatible = "cache";
- 			cache-level = <2>;
- 			cache-unified;
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -34,12 +34,12 @@
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 
--		CPU0: cpu@0 {
-+		cpu0: cpu@0 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			reg = <0x0>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
-@@ -47,12 +47,12 @@
- 			#cooling-cells = <2>;
- 		};
- 
--		CPU1: cpu@1 {
-+		cpu1: cpu@1 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			enable-method = "psci";
- 			reg = <0x1>;
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
-@@ -60,12 +60,12 @@
- 			#cooling-cells = <2>;
- 		};
- 
--		CPU2: cpu@2 {
-+		cpu2: cpu@2 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			enable-method = "psci";
- 			reg = <0x2>;
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
-@@ -73,12 +73,12 @@
- 			#cooling-cells = <2>;
- 		};
- 
--		CPU3: cpu@3 {
-+		cpu3: cpu@3 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			enable-method = "psci";
- 			reg = <0x3>;
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
-@@ -86,7 +86,7 @@
- 			#cooling-cells = <2>;
- 		};
- 
--		L2_0: l2-cache {
-+		l2_0: l2-cache {
- 			compatible = "cache";
- 			cache-level = <2>;
- 			cache-unified;
-@@ -993,10 +993,10 @@
- 			cooling-maps {
- 				map0 {
- 					trip = <&cpu_alert>;
--					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- 				};
- 			};
- 		};
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -32,39 +32,39 @@
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 
--		CPU0: cpu@0 {
-+		cpu0: cpu@0 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			reg = <0x0>;
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			enable-method = "psci";
- 		};
- 
--		CPU1: cpu@1 {
-+		cpu1: cpu@1 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			enable-method = "psci";
- 			reg = <0x1>;
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 		};
- 
--		CPU2: cpu@2 {
-+		cpu2: cpu@2 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			enable-method = "psci";
- 			reg = <0x2>;
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 		};
- 
--		CPU3: cpu@3 {
-+		cpu3: cpu@3 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a53";
- 			enable-method = "psci";
- 			reg = <0x3>;
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 		};
- 
--		L2_0: l2-cache {
-+		l2_0: l2-cache {
- 			compatible = "cache";
- 			cache-level = <2>;
- 			cache-unified;
---- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
-@@ -33,12 +33,12 @@
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 
--		CPU0: cpu@0 {
-+		cpu0: cpu@0 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a73";
- 			reg = <0x0>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
-@@ -46,12 +46,12 @@
- 			#cooling-cells = <2>;
- 		};
- 
--		CPU1: cpu@1 {
-+		cpu1: cpu@1 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a73";
- 			reg = <0x1>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
-@@ -59,12 +59,12 @@
- 			#cooling-cells = <2>;
- 		};
- 
--		CPU2: cpu@2 {
-+		cpu2: cpu@2 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a73";
- 			reg = <0x2>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
-@@ -72,12 +72,12 @@
- 			#cooling-cells = <2>;
- 		};
- 
--		CPU3: cpu@3 {
-+		cpu3: cpu@3 {
- 			device_type = "cpu";
- 			compatible = "arm,cortex-a73";
- 			reg = <0x3>;
- 			enable-method = "psci";
--			next-level-cache = <&L2_0>;
-+			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
-@@ -85,7 +85,7 @@
- 			#cooling-cells = <2>;
- 		};
- 
--		L2_0: l2-cache {
-+		l2_0: l2-cache {
- 			compatible = "cache";
- 			cache-level = <2>;
- 			cache-unified;
-@@ -845,10 +845,10 @@
- 			cooling-maps {
- 				map0 {
- 					trip = <&cpu0_alert>;
--					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- 				};
- 			};
- 		};
-@@ -875,10 +875,10 @@
- 			cooling-maps {
- 				map0 {
- 					trip = <&cpu1_alert>;
--					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- 				};
- 			};
- 		};
-@@ -905,10 +905,10 @@
- 			cooling-maps {
- 				map0 {
- 					trip = <&cpu2_alert>;
--					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- 				};
- 			};
- 		};
-@@ -935,10 +935,10 @@
- 			cooling-maps {
- 				map0 {
- 					trip = <&cpu3_alert>;
--					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
--							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- 				};
- 			};
- 		};

target/linux/qualcommax/patches-6.6/0037-v6.16-arm64-dts-qcom-ipq6018-add-1.2GHz-CPU-Frequency.patch

@@ -1,33 +0,0 @@
-From 144230e5840c09984ad743c3df9de5fb443159a9 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <[email protected]>
-Date: Mon, 10 Feb 2025 15:01:18 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency
-
-The final version of IPQ6000 (SoC id: IPQ6000, SBL version:
-BOOT.XF.0.3-00086-IPQ60xxLZB-1) has a max design frequency
-of 1.2GHz, so add this CPU frequency.
-
-Signed-off-by: Chukun Pan <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -119,6 +119,13 @@
- 			clock-latency-ns = <200000>;
- 		};
- 
-+		opp-1200000000 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt = <850000>;
-+			opp-supported-hw = <0x4>;
-+			clock-latency-ns = <200000>;
-+		};
-+
- 		opp-1320000000 {
- 			opp-hz = /bits/ 64 <1320000000>;
- 			opp-microvolt = <862500>;

target/linux/qualcommax/patches-6.6/0038-v6.16-arm64-dts-qcom-ipq6018-add-1.5GHz-CPU-Frequency.patch

@@ -1,33 +0,0 @@
-From a96e765a7b3f64429f7eec3471a2093355ab041e Mon Sep 17 00:00:00 2001
-From: Chukun Pan <[email protected]>
-Date: Mon, 10 Feb 2025 15:01:19 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency
-
-The early version of IPQ6000 (SoC id: IPQ6018, SBL version:
-BOOT.XF.0.3-00077-IPQ60xxLZB-2) and IPQ6005 SoCs can reach
-a max frequency of 1.5GHz, so add this CPU frequency.
-
-Signed-off-by: Chukun Pan <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -140,6 +140,13 @@
- 			clock-latency-ns = <200000>;
- 		};
- 
-+		opp-1512000000 {
-+			opp-hz = /bits/ 64 <1512000000>;
-+			opp-microvolt = <937500>;
-+			opp-supported-hw = <0x2>;
-+			clock-latency-ns = <200000>;
-+		};
-+
- 		opp-1608000000 {
- 			opp-hz = /bits/ 64 <1608000000>;
- 			opp-microvolt = <987500>;

target/linux/qualcommax/patches-6.6/0039-v6.16-arm64-dts-qcom-ipq6018-move-mp5496-regulator-out-of-.patch

@@ -1,120 +0,0 @@
-From 0c4c0f14b7d704bcb728d018a74788771dc9286b Mon Sep 17 00:00:00 2001
-From: Chukun Pan <[email protected]>
-Date: Mon, 10 Feb 2025 15:01:20 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq6018: move mp5496 regulator out of soc dtsi
-
-Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496
-pmic was never part of the IPQ60xx SoC, it's optional, so we moved
-it out of the soc dtsi.
-
-Signed-off-by: Chukun Pan <[email protected]>
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts |  2 +-
- arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 35 ++++++++++++++++++++++++++++
- arch/arm64/boot/dts/qcom/ipq6018.dtsi        | 14 -----------
- 3 files changed, 36 insertions(+), 15 deletions(-)
- create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
-
---- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
-@@ -7,7 +7,7 @@
- 
- /dts-v1/;
- 
--#include "ipq6018.dtsi"
-+#include "ipq6018-mp5496.dtsi"
- 
- / {
- 	model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
---- /dev/null
-+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
-@@ -0,0 +1,35 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+/*
-+ * ipq6018-mp5496.dtsi describes common properties (e.g. regulators) that
-+ * apply to most devices that make use of the IPQ6018 SoC and MP5496 PMIC.
-+ */
-+
-+#include "ipq6018.dtsi"
-+
-+&cpu0 {
-+	cpu-supply = <&ipq6018_s2>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&ipq6018_s2>;
-+};
-+
-+&cpu2 {
-+	cpu-supply = <&ipq6018_s2>;
-+};
-+
-+&cpu3 {
-+	cpu-supply = <&ipq6018_s2>;
-+};
-+
-+&rpm_requests {
-+	regulators {
-+		compatible = "qcom,rpm-mp5496-regulators";
-+
-+		ipq6018_s2: s2 {
-+			regulator-min-microvolt = <725000>;
-+			regulator-max-microvolt = <1062500>;
-+			regulator-always-on;
-+		};
-+	};
-+};
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -43,7 +43,6 @@
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
--			cpu-supply = <&ipq6018_s2>;
- 			#cooling-cells = <2>;
- 		};
- 
-@@ -56,7 +55,6 @@
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
--			cpu-supply = <&ipq6018_s2>;
- 			#cooling-cells = <2>;
- 		};
- 
-@@ -69,7 +67,6 @@
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
--			cpu-supply = <&ipq6018_s2>;
- 			#cooling-cells = <2>;
- 		};
- 
-@@ -82,7 +79,6 @@
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			operating-points-v2 = <&cpu_opp_table>;
--			cpu-supply = <&ipq6018_s2>;
- 			#cooling-cells = <2>;
- 		};
- 
-@@ -184,16 +180,6 @@
- 			rpm_requests: rpm-requests {
- 				compatible = "qcom,rpm-ipq6018";
- 				qcom,glink-channels = "rpm_requests";
--
--				regulators {
--					compatible = "qcom,rpm-mp5496-regulators";
--
--					ipq6018_s2: s2 {
--						regulator-min-microvolt = <725000>;
--						regulator-max-microvolt = <1062500>;
--						regulator-always-on;
--					};
--				};
- 			};
- 		};
- 	};

target/linux/qualcommax/patches-6.6/0040-v6.16-arm64-dts-qcom-ipq6018-rename-labels-of-mp5496-regul.patch

@@ -1,50 +0,0 @@
-From e60f872c2dc4c1d9227977c8714373fe6328699c Mon Sep 17 00:00:00 2001
-From: Chukun Pan <[email protected]>
-Date: Mon, 10 Feb 2025 15:01:21 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq6018: rename labels of mp5496 regulator
-
-Change the labels of mp5496 regulator from ipq6018 to mp5496.
-
-Suggested-by: Konrad Dybcio <[email protected]>
-Suggested-by: Dmitry Baryshkov <[email protected]>
-Signed-off-by: Chukun Pan <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
-@@ -7,26 +7,26 @@
- #include "ipq6018.dtsi"
- 
- &cpu0 {
--	cpu-supply = <&ipq6018_s2>;
-+	cpu-supply = <&mp5496_s2>;
- };
- 
- &cpu1 {
--	cpu-supply = <&ipq6018_s2>;
-+	cpu-supply = <&mp5496_s2>;
- };
- 
- &cpu2 {
--	cpu-supply = <&ipq6018_s2>;
-+	cpu-supply = <&mp5496_s2>;
- };
- 
- &cpu3 {
--	cpu-supply = <&ipq6018_s2>;
-+	cpu-supply = <&mp5496_s2>;
- };
- 
- &rpm_requests {
- 	regulators {
- 		compatible = "qcom,rpm-mp5496-regulators";
- 
--		ipq6018_s2: s2 {
-+		mp5496_s2: s2 {
- 			regulator-min-microvolt = <725000>;
- 			regulator-max-microvolt = <1062500>;
- 			regulator-always-on;

target/linux/qualcommax/patches-6.6/0041-v6.16-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch

@@ -1,33 +0,0 @@
-From a566fb9ba8ffecb56c50729390a9ea076f5c9532 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <[email protected]>
-Date: Mon, 10 Feb 2025 15:01:22 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator
-
-Add LDOA2 regulator from MP5496 to support SDCC voltage scaling.
-
-Suggested-by: Robert Marko <[email protected]>
-Signed-off-by: Chukun Pan <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
-@@ -31,5 +31,14 @@
- 			regulator-max-microvolt = <1062500>;
- 			regulator-always-on;
- 		};
-+
-+		mp5496_l2: l2 {
-+			regulator-min-microvolt = <1800000>;
-+			regulator-max-microvolt = <3300000>;
-+		};
- 	};
- };
-+
-+&sdhc {
-+	vqmmc-supply = <&mp5496_l2>;
-+};

target/linux/qualcommax/patches-6.6/0042-v6.10-clk-qcom-clk-rcg-introduce-support-for-multiple-conf.patch

@@ -1,83 +0,0 @@
-From d06b1043644a1831ab141bbee2669002bba15b0f Mon Sep 17 00:00:00 2001
-From: Christian Marangi <[email protected]>
-Date: Wed, 20 Dec 2023 23:17:22 +0100
-Subject: [PATCH] clk: qcom: clk-rcg: introduce support for multiple conf for
- same freq
-
-Some RCG frequency can be reached by multiple configuration.
-
-We currently declare multiple configuration for the same frequency but
-that is not supported and always the first configuration will be taken.
-
-These multiple configuration are needed as based on the current parent
-configuration, it may be needed to use a different configuration to
-reach the same frequency.
-
-To handle this introduce 3 new macro, C, FM and FMS:
-
-- C is used to declare a freq_conf where src, pre_div, m and n are
-  provided.
-
-- FM is used to declare a freq_multi_tbl with the frequency and an
-  array of confs to insert all the config for the provided frequency.
-
-- FMS is used to declare a freq_multi_tbl with the frequency and an
-  array of a single conf with the provided src, pre_div, m and n.
-
-Struct clk_rcg2 is changed to add a union type to reference a simple
-freq_tbl or a complex freq_multi_tbl.
-
-Signed-off-by: Christian Marangi <[email protected]>
-Acked-by: Stephen Boyd <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- drivers/clk/qcom/clk-rcg.h | 23 ++++++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/clk-rcg.h
-+++ b/drivers/clk/qcom/clk-rcg.h
-@@ -17,6 +17,23 @@ struct freq_tbl {
- 	u16 n;
- };
- 
-+#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) }
-+#define FM(f, confs) { (f), ARRAY_SIZE(confs), (confs) }
-+#define FMS(f, s, h, m, n) { (f), 1, (const struct freq_conf []){ C(s, h, m, n) } }
-+
-+struct freq_conf {
-+	u8 src;
-+	u8 pre_div;
-+	u16 m;
-+	u16 n;
-+};
-+
-+struct freq_multi_tbl {
-+	unsigned long freq;
-+	size_t num_confs;
-+	const struct freq_conf *confs;
-+};
-+
- /**
-  * struct mn - M/N:D counter
-  * @mnctr_en_bit: bit to enable mn counter
-@@ -138,6 +155,7 @@ extern const struct clk_ops clk_dyn_rcg_
-  * @safe_src_index: safe src index value
-  * @parent_map: map from software's parent index to hardware's src_sel field
-  * @freq_tbl: frequency table
-+ * @freq_multi_tbl: frequency table for clocks reachable with multiple RCGs conf
-  * @clkr: regmap clock handle
-  * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
-  * @parked_cfg: cached value of the CFG register for parked RCGs
-@@ -149,7 +167,10 @@ struct clk_rcg2 {
- 	u8			hid_width;
- 	u8			safe_src_index;
- 	const struct parent_map	*parent_map;
--	const struct freq_tbl	*freq_tbl;
-+	union {
-+		const struct freq_tbl		*freq_tbl;
-+		const struct freq_multi_tbl	*freq_multi_tbl;
-+	};
- 	struct clk_regmap	clkr;
- 	u8			cfg_off;
- 	u32			parked_cfg;

target/linux/qualcommax/patches-6.6/0043-v6.10-clk-qcom-clk-rcg2-add-support-for-rcg2-freq-multi-op.patch

@@ -1,296 +0,0 @@
-From 89da22456af0762477d8c1345fdd17961b3ada80 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <[email protected]>
-Date: Wed, 20 Dec 2023 23:17:23 +0100
-Subject: [PATCH] clk: qcom: clk-rcg2: add support for rcg2 freq multi ops
-
-Some RCG frequency can be reached by multiple configuration.
-
-Add clk_rcg2_fm_ops ops to support these special RCG configurations.
-
-These alternative ops will select the frequency using a CEIL policy.
-
-When the correct frequency is found, the correct config is selected by
-calculating the final rate (by checking the defined parent and values
-in the config that is being checked) and deciding based on the one that
-is less different than the requested one.
-
-These check are skipped if there is just one config for the requested
-freq.
-
-qcom_find_freq_multi is added to search the freq with the new struct
-freq_multi_tbl.
-__clk_rcg2_select_conf is used to select the correct conf by simulating
-the final clock.
-If a conf can't be found due to parent not reachable, a WARN is printed
-and -EINVAL is returned.
-
-Tested-by: Wei Lei <[email protected]>
-Signed-off-by: Christian Marangi <[email protected]>
-Acked-by: Stephen Boyd <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- drivers/clk/qcom/clk-rcg.h  |   1 +
- drivers/clk/qcom/clk-rcg2.c | 166 ++++++++++++++++++++++++++++++++++++
- drivers/clk/qcom/common.c   |  18 ++++
- drivers/clk/qcom/common.h   |   2 +
- 4 files changed, 187 insertions(+)
-
---- a/drivers/clk/qcom/clk-rcg.h
-+++ b/drivers/clk/qcom/clk-rcg.h
-@@ -190,6 +190,7 @@ struct clk_rcg2_gfx3d {
- 
- extern const struct clk_ops clk_rcg2_ops;
- extern const struct clk_ops clk_rcg2_floor_ops;
-+extern const struct clk_ops clk_rcg2_fm_ops;
- extern const struct clk_ops clk_rcg2_mux_closest_ops;
- extern const struct clk_ops clk_edp_pixel_ops;
- extern const struct clk_ops clk_byte_ops;
---- a/drivers/clk/qcom/clk-rcg2.c
-+++ b/drivers/clk/qcom/clk-rcg2.c
-@@ -260,6 +260,115 @@ static int _freq_tbl_determine_rate(stru
- 	return 0;
- }
- 
-+static const struct freq_conf *
-+__clk_rcg2_select_conf(struct clk_hw *hw, const struct freq_multi_tbl *f,
-+		       unsigned long req_rate)
-+{
-+	unsigned long rate_diff, best_rate_diff = ULONG_MAX;
-+	const struct freq_conf *conf, *best_conf = NULL;
-+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-+	const char *name = clk_hw_get_name(hw);
-+	unsigned long parent_rate, rate;
-+	struct clk_hw *p;
-+	int index, i;
-+
-+	/* Exit early if only one config is defined */
-+	if (f->num_confs == 1) {
-+		best_conf = f->confs;
-+		goto exit;
-+	}
-+
-+	/* Search in each provided config the one that is near the wanted rate */
-+	for (i = 0, conf = f->confs; i < f->num_confs; i++, conf++) {
-+		index = qcom_find_src_index(hw, rcg->parent_map, conf->src);
-+		if (index < 0)
-+			continue;
-+
-+		p = clk_hw_get_parent_by_index(hw, index);
-+		if (!p)
-+			continue;
-+
-+		parent_rate =  clk_hw_get_rate(p);
-+		rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
-+
-+		if (rate == req_rate) {
-+			best_conf = conf;
-+			goto exit;
-+		}
-+
-+		rate_diff = abs_diff(req_rate, rate);
-+		if (rate_diff < best_rate_diff) {
-+			best_rate_diff = rate_diff;
-+			best_conf = conf;
-+		}
-+	}
-+
-+	/*
-+	 * Very unlikely. Warn if we couldn't find a correct config
-+	 * due to parent not found in every config.
-+	 */
-+	if (unlikely(!best_conf)) {
-+		WARN(1, "%s: can't find a configuration for rate %lu\n",
-+		     name, req_rate);
-+		return ERR_PTR(-EINVAL);
-+	}
-+
-+exit:
-+	return best_conf;
-+}
-+
-+static int _freq_tbl_fm_determine_rate(struct clk_hw *hw, const struct freq_multi_tbl *f,
-+				       struct clk_rate_request *req)
-+{
-+	unsigned long clk_flags, rate = req->rate;
-+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-+	const struct freq_conf *conf;
-+	struct clk_hw *p;
-+	int index;
-+
-+	f = qcom_find_freq_multi(f, rate);
-+	if (!f || !f->confs)
-+		return -EINVAL;
-+
-+	conf = __clk_rcg2_select_conf(hw, f, rate);
-+	if (IS_ERR(conf))
-+		return PTR_ERR(conf);
-+	index = qcom_find_src_index(hw, rcg->parent_map, conf->src);
-+	if (index < 0)
-+		return index;
-+
-+	clk_flags = clk_hw_get_flags(hw);
-+	p = clk_hw_get_parent_by_index(hw, index);
-+	if (!p)
-+		return -EINVAL;
-+
-+	if (clk_flags & CLK_SET_RATE_PARENT) {
-+		rate = f->freq;
-+		if (conf->pre_div) {
-+			if (!rate)
-+				rate = req->rate;
-+			rate /= 2;
-+			rate *= conf->pre_div + 1;
-+		}
-+
-+		if (conf->n) {
-+			u64 tmp = rate;
-+
-+			tmp = tmp * conf->n;
-+			do_div(tmp, conf->m);
-+			rate = tmp;
-+		}
-+	} else {
-+		rate =  clk_hw_get_rate(p);
-+	}
-+
-+	req->best_parent_hw = p;
-+	req->best_parent_rate = rate;
-+	req->rate = f->freq;
-+
-+	return 0;
-+}
-+
- static int clk_rcg2_determine_rate(struct clk_hw *hw,
- 				   struct clk_rate_request *req)
- {
-@@ -276,6 +385,14 @@ static int clk_rcg2_determine_floor_rate
- 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
- }
- 
-+static int clk_rcg2_fm_determine_rate(struct clk_hw *hw,
-+				      struct clk_rate_request *req)
-+{
-+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-+
-+	return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req);
-+}
-+
- static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
- 				u32 *_cfg)
- {
-@@ -371,6 +488,30 @@ static int __clk_rcg2_set_rate(struct cl
- 	return clk_rcg2_configure(rcg, f);
- }
- 
-+static int __clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate)
-+{
-+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-+	const struct freq_multi_tbl *f;
-+	const struct freq_conf *conf;
-+	struct freq_tbl f_tbl = {};
-+
-+	f = qcom_find_freq_multi(rcg->freq_multi_tbl, rate);
-+	if (!f || !f->confs)
-+		return -EINVAL;
-+
-+	conf = __clk_rcg2_select_conf(hw, f, rate);
-+	if (IS_ERR(conf))
-+		return PTR_ERR(conf);
-+
-+	f_tbl.freq = f->freq;
-+	f_tbl.src = conf->src;
-+	f_tbl.pre_div = conf->pre_div;
-+	f_tbl.m = conf->m;
-+	f_tbl.n = conf->n;
-+
-+	return clk_rcg2_configure(rcg, &f_tbl);
-+}
-+
- static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
- 			    unsigned long parent_rate)
- {
-@@ -383,6 +524,12 @@ static int clk_rcg2_set_floor_rate(struc
- 	return __clk_rcg2_set_rate(hw, rate, FLOOR);
- }
- 
-+static int clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate,
-+				unsigned long parent_rate)
-+{
-+	return __clk_rcg2_fm_set_rate(hw, rate);
-+}
-+
- static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
- 		unsigned long rate, unsigned long parent_rate, u8 index)
- {
-@@ -395,6 +542,12 @@ static int clk_rcg2_set_floor_rate_and_p
- 	return __clk_rcg2_set_rate(hw, rate, FLOOR);
- }
- 
-+static int clk_rcg2_fm_set_rate_and_parent(struct clk_hw *hw,
-+		unsigned long rate, unsigned long parent_rate, u8 index)
-+{
-+	return __clk_rcg2_fm_set_rate(hw, rate);
-+}
-+
- static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
- {
- 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-@@ -505,6 +658,19 @@ const struct clk_ops clk_rcg2_floor_ops
- };
- EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
- 
-+const struct clk_ops clk_rcg2_fm_ops = {
-+	.is_enabled = clk_rcg2_is_enabled,
-+	.get_parent = clk_rcg2_get_parent,
-+	.set_parent = clk_rcg2_set_parent,
-+	.recalc_rate = clk_rcg2_recalc_rate,
-+	.determine_rate = clk_rcg2_fm_determine_rate,
-+	.set_rate = clk_rcg2_fm_set_rate,
-+	.set_rate_and_parent = clk_rcg2_fm_set_rate_and_parent,
-+	.get_duty_cycle = clk_rcg2_get_duty_cycle,
-+	.set_duty_cycle = clk_rcg2_set_duty_cycle,
-+};
-+EXPORT_SYMBOL_GPL(clk_rcg2_fm_ops);
-+
- const struct clk_ops clk_rcg2_mux_closest_ops = {
- 	.determine_rate = __clk_mux_determine_rate_closest,
- 	.get_parent = clk_rcg2_get_parent,
---- a/drivers/clk/qcom/common.c
-+++ b/drivers/clk/qcom/common.c
-@@ -41,6 +41,24 @@ struct freq_tbl *qcom_find_freq(const st
- }
- EXPORT_SYMBOL_GPL(qcom_find_freq);
- 
-+const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f,
-+						  unsigned long rate)
-+{
-+	if (!f)
-+		return NULL;
-+
-+	if (!f->freq)
-+		return f;
-+
-+	for (; f->freq; f++)
-+		if (rate <= f->freq)
-+			return f;
-+
-+	/* Default to our fastest rate */
-+	return f - 1;
-+}
-+EXPORT_SYMBOL_GPL(qcom_find_freq_multi);
-+
- const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
- 					    unsigned long rate)
- {
---- a/drivers/clk/qcom/common.h
-+++ b/drivers/clk/qcom/common.h
-@@ -45,6 +45,8 @@ extern const struct freq_tbl *qcom_find_
- 					     unsigned long rate);
- extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
- 						   unsigned long rate);
-+extern const struct freq_multi_tbl *qcom_find_freq_multi(const struct freq_multi_tbl *f,
-+							 unsigned long rate);
- extern void
- qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count);
- extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,

target/linux/qualcommax/patches-6.6/0044-v6.10-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch

@@ -1,227 +0,0 @@
-From e88f03230dc07aa3293b6aeb078bd27370bb2594 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <[email protected]>
-Date: Wed, 20 Dec 2023 23:17:24 +0100
-Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
- conf
-
-Rework nss_port5/6 to use the new multiple configuration implementation
-and correctly fix the clocks for these port under some corner case.
-
-This is particularly relevant for device that have 2.5G or 10G port
-connected to port5 or port 6 on ipq8074. As the parent are shared
-across multiple port it may be required to select the correct
-configuration to accomplish the desired clock. Without this patch such
-port doesn't work in some specific ethernet speed as the clock will be
-set to the wrong frequency as we just select the first configuration for
-the related frequency instead of selecting the best one.
-
-Signed-off-by: Christian Marangi <[email protected]>
-Acked-by: Stephen Boyd <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- drivers/clk/qcom/gcc-ipq8074.c | 120 +++++++++++++++++++++------------
- 1 file changed, 76 insertions(+), 44 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -1677,15 +1677,23 @@ static struct clk_regmap_div nss_port4_t
- 	},
- };
- 
--static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
--	F(19200000, P_XO, 1, 0, 0),
--	F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
--	F(25000000, P_UNIPHY0_RX, 5, 0, 0),
--	F(78125000, P_UNIPHY1_RX, 4, 0, 0),
--	F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
--	F(125000000, P_UNIPHY0_RX, 1, 0, 0),
--	F(156250000, P_UNIPHY1_RX, 2, 0, 0),
--	F(312500000, P_UNIPHY1_RX, 1, 0, 0),
-+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
-+	C(P_UNIPHY1_RX, 12.5, 0, 0),
-+	C(P_UNIPHY0_RX, 5, 0, 0),
-+};
-+
-+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
-+	C(P_UNIPHY1_RX, 2.5, 0, 0),
-+	C(P_UNIPHY0_RX, 1, 0, 0),
-+};
-+
-+static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
-+	FMS(19200000, P_XO, 1, 0, 0),
-+	FM(25000000, ftbl_nss_port5_rx_clk_src_25),
-+	FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
-+	FM(125000000, ftbl_nss_port5_rx_clk_src_125),
-+	FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
-+	FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
- 	{ }
- };
- 
-@@ -1712,14 +1720,14 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32
- 
- static struct clk_rcg2 nss_port5_rx_clk_src = {
- 	.cmd_rcgr = 0x68060,
--	.freq_tbl = ftbl_nss_port5_rx_clk_src,
-+	.freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
- 	.hid_width = 5,
- 	.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
- 	.clkr.hw.init = &(struct clk_init_data){
- 		.name = "nss_port5_rx_clk_src",
- 		.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
- 		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
--		.ops = &clk_rcg2_ops,
-+		.ops = &clk_rcg2_fm_ops,
- 	},
- };
- 
-@@ -1739,15 +1747,23 @@ static struct clk_regmap_div nss_port5_r
- 	},
- };
- 
--static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
--	F(19200000, P_XO, 1, 0, 0),
--	F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
--	F(25000000, P_UNIPHY0_TX, 5, 0, 0),
--	F(78125000, P_UNIPHY1_TX, 4, 0, 0),
--	F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
--	F(125000000, P_UNIPHY0_TX, 1, 0, 0),
--	F(156250000, P_UNIPHY1_TX, 2, 0, 0),
--	F(312500000, P_UNIPHY1_TX, 1, 0, 0),
-+static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
-+	C(P_UNIPHY1_TX, 12.5, 0, 0),
-+	C(P_UNIPHY0_TX, 5, 0, 0),
-+};
-+
-+static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
-+	C(P_UNIPHY1_TX, 2.5, 0, 0),
-+	C(P_UNIPHY0_TX, 1, 0, 0),
-+};
-+
-+static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
-+	FMS(19200000, P_XO, 1, 0, 0),
-+	FM(25000000, ftbl_nss_port5_tx_clk_src_25),
-+	FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
-+	FM(125000000, ftbl_nss_port5_tx_clk_src_125),
-+	FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
-+	FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
- 	{ }
- };
- 
-@@ -1774,14 +1790,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32
- 
- static struct clk_rcg2 nss_port5_tx_clk_src = {
- 	.cmd_rcgr = 0x68068,
--	.freq_tbl = ftbl_nss_port5_tx_clk_src,
-+	.freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
- 	.hid_width = 5,
- 	.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
- 	.clkr.hw.init = &(struct clk_init_data){
- 		.name = "nss_port5_tx_clk_src",
- 		.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
- 		.num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
--		.ops = &clk_rcg2_ops,
-+		.ops = &clk_rcg2_fm_ops,
- 	},
- };
- 
-@@ -1801,15 +1817,23 @@ static struct clk_regmap_div nss_port5_t
- 	},
- };
- 
--static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
--	F(19200000, P_XO, 1, 0, 0),
--	F(25000000, P_UNIPHY2_RX, 5, 0, 0),
--	F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
--	F(78125000, P_UNIPHY2_RX, 4, 0, 0),
--	F(125000000, P_UNIPHY2_RX, 1, 0, 0),
--	F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
--	F(156250000, P_UNIPHY2_RX, 2, 0, 0),
--	F(312500000, P_UNIPHY2_RX, 1, 0, 0),
-+static const struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
-+	C(P_UNIPHY2_RX, 5, 0, 0),
-+	C(P_UNIPHY2_RX, 12.5, 0, 0),
-+};
-+
-+static const struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
-+	C(P_UNIPHY2_RX, 1, 0, 0),
-+	C(P_UNIPHY2_RX, 2.5, 0, 0),
-+};
-+
-+static const struct freq_multi_tbl ftbl_nss_port6_rx_clk_src[] = {
-+	FMS(19200000, P_XO, 1, 0, 0),
-+	FM(25000000, ftbl_nss_port6_rx_clk_src_25),
-+	FMS(78125000, P_UNIPHY2_RX, 4, 0, 0),
-+	FM(125000000, ftbl_nss_port6_rx_clk_src_125),
-+	FMS(156250000, P_UNIPHY2_RX, 2, 0, 0),
-+	FMS(312500000, P_UNIPHY2_RX, 1, 0, 0),
- 	{ }
- };
- 
-@@ -1831,14 +1855,14 @@ static const struct parent_map gcc_xo_un
- 
- static struct clk_rcg2 nss_port6_rx_clk_src = {
- 	.cmd_rcgr = 0x68070,
--	.freq_tbl = ftbl_nss_port6_rx_clk_src,
-+	.freq_multi_tbl = ftbl_nss_port6_rx_clk_src,
- 	.hid_width = 5,
- 	.parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
- 	.clkr.hw.init = &(struct clk_init_data){
- 		.name = "nss_port6_rx_clk_src",
- 		.parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
- 		.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
--		.ops = &clk_rcg2_ops,
-+		.ops = &clk_rcg2_fm_ops,
- 	},
- };
- 
-@@ -1858,15 +1882,23 @@ static struct clk_regmap_div nss_port6_r
- 	},
- };
- 
--static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
--	F(19200000, P_XO, 1, 0, 0),
--	F(25000000, P_UNIPHY2_TX, 5, 0, 0),
--	F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
--	F(78125000, P_UNIPHY2_TX, 4, 0, 0),
--	F(125000000, P_UNIPHY2_TX, 1, 0, 0),
--	F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
--	F(156250000, P_UNIPHY2_TX, 2, 0, 0),
--	F(312500000, P_UNIPHY2_TX, 1, 0, 0),
-+static const struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
-+	C(P_UNIPHY2_TX, 5, 0, 0),
-+	C(P_UNIPHY2_TX, 12.5, 0, 0),
-+};
-+
-+static const struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
-+	C(P_UNIPHY2_TX, 1, 0, 0),
-+	C(P_UNIPHY2_TX, 2.5, 0, 0),
-+};
-+
-+static const struct freq_multi_tbl ftbl_nss_port6_tx_clk_src[] = {
-+	FMS(19200000, P_XO, 1, 0, 0),
-+	FM(25000000, ftbl_nss_port6_tx_clk_src_25),
-+	FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
-+	FM(125000000, ftbl_nss_port6_tx_clk_src_125),
-+	FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
-+	FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
- 	{ }
- };
- 
-@@ -1888,14 +1920,14 @@ static const struct parent_map gcc_xo_un
- 
- static struct clk_rcg2 nss_port6_tx_clk_src = {
- 	.cmd_rcgr = 0x68078,
--	.freq_tbl = ftbl_nss_port6_tx_clk_src,
-+	.freq_multi_tbl = ftbl_nss_port6_tx_clk_src,
- 	.hid_width = 5,
- 	.parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
- 	.clkr.hw.init = &(struct clk_init_data){
- 		.name = "nss_port6_tx_clk_src",
- 		.parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
- 		.num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
--		.ops = &clk_rcg2_ops,
-+		.ops = &clk_rcg2_fm_ops,
- 	},
- };
- 

target/linux/qualcommax/patches-6.6/0045-v6.7-arm64-dts-qcom-ipq8074-switch-PCIe-QMP-PHY-to-new-st.patch

@@ -1,122 +0,0 @@
-From 9e5e778f3340a687dd91c533064f963d352921c6 Mon Sep 17 00:00:00 2001
-From: Dmitry Baryshkov <[email protected]>
-Date: Sun, 20 Aug 2023 17:20:26 +0300
-Subject: [PATCH] arm64: dts: qcom: ipq8074: switch PCIe QMP PHY to new style
- of bindings
-
-Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
-resource region, no per-PHY subnodes).
-
-Signed-off-by: Dmitry Baryshkov <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 67 +++++++++++----------------
- 1 file changed, 28 insertions(+), 39 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -211,59 +211,48 @@
- 
- 		pcie_qmp0: phy@84000 {
- 			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
--			reg = <0x00084000 0x1bc>;
--			#address-cells = <1>;
--			#size-cells = <1>;
--			ranges;
-+			reg = <0x00084000 0x1000>;
- 
- 			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
--				<&gcc GCC_PCIE0_AHB_CLK>;
--			clock-names = "aux", "cfg_ahb";
-+				 <&gcc GCC_PCIE0_AHB_CLK>,
-+				 <&gcc GCC_PCIE0_PIPE_CLK>;
-+			clock-names = "aux",
-+				      "cfg_ahb",
-+				      "pipe";
-+
-+			clock-output-names = "pcie20_phy0_pipe_clk";
-+			#clock-cells = <0>;
-+
-+			#phy-cells = <0>;
-+
- 			resets = <&gcc GCC_PCIE0_PHY_BCR>,
--				<&gcc GCC_PCIE0PHY_PHY_BCR>;
-+				 <&gcc GCC_PCIE0PHY_PHY_BCR>;
- 			reset-names = "phy",
- 				      "common";
- 			status = "disabled";
--
--			pcie_phy0: phy@84200 {
--				reg = <0x84200 0x16c>,
--				      <0x84400 0x200>,
--				      <0x84800 0x1f0>,
--				      <0x84c00 0xf4>;
--				#phy-cells = <0>;
--				#clock-cells = <0>;
--				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
--				clock-names = "pipe0";
--				clock-output-names = "pcie20_phy0_pipe_clk";
--			};
- 		};
- 
- 		pcie_qmp1: phy@8e000 {
- 			compatible = "qcom,ipq8074-qmp-pcie-phy";
--			reg = <0x0008e000 0x1c4>;
--			#address-cells = <1>;
--			#size-cells = <1>;
--			ranges;
-+			reg = <0x0008e000 0x1000>;
- 
- 			clocks = <&gcc GCC_PCIE1_AUX_CLK>,
--				<&gcc GCC_PCIE1_AHB_CLK>;
--			clock-names = "aux", "cfg_ahb";
-+				 <&gcc GCC_PCIE1_AHB_CLK>,
-+				 <&gcc GCC_PCIE1_PIPE_CLK>;
-+			clock-names = "aux",
-+				      "cfg_ahb",
-+				      "pipe";
-+
-+			clock-output-names = "pcie20_phy1_pipe_clk";
-+			#clock-cells = <0>;
-+
-+			#phy-cells = <0>;
-+
- 			resets = <&gcc GCC_PCIE1_PHY_BCR>,
--				<&gcc GCC_PCIE1PHY_PHY_BCR>;
-+				 <&gcc GCC_PCIE1PHY_PHY_BCR>;
- 			reset-names = "phy",
- 				      "common";
- 			status = "disabled";
--
--			pcie_phy1: phy@8e200 {
--				reg = <0x8e200 0x130>,
--				      <0x8e400 0x200>,
--				      <0x8e800 0x1f8>;
--				#phy-cells = <0>;
--				#clock-cells = <0>;
--				clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
--				clock-names = "pipe0";
--				clock-output-names = "pcie20_phy1_pipe_clk";
--			};
- 		};
- 
- 		mdio: mdio@90000 {
-@@ -839,7 +828,7 @@
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 
--			phys = <&pcie_phy1>;
-+			phys = <&pcie_qmp1>;
- 			phy-names = "pciephy";
- 
- 			ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
-@@ -901,7 +890,7 @@
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 
--			phys = <&pcie_phy0>;
-+			phys = <&pcie_qmp0>;
- 			phy-names = "pciephy";
- 
- 			ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */

target/linux/qualcommax/patches-6.6/0046-v6.8-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch

@@ -1,39 +0,0 @@
-From 591da388c344f934601548cb44f54eab012c6c94 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Fri, 13 Oct 2023 18:39:34 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to
- GCC
-
-Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to
-find them by matching globaly by name.
-
-If not passed directly, driver maintains backwards compatibility by then
-falling back to global lookup.
-
-Signed-off-by: Robert Marko <[email protected]>
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Link: https://lore.kernel.org/r/[email protected]
-Signed-off-by: Bjorn Andersson <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -371,8 +371,14 @@
- 		gcc: gcc@1800000 {
- 			compatible = "qcom,gcc-ipq8074";
- 			reg = <0x01800000 0x80000>;
--			clocks = <&xo>, <&sleep_clk>;
--			clock-names = "xo", "sleep_clk";
-+			clocks = <&xo>,
-+				 <&sleep_clk>,
-+				 <&pcie_qmp0>,
-+				 <&pcie_qmp1>;
-+			clock-names = "xo",
-+				      "sleep_clk",
-+				      "pcie0_pipe",
-+				      "pcie1_pipe";
- 			#clock-cells = <1>;
- 			#power-domain-cells = <1>;
- 			#reset-cells = <1>;

target/linux/qualcommax/patches-6.6/0047-v6.11-PCI-qcom-Use-devm_clk_bulk_get_all-API.patch

@@ -1,388 +0,0 @@
-From 652935ba05860eadaa19ac9efe7aea61fb7a3aef Mon Sep 17 00:00:00 2001
-From: Manivannan Sadhasivam <[email protected]>
-Date: Wed, 17 Apr 2024 12:32:53 +0530
-Subject: [PATCH] PCI: qcom: Use devm_clk_bulk_get_all() API
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There is no need for the device drivers to validate the clocks defined in
-Devicetree. The validation should be performed by the DT schema and the
-drivers should just get all the clocks from DT. Right now the driver
-hardcodes the clock info and validates them against DT which is redundant.
-
-So use devm_clk_bulk_get_all() that just gets all the clocks defined in DT
-and get rid of all static clocks info from the driver. This simplifies the
-driver.
-
-Link: https://lore.kernel.org/linux-pci/[email protected]
-Signed-off-by: Manivannan Sadhasivam <[email protected]>
-Signed-off-by: Krzysztof Wilczyński <[email protected]>
-Signed-off-by: Bjorn Helgaas <[email protected]>
----
- drivers/pci/controller/dwc/pcie-qcom.c | 177 ++++++++-----------------
- 1 file changed, 58 insertions(+), 119 deletions(-)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -151,58 +151,56 @@
- 
- #define QCOM_PCIE_CRC8_POLYNOMIAL		(BIT(2) | BIT(1) | BIT(0))
- 
--#define QCOM_PCIE_1_0_0_MAX_CLOCKS		4
- struct qcom_pcie_resources_1_0_0 {
--	struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS];
-+	struct clk_bulk_data *clks;
-+	int num_clks;
- 	struct reset_control *core;
- 	struct regulator *vdda;
- };
- 
--#define QCOM_PCIE_2_1_0_MAX_CLOCKS		5
- #define QCOM_PCIE_2_1_0_MAX_RESETS		6
- #define QCOM_PCIE_2_1_0_MAX_SUPPLY		3
- struct qcom_pcie_resources_2_1_0 {
--	struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
-+	struct clk_bulk_data *clks;
-+	int num_clks;
- 	struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS];
- 	int num_resets;
- 	struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
- };
- 
--#define QCOM_PCIE_2_3_2_MAX_CLOCKS		4
- #define QCOM_PCIE_2_3_2_MAX_SUPPLY		2
- struct qcom_pcie_resources_2_3_2 {
--	struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS];
-+	struct clk_bulk_data *clks;
-+	int num_clks;
- 	struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
- };
- 
--#define QCOM_PCIE_2_3_3_MAX_CLOCKS		5
- #define QCOM_PCIE_2_3_3_MAX_RESETS		7
- struct qcom_pcie_resources_2_3_3 {
--	struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS];
-+	struct clk_bulk_data *clks;
-+	int num_clks;
- 	struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS];
- };
- 
--#define QCOM_PCIE_2_4_0_MAX_CLOCKS		4
- #define QCOM_PCIE_2_4_0_MAX_RESETS		12
- struct qcom_pcie_resources_2_4_0 {
--	struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
-+	struct clk_bulk_data *clks;
- 	int num_clks;
- 	struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS];
- 	int num_resets;
- };
- 
--#define QCOM_PCIE_2_7_0_MAX_CLOCKS		15
- #define QCOM_PCIE_2_7_0_MAX_SUPPLIES		2
- struct qcom_pcie_resources_2_7_0 {
--	struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS];
-+	struct clk_bulk_data *clks;
- 	int num_clks;
- 	struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES];
- 	struct reset_control *rst;
- };
- 
--#define QCOM_PCIE_2_9_0_MAX_CLOCKS		5
- struct qcom_pcie_resources_2_9_0 {
--	struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS];
-+	struct clk_bulk_data *clks;
-+	int num_clks;
- 	struct reset_control *rst;
- };
- 
-@@ -313,21 +311,11 @@ static int qcom_pcie_get_resources_2_1_0
- 	if (ret)
- 		return ret;
- 
--	res->clks[0].id = "iface";
--	res->clks[1].id = "core";
--	res->clks[2].id = "phy";
--	res->clks[3].id = "aux";
--	res->clks[4].id = "ref";
--
--	/* iface, core, phy are required */
--	ret = devm_clk_bulk_get(dev, 3, res->clks);
--	if (ret < 0)
--		return ret;
--
--	/* aux, ref are optional */
--	ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
--	if (ret < 0)
--		return ret;
-+	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
-+	if (res->num_clks < 0) {
-+		dev_err(dev, "Failed to get clocks\n");
-+		return res->num_clks;
-+	}
- 
- 	res->resets[0].id = "pci";
- 	res->resets[1].id = "axi";
-@@ -349,7 +337,7 @@ static void qcom_pcie_deinit_2_1_0(struc
- {
- 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
- 
--	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
-+	clk_bulk_disable_unprepare(res->num_clks, res->clks);
- 	reset_control_bulk_assert(res->num_resets, res->resets);
- 
- 	writel(1, pcie->parf + PARF_PHY_CTRL);
-@@ -401,7 +389,7 @@ static int qcom_pcie_post_init_2_1_0(str
- 	val &= ~PHY_TEST_PWR_DOWN;
- 	writel(val, pcie->parf + PARF_PHY_CTRL);
- 
--	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
-+	ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
- 	if (ret)
- 		return ret;
- 
-@@ -452,20 +440,16 @@ static int qcom_pcie_get_resources_1_0_0
- 	struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
- 	struct dw_pcie *pci = pcie->pci;
- 	struct device *dev = pci->dev;
--	int ret;
- 
- 	res->vdda = devm_regulator_get(dev, "vdda");
- 	if (IS_ERR(res->vdda))
- 		return PTR_ERR(res->vdda);
- 
--	res->clks[0].id = "iface";
--	res->clks[1].id = "aux";
--	res->clks[2].id = "master_bus";
--	res->clks[3].id = "slave_bus";
--
--	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
--	if (ret < 0)
--		return ret;
-+	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
-+	if (res->num_clks < 0) {
-+		dev_err(dev, "Failed to get clocks\n");
-+		return res->num_clks;
-+	}
- 
- 	res->core = devm_reset_control_get_exclusive(dev, "core");
- 	return PTR_ERR_OR_ZERO(res->core);
-@@ -476,7 +460,7 @@ static void qcom_pcie_deinit_1_0_0(struc
- 	struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
- 
- 	reset_control_assert(res->core);
--	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
-+	clk_bulk_disable_unprepare(res->num_clks, res->clks);
- 	regulator_disable(res->vdda);
- }
- 
-@@ -493,7 +477,7 @@ static int qcom_pcie_init_1_0_0(struct q
- 		return ret;
- 	}
- 
--	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
-+	ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
- 	if (ret) {
- 		dev_err(dev, "cannot prepare/enable clocks\n");
- 		goto err_assert_reset;
-@@ -508,7 +492,7 @@ static int qcom_pcie_init_1_0_0(struct q
- 	return 0;
- 
- err_disable_clks:
--	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
-+	clk_bulk_disable_unprepare(res->num_clks, res->clks);
- err_assert_reset:
- 	reset_control_assert(res->core);
- 
-@@ -556,14 +540,11 @@ static int qcom_pcie_get_resources_2_3_2
- 	if (ret)
- 		return ret;
- 
--	res->clks[0].id = "aux";
--	res->clks[1].id = "cfg";
--	res->clks[2].id = "bus_master";
--	res->clks[3].id = "bus_slave";
--
--	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
--	if (ret < 0)
--		return ret;
-+	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
-+	if (res->num_clks < 0) {
-+		dev_err(dev, "Failed to get clocks\n");
-+		return res->num_clks;
-+	}
- 
- 	return 0;
- }
-@@ -572,7 +553,7 @@ static void qcom_pcie_deinit_2_3_2(struc
- {
- 	struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
- 
--	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
-+	clk_bulk_disable_unprepare(res->num_clks, res->clks);
- 	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
- }
- 
-@@ -589,7 +570,7 @@ static int qcom_pcie_init_2_3_2(struct q
- 		return ret;
- 	}
- 
--	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
-+	ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
- 	if (ret) {
- 		dev_err(dev, "cannot prepare/enable clocks\n");
- 		regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
-@@ -637,17 +618,11 @@ static int qcom_pcie_get_resources_2_4_0
- 	bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
- 	int ret;
- 
--	res->clks[0].id = "aux";
--	res->clks[1].id = "master_bus";
--	res->clks[2].id = "slave_bus";
--	res->clks[3].id = "iface";
--
--	/* qcom,pcie-ipq4019 is defined without "iface" */
--	res->num_clks = is_ipq ? 3 : 4;
--
--	ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
--	if (ret < 0)
--		return ret;
-+	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
-+	if (res->num_clks < 0) {
-+		dev_err(dev, "Failed to get clocks\n");
-+		return res->num_clks;
-+	}
- 
- 	res->resets[0].id = "axi_m";
- 	res->resets[1].id = "axi_s";
-@@ -718,15 +693,11 @@ static int qcom_pcie_get_resources_2_3_3
- 	struct device *dev = pci->dev;
- 	int ret;
- 
--	res->clks[0].id = "iface";
--	res->clks[1].id = "axi_m";
--	res->clks[2].id = "axi_s";
--	res->clks[3].id = "ahb";
--	res->clks[4].id = "aux";
--
--	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
--	if (ret < 0)
--		return ret;
-+	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
-+	if (res->num_clks < 0) {
-+		dev_err(dev, "Failed to get clocks\n");
-+		return res->num_clks;
-+	}
- 
- 	res->rst[0].id = "axi_m";
- 	res->rst[1].id = "axi_s";
-@@ -747,7 +718,7 @@ static void qcom_pcie_deinit_2_3_3(struc
- {
- 	struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
- 
--	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
-+	clk_bulk_disable_unprepare(res->num_clks, res->clks);
- }
- 
- static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
-@@ -777,7 +748,7 @@ static int qcom_pcie_init_2_3_3(struct q
- 	 */
- 	usleep_range(2000, 2500);
- 
--	ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
-+	ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
- 	if (ret) {
- 		dev_err(dev, "cannot prepare/enable clocks\n");
- 		goto err_assert_resets;
-@@ -838,8 +809,6 @@ static int qcom_pcie_get_resources_2_7_0
- 	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
- 	struct dw_pcie *pci = pcie->pci;
- 	struct device *dev = pci->dev;
--	unsigned int num_clks, num_opt_clks;
--	unsigned int idx;
- 	int ret;
- 
- 	res->rst = devm_reset_control_array_get_exclusive(dev);
-@@ -853,36 +822,11 @@ static int qcom_pcie_get_resources_2_7_0
- 	if (ret)
- 		return ret;
- 
--	idx = 0;
--	res->clks[idx++].id = "aux";
--	res->clks[idx++].id = "cfg";
--	res->clks[idx++].id = "bus_master";
--	res->clks[idx++].id = "bus_slave";
--	res->clks[idx++].id = "slave_q2a";
--
--	num_clks = idx;
--
--	ret = devm_clk_bulk_get(dev, num_clks, res->clks);
--	if (ret < 0)
--		return ret;
--
--	res->clks[idx++].id = "tbu";
--	res->clks[idx++].id = "ddrss_sf_tbu";
--	res->clks[idx++].id = "aggre0";
--	res->clks[idx++].id = "aggre1";
--	res->clks[idx++].id = "noc_aggr";
--	res->clks[idx++].id = "noc_aggr_4";
--	res->clks[idx++].id = "noc_aggr_south_sf";
--	res->clks[idx++].id = "cnoc_qx";
--	res->clks[idx++].id = "sleep";
--	res->clks[idx++].id = "cnoc_sf_axi";
--
--	num_opt_clks = idx - num_clks;
--	res->num_clks = idx;
--
--	ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks);
--	if (ret < 0)
--		return ret;
-+	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
-+	if (res->num_clks < 0) {
-+		dev_err(dev, "Failed to get clocks\n");
-+		return res->num_clks;
-+	}
- 
- 	return 0;
- }
-@@ -1073,17 +1017,12 @@ static int qcom_pcie_get_resources_2_9_0
- 	struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
- 	struct dw_pcie *pci = pcie->pci;
- 	struct device *dev = pci->dev;
--	int ret;
--
--	res->clks[0].id = "iface";
--	res->clks[1].id = "axi_m";
--	res->clks[2].id = "axi_s";
--	res->clks[3].id = "axi_bridge";
--	res->clks[4].id = "rchng";
- 
--	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
--	if (ret < 0)
--		return ret;
-+	res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
-+	if (res->num_clks < 0) {
-+		dev_err(dev, "Failed to get clocks\n");
-+		return res->num_clks;
-+	}
- 
- 	res->rst = devm_reset_control_array_get_exclusive(dev);
- 	if (IS_ERR(res->rst))
-@@ -1096,7 +1035,7 @@ static void qcom_pcie_deinit_2_9_0(struc
- {
- 	struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
- 
--	clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
-+	clk_bulk_disable_unprepare(res->num_clks, res->clks);
- }
- 
- static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
-@@ -1125,7 +1064,7 @@ static int qcom_pcie_init_2_9_0(struct q
- 
- 	usleep_range(2000, 2500);
- 
--	return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
-+	return clk_bulk_prepare_enable(res->num_clks, res->clks);
- }
- 
- static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)

target/linux/qualcommax/patches-6.6/0048-v6.16-PCI-qcom-Add-support-for-IPQ5018.patch

@@ -1,31 +0,0 @@
-From 3e5127469a8d41153fb30031a271788f52dd17ec Mon Sep 17 00:00:00 2001
-From: Nitheesh Sekar <[email protected]>
-Date: Wed, 26 Mar 2025 12:10:58 +0400
-Subject: [PATCH] PCI: qcom: Add support for IPQ5018
-
-Add IPQ5018 platform with is based on Qcom IP rev. 2.9.0 and Synopsys IP
-rev. 5.00a.
-
-The platform itself has two PCIe Gen2 controllers: one single-lane and
-one dual-lane. So add the IPQ5018 compatible and re-use 2_9_0 ops.
-
-Signed-off-by: Nitheesh Sekar <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
-Signed-off-by: Manivannan Sadhasivam <[email protected]>
-Reviewed-by: Manivannan Sadhasivam <[email protected]>
-Link: https://patch.msgid.link/[email protected]
----
- drivers/pci/controller/dwc/pcie-qcom.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -1580,6 +1580,7 @@ static const struct of_device_id qcom_pc
- 	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
- 	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
- 	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
-+	{ .compatible = "qcom,pcie-ipq5018", .data = &cfg_2_9_0 },
- 	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
- 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
- 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },

target/linux/qualcommax/patches-6.6/0102-arm64-dts-ipq8074-add-reserved-memory-nodes.patch

@@ -1,60 +0,0 @@
-From ad2d07f71739351eeea1d8a120c0918e2c4b265f Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Wed, 22 Dec 2021 12:23:34 +0100
-Subject: [PATCH] arm64: dts: ipq8074: add reserved memory nodes
-
-IPQ8074 has multiple reserved memory ranges, if they are not defined
-then weird things tend to happen, board hangs and resets when PCI or
-WLAN is used etc.
-
-So, to avoid all of that add the reserved memory nodes from the downstream
-5.4 kernel from QCA.
-This is their default layout meant for devices with 1GB of RAM, but
-devices with lower ammounts can override the Q6 node.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 35 +++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -86,6 +86,16 @@
- 		#size-cells = <2>;
- 		ranges;
- 
-+		nss@40000000 {
-+			no-map;
-+			reg = <0x0 0x40000000 0x0 0x01000000>;
-+		};
-+
-+		tzapp_region: tzapp@4a400000 {
-+			no-map;
-+			reg = <0x0 0x4a400000 0x0 0x00200000>;
-+		};
-+
- 		bootloader@4a600000 {
- 			reg = <0x0 0x4a600000 0x0 0x400000>;
- 			no-map;
-@@ -108,6 +118,21 @@
- 			reg = <0x0 0x4ac00000 0x0 0x400000>;
- 			no-map;
- 		};
-+
-+		q6_region: wcnss@4b000000 {
-+			no-map;
-+			reg = <0x0 0x4b000000 0x0 0x05f00000>;
-+		};
-+
-+		q6_etr_region: q6_etr_dump@50f00000 {
-+			no-map;
-+			reg = <0x0 0x50f00000 0x0 0x00100000>;
-+		};
-+
-+		m3_dump_region: m3_dump@51000000 {
-+			no-map;
-+			reg = <0x0 0x51000000 0x0 0x100000>;
-+		};
- 	};
- 
- 	firmware {

target/linux/qualcommax/patches-6.6/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch

@@ -1,43 +0,0 @@
-From fb1f6850be00d8dd8a54017be4c1336e224069ac Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Wed, 16 Nov 2022 22:26:25 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: use msi-parent for PCIe
-
-Instead of hardcoding the IRQ, simply use msi-parent instead.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -752,7 +752,7 @@
- 			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
- 			ranges = <0 0xb00a000 0xffd>;
- 
--			v2m@0 {
-+			gic_v2m0: v2m@0 {
- 				compatible = "arm,gic-v2m-frame";
- 				msi-controller;
- 				reg = <0x0 0xffd>;
-@@ -865,8 +865,7 @@
- 			ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
- 				 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
- 
--			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
--			interrupt-names = "msi";
-+			msi-parent = <&gic_v2m0>;
- 			#interrupt-cells = <1>;
- 			interrupt-map-mask = <0 0 0 0x7>;
- 			interrupt-map = <0 0 0 1 &intc 0 0 142
-@@ -927,8 +926,7 @@
- 			ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
- 				 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
- 
--			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
--			interrupt-names = "msi";
-+			msi-parent = <&gic_v2m0>;
- 			#interrupt-cells = <1>;
- 			interrupt-map-mask = <0 0 0 0x7>;
- 			interrupt-map = <0 0 0 1 &intc 0 0 75

target/linux/qualcommax/patches-6.6/0112-remoteproc-qcom-Add-PRNG-proxy-clock.patch

@@ -1,155 +0,0 @@
-From 125681433c8e526356947acf572fe8ca8ad32291 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Sat, 30 Jan 2021 10:50:05 +0530
-Subject: [PATCH] remoteproc: qcom: Add PRNG proxy clock
-
-PRNG clock is needed by the secure PIL, support for the same
-is added in subsequent patches.
-
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Signed-off-by: Nikhil Prakash V <[email protected]>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
- 1 file changed, 47 insertions(+), 18 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -91,19 +91,6 @@ enum {
- 	WCSS_QCS404,
- };
- 
--struct wcss_data {
--	const char *firmware_name;
--	unsigned int crash_reason_smem;
--	u32 version;
--	bool aon_reset_required;
--	bool wcss_q6_reset_required;
--	const char *ssr_name;
--	const char *sysmon_name;
--	int ssctl_id;
--	const struct rproc_ops *ops;
--	bool requires_force_stop;
--};
--
- struct q6v5_wcss {
- 	struct device *dev;
- 
-@@ -128,6 +115,7 @@ struct q6v5_wcss {
- 	struct clk *qdsp6ss_xo_cbcr;
- 	struct clk *qdsp6ss_core_gfmux;
- 	struct clk *lcc_bcr_sleep;
-+	struct clk *prng_clk;
- 	struct regulator *cx_supply;
- 	struct qcom_sysmon *sysmon;
- 
-@@ -151,6 +139,21 @@ struct q6v5_wcss {
- 	struct qcom_rproc_ssr ssr_subdev;
- };
- 
-+struct wcss_data {
-+	int (*init_clock)(struct q6v5_wcss *wcss);
-+	int (*init_regulator)(struct q6v5_wcss *wcss);
-+	const char *firmware_name;
-+	unsigned int crash_reason_smem;
-+	u32 version;
-+	bool aon_reset_required;
-+	bool wcss_q6_reset_required;
-+	const char *ssr_name;
-+	const char *sysmon_name;
-+	int ssctl_id;
-+	const struct rproc_ops *ops;
-+	bool requires_force_stop;
-+};
-+
- static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
- {
- 	int ret;
-@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc
- 	struct q6v5_wcss *wcss = rproc->priv;
- 	int ret;
- 
-+	ret = clk_prepare_enable(wcss->prng_clk);
-+	if (ret) {
-+		dev_err(wcss->dev, "prng clock enable failed\n");
-+		return ret;
-+	}
-+
- 	qcom_q6v5_prepare(&wcss->q6v5);
- 
- 	/* Release Q6 and WCSS reset */
-@@ -733,6 +742,7 @@ static int q6v5_wcss_stop(struct rproc *
- 			return ret;
- 	}
- 
-+	clk_disable_unprepare(wcss->prng_clk);
- 	qcom_q6v5_unprepare(&wcss->q6v5);
- 
- 	return 0;
-@@ -899,7 +909,21 @@ static int q6v5_alloc_memory_region(stru
- 	return 0;
- }
- 
--static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
-+static int ipq8074_init_clock(struct q6v5_wcss *wcss)
-+{
-+	int ret;
-+
-+	wcss->prng_clk = devm_clk_get(wcss->dev, "prng");
-+	if (IS_ERR(wcss->prng_clk)) {
-+		ret = PTR_ERR(wcss->prng_clk);
-+		if (ret != -EPROBE_DEFER)
-+			dev_err(wcss->dev, "Failed to get prng clock\n");
-+		return ret;
-+	}
-+	return 0;
-+}
-+
-+static int qcs404_init_clock(struct q6v5_wcss *wcss)
- {
- 	int ret;
- 
-@@ -989,7 +1013,7 @@ static int q6v5_wcss_init_clock(struct q
- 	return 0;
- }
- 
--static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
-+static int qcs404_init_regulator(struct q6v5_wcss *wcss)
- {
- 	wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
- 	if (IS_ERR(wcss->cx_supply))
-@@ -1033,12 +1057,14 @@ static int q6v5_wcss_probe(struct platfo
- 	if (ret)
- 		goto free_rproc;
- 
--	if (wcss->version == WCSS_QCS404) {
--		ret = q6v5_wcss_init_clock(wcss);
-+	if (desc->init_clock) {
-+		ret = desc->init_clock(wcss);
- 		if (ret)
- 			goto free_rproc;
-+	}
- 
--		ret = q6v5_wcss_init_regulator(wcss);
-+	if (desc->init_regulator) {
-+		ret = desc->init_regulator(wcss);
- 		if (ret)
- 			goto free_rproc;
- 	}
-@@ -1084,6 +1110,7 @@ static void q6v5_wcss_remove(struct plat
- }
- 
- static const struct wcss_data wcss_ipq8074_res_init = {
-+	.init_clock = ipq8074_init_clock,
- 	.firmware_name = "IPQ8074/q6_fw.mdt",
- 	.crash_reason_smem = WCSS_CRASH_REASON,
- 	.aon_reset_required = true,
-@@ -1093,6 +1120,8 @@ static const struct wcss_data wcss_ipq80
- };
- 
- static const struct wcss_data wcss_qcs404_res_init = {
-+	.init_clock = qcs404_init_clock,
-+	.init_regulator = qcs404_init_regulator,
- 	.crash_reason_smem = WCSS_CRASH_REASON,
- 	.firmware_name = "wcnss.mdt",
- 	.version = WCSS_QCS404,

target/linux/qualcommax/patches-6.6/0113-remoteproc-qcom-Add-secure-PIL-support.patch

@@ -1,143 +0,0 @@
-From 7358d42dfbdfdb5d4f1d0d4c2e5c2bb4143a29b0 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Sat, 30 Jan 2021 10:50:06 +0530
-Subject: [PATCH] remoteproc: qcom: Add secure PIL support
-
-IPQ8074 uses secure PIL. Hence, adding the support for the same.
-
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Signed-off-by: Nikhil Prakash V <[email protected]>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++--
- 1 file changed, 40 insertions(+), 3 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -18,6 +18,7 @@
- #include <linux/regulator/consumer.h>
- #include <linux/reset.h>
- #include <linux/soc/qcom/mdt_loader.h>
-+#include <linux/firmware/qcom/qcom_scm.h>
- #include "qcom_common.h"
- #include "qcom_pil_info.h"
- #include "qcom_q6v5.h"
-@@ -86,6 +87,9 @@
- #define TCSR_WCSS_CLK_ENABLE	0x14
- 
- #define MAX_HALT_REG		3
-+
-+#define WCNSS_PAS_ID		6
-+
- enum {
- 	WCSS_IPQ8074,
- 	WCSS_QCS404,
-@@ -134,6 +138,7 @@ struct q6v5_wcss {
- 	unsigned int crash_reason_smem;
- 	u32 version;
- 	bool requires_force_stop;
-+	bool need_mem_protection;
- 
- 	struct qcom_rproc_glink glink_subdev;
- 	struct qcom_rproc_ssr ssr_subdev;
-@@ -152,6 +157,7 @@ struct wcss_data {
- 	int ssctl_id;
- 	const struct rproc_ops *ops;
- 	bool requires_force_stop;
-+	bool need_mem_protection;
- };
- 
- static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
-@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc
- 
- 	qcom_q6v5_prepare(&wcss->q6v5);
- 
-+	if (wcss->need_mem_protection) {
-+		ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
-+		if (ret) {
-+			dev_err(wcss->dev, "wcss_reset failed\n");
-+			return ret;
-+		}
-+		goto wait_for_reset;
-+	}
-+
- 	/* Release Q6 and WCSS reset */
- 	ret = reset_control_deassert(wcss->wcss_reset);
- 	if (ret) {
-@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc
- 	if (ret)
- 		goto wcss_q6_reset;
- 
-+wait_for_reset:
- 	ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
- 	if (ret == -ETIMEDOUT)
- 		dev_err(wcss->dev, "start timed out\n");
-@@ -718,6 +734,15 @@ static int q6v5_wcss_stop(struct rproc *
- 	struct q6v5_wcss *wcss = rproc->priv;
- 	int ret;
- 
-+	if (wcss->need_mem_protection) {
-+		ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
-+		if (ret) {
-+			dev_err(wcss->dev, "not able to shutdown\n");
-+			return ret;
-+		}
-+		goto pas_done;
-+	}
-+
- 	/* WCSS powerdown */
- 	if (wcss->requires_force_stop) {
- 		ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
-@@ -742,6 +767,7 @@ static int q6v5_wcss_stop(struct rproc *
- 			return ret;
- 	}
- 
-+pas_done:
- 	clk_disable_unprepare(wcss->prng_clk);
- 	qcom_q6v5_unprepare(&wcss->q6v5);
- 
-@@ -765,9 +791,15 @@ static int q6v5_wcss_load(struct rproc *
- 	struct q6v5_wcss *wcss = rproc->priv;
- 	int ret;
- 
--	ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
--				    0, wcss->mem_region, wcss->mem_phys,
--				    wcss->mem_size, &wcss->mem_reloc);
-+	if (wcss->need_mem_protection)
-+		ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
-+				    WCNSS_PAS_ID, wcss->mem_region,
-+				    wcss->mem_phys, wcss->mem_size,
-+				    &wcss->mem_reloc);
-+	else
-+		ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
-+					    0, wcss->mem_region, wcss->mem_phys,
-+					    wcss->mem_size, &wcss->mem_reloc);
- 	if (ret)
- 		return ret;
- 
-@@ -1035,6 +1067,9 @@ static int q6v5_wcss_probe(struct platfo
- 	if (!desc)
- 		return -EINVAL;
- 
-+	if (desc->need_mem_protection && !qcom_scm_is_available())
-+		return -EPROBE_DEFER;
-+
- 	rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
- 			    desc->firmware_name, sizeof(*wcss));
- 	if (!rproc) {
-@@ -1048,6 +1083,7 @@ static int q6v5_wcss_probe(struct platfo
- 
- 	wcss->version = desc->version;
- 	wcss->requires_force_stop = desc->requires_force_stop;
-+	wcss->need_mem_protection = desc->need_mem_protection;
- 
- 	ret = q6v5_wcss_init_mmio(wcss, pdev);
- 	if (ret)
-@@ -1117,6 +1153,7 @@ static const struct wcss_data wcss_ipq80
- 	.wcss_q6_reset_required = true,
- 	.ops = &q6v5_wcss_ipq8074_ops,
- 	.requires_force_stop = true,
-+	.need_mem_protection = true,
- };
- 
- static const struct wcss_data wcss_qcs404_res_init = {

target/linux/qualcommax/patches-6.6/0114-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch

@@ -1,103 +0,0 @@
-From b422c9d4f048b086ce83f44a7cfcddcce162897f Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Sat, 30 Jan 2021 10:50:07 +0530
-Subject: [PATCH] remoteproc: qcom: Add support for split q6 + m3 wlan firmware
-
-IPQ8074 supports split firmware for q6 and m3 as well.
-So add support for loading the m3 firmware before q6.
-Now the drivers works fine for both split and unified
-firmwares.
-
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Signed-off-by: Nikhil Prakash V <[email protected]>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++----
- 1 file changed, 29 insertions(+), 4 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -139,6 +139,7 @@ struct q6v5_wcss {
- 	u32 version;
- 	bool requires_force_stop;
- 	bool need_mem_protection;
-+	const char *m3_firmware_name;
- 
- 	struct qcom_rproc_glink glink_subdev;
- 	struct qcom_rproc_ssr ssr_subdev;
-@@ -147,7 +148,8 @@ struct q6v5_wcss {
- struct wcss_data {
- 	int (*init_clock)(struct q6v5_wcss *wcss);
- 	int (*init_regulator)(struct q6v5_wcss *wcss);
--	const char *firmware_name;
-+	const char *q6_firmware_name;
-+	const char *m3_firmware_name;
- 	unsigned int crash_reason_smem;
- 	u32 version;
- 	bool aon_reset_required;
-@@ -789,8 +791,29 @@ static void *q6v5_wcss_da_to_va(struct r
- static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
- {
- 	struct q6v5_wcss *wcss = rproc->priv;
-+	const struct firmware *m3_fw;
- 	int ret;
- 
-+	if (wcss->m3_firmware_name) {
-+		ret = request_firmware(&m3_fw, wcss->m3_firmware_name,
-+				       wcss->dev);
-+		if (ret)
-+			goto skip_m3;
-+
-+		ret = qcom_mdt_load_no_init(wcss->dev, m3_fw,
-+					    wcss->m3_firmware_name, 0,
-+					    wcss->mem_region, wcss->mem_phys,
-+					    wcss->mem_size, &wcss->mem_reloc);
-+
-+		release_firmware(m3_fw);
-+
-+		if (ret) {
-+			dev_err(wcss->dev, "can't load m3_fw.bXX\n");
-+			return ret;
-+		}
-+	}
-+
-+skip_m3:
- 	if (wcss->need_mem_protection)
- 		ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
- 				    WCNSS_PAS_ID, wcss->mem_region,
-@@ -1071,7 +1094,7 @@ static int q6v5_wcss_probe(struct platfo
- 		return -EPROBE_DEFER;
- 
- 	rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
--			    desc->firmware_name, sizeof(*wcss));
-+			    desc->q6_firmware_name, sizeof(*wcss));
- 	if (!rproc) {
- 		dev_err(&pdev->dev, "failed to allocate rproc\n");
- 		return -ENOMEM;
-@@ -1084,6 +1107,7 @@ static int q6v5_wcss_probe(struct platfo
- 	wcss->version = desc->version;
- 	wcss->requires_force_stop = desc->requires_force_stop;
- 	wcss->need_mem_protection = desc->need_mem_protection;
-+	wcss->m3_firmware_name = desc->m3_firmware_name;
- 
- 	ret = q6v5_wcss_init_mmio(wcss, pdev);
- 	if (ret)
-@@ -1147,7 +1171,8 @@ static void q6v5_wcss_remove(struct plat
- 
- static const struct wcss_data wcss_ipq8074_res_init = {
- 	.init_clock = ipq8074_init_clock,
--	.firmware_name = "IPQ8074/q6_fw.mdt",
-+	.q6_firmware_name = "IPQ8074/q6_fw.mdt",
-+	.m3_firmware_name = "IPQ8074/m3_fw.mdt",
- 	.crash_reason_smem = WCSS_CRASH_REASON,
- 	.aon_reset_required = true,
- 	.wcss_q6_reset_required = true,
-@@ -1160,7 +1185,7 @@ static const struct wcss_data wcss_qcs40
- 	.init_clock = qcs404_init_clock,
- 	.init_regulator = qcs404_init_regulator,
- 	.crash_reason_smem = WCSS_CRASH_REASON,
--	.firmware_name = "wcnss.mdt",
-+	.q6_firmware_name = "wcnss.mdt",
- 	.version = WCSS_QCS404,
- 	.aon_reset_required = false,
- 	.wcss_q6_reset_required = false,

target/linux/qualcommax/patches-6.6/0115-remoteproc-qcom-Add-ssr-subdevice-identifier.patch

@@ -1,24 +0,0 @@
-From 3a8f67b4770c817b04794c9a02e3f88f85d86280 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Sat, 30 Jan 2021 10:50:08 +0530
-Subject: [PATCH] remoteproc: qcom: Add ssr subdevice identifier
-
-Add name for ssr subdevice on IPQ8074 SoC.
-
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Signed-off-by: Nikhil Prakash V <[email protected]>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -1176,6 +1176,7 @@ static const struct wcss_data wcss_ipq80
- 	.crash_reason_smem = WCSS_CRASH_REASON,
- 	.aon_reset_required = true,
- 	.wcss_q6_reset_required = true,
-+	.ssr_name = "q6wcss",
- 	.ops = &q6v5_wcss_ipq8074_ops,
- 	.requires_force_stop = true,
- 	.need_mem_protection = true,

target/linux/qualcommax/patches-6.6/0116-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch

@@ -1,79 +0,0 @@
-From 8c73af6e8d78c66cfef0f551b00d375ec0b67ff3 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Sat, 30 Jan 2021 10:50:09 +0530
-Subject: [PATCH] remoteproc: qcom: Update regmap offsets for halt register
-
-Fixed issue in reading halt-regs parameter from device-tree.
-
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++--------
- 1 file changed, 14 insertions(+), 8 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -86,7 +86,7 @@
- #define TCSR_WCSS_CLK_MASK	0x1F
- #define TCSR_WCSS_CLK_ENABLE	0x14
- 
--#define MAX_HALT_REG		3
-+#define MAX_HALT_REG		4
- 
- #define WCNSS_PAS_ID		6
- 
-@@ -154,6 +154,7 @@ struct wcss_data {
- 	u32 version;
- 	bool aon_reset_required;
- 	bool wcss_q6_reset_required;
-+	bool bcr_reset_required;
- 	const char *ssr_name;
- 	const char *sysmon_name;
- 	int ssctl_id;
-@@ -875,10 +876,13 @@ static int q6v5_wcss_init_reset(struct q
- 		}
- 	}
- 
--	wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset");
--	if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
--		dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
--		return PTR_ERR(wcss->wcss_q6_bcr_reset);
-+	if (desc->bcr_reset_required) {
-+		wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev,
-+									   "wcss_q6_bcr_reset");
-+		if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
-+			dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
-+			return PTR_ERR(wcss->wcss_q6_bcr_reset);
-+		}
- 	}
- 
- 	return 0;
-@@ -928,9 +932,9 @@ static int q6v5_wcss_init_mmio(struct q6
- 		return -EINVAL;
- 	}
- 
--	wcss->halt_q6 = halt_reg[0];
--	wcss->halt_wcss = halt_reg[1];
--	wcss->halt_nc = halt_reg[2];
-+	wcss->halt_q6 = halt_reg[1];
-+	wcss->halt_wcss = halt_reg[2];
-+	wcss->halt_nc = halt_reg[3];
- 
- 	return 0;
- }
-@@ -1176,6 +1180,7 @@ static const struct wcss_data wcss_ipq80
- 	.crash_reason_smem = WCSS_CRASH_REASON,
- 	.aon_reset_required = true,
- 	.wcss_q6_reset_required = true,
-+	.bcr_reset_required = false,
- 	.ssr_name = "q6wcss",
- 	.ops = &q6v5_wcss_ipq8074_ops,
- 	.requires_force_stop = true,
-@@ -1190,6 +1195,7 @@ static const struct wcss_data wcss_qcs40
- 	.version = WCSS_QCS404,
- 	.aon_reset_required = false,
- 	.wcss_q6_reset_required = false,
-+	.bcr_reset_required = true,
- 	.ssr_name = "mpss",
- 	.sysmon_name = "wcnss",
- 	.ssctl_id = 0x12,

target/linux/qualcommax/patches-6.6/0117-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch

@@ -1,26 +0,0 @@
-From ff7c6533ed8c4de58ed6c8aab03ea59c03eb4f31 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Sat, 30 Jan 2021 10:50:10 +0530
-Subject: [PATCH] dt-bindings: clock: qcom: Add reset for WCSSAON
-
-Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
-
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Signed-off-by: Nikhil Prakash V <[email protected]>
-Acked-by: Rob Herring <[email protected]>
-Acked-by: Stephen Boyd <[email protected]>
----
- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-@@ -381,6 +381,7 @@
- #define GCC_NSSPORT4_RESET			143
- #define GCC_NSSPORT5_RESET			144
- #define GCC_NSSPORT6_RESET			145
-+#define GCC_WCSSAON_RESET			146
- 
- #define USB0_GDSC				0
- #define USB1_GDSC				1

target/linux/qualcommax/patches-6.6/0118-clk-qcom-Add-WCSSAON-reset.patch

@@ -1,25 +0,0 @@
-From 43d9788f546d24df22d8ba3fcc2497d7ccc198f3 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Sat, 30 Jan 2021 10:50:11 +0530
-Subject: [PATCH] clk: qcom: Add WCSSAON reset
-
-Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
-
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Signed-off-by: Nikhil Prakash V <[email protected]>
-Acked-by: Stephen Boyd <[email protected]>
----
- drivers/clk/qcom/gcc-ipq8074.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -4712,6 +4712,7 @@ static const struct qcom_reset_map gcc_i
- 	[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
- 	[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
- 	[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
-+	[GCC_WCSSAON_RESET] = { 0x59010, 0 },
- };
- 
- static struct gdsc *gcc_ipq8074_gdscs[] = {

target/linux/qualcommax/patches-6.6/0119-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch

@@ -1,48 +0,0 @@
-From 406a332fd1bcc4e18d73cce390f56272fe9111d7 Mon Sep 17 00:00:00 2001
-From: Sivaprakash Murugesan <[email protected]>
-Date: Fri, 17 Apr 2020 16:37:10 +0530
-Subject: [PATCH] remoteproc: wcss: disable auto boot for IPQ8074
-
-There is no need for remoteproc to boot automatically, ath11k will trigger
-booting when its probing.
-
-Signed-off-by: Sivaprakash Murugesan <[email protected]>
-Signed-off-by: Robert Marko <[email protected]>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -161,6 +161,7 @@ struct wcss_data {
- 	const struct rproc_ops *ops;
- 	bool requires_force_stop;
- 	bool need_mem_protection;
-+	bool need_auto_boot;
- };
- 
- static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
-@@ -1149,6 +1150,7 @@ static int q6v5_wcss_probe(struct platfo
- 						      desc->sysmon_name,
- 						      desc->ssctl_id);
- 
-+	rproc->auto_boot = desc->need_auto_boot;
- 	ret = rproc_add(rproc);
- 	if (ret)
- 		goto free_rproc;
-@@ -1185,6 +1187,7 @@ static const struct wcss_data wcss_ipq80
- 	.ops = &q6v5_wcss_ipq8074_ops,
- 	.requires_force_stop = true,
- 	.need_mem_protection = true,
-+	.need_auto_boot = false,
- };
- 
- static const struct wcss_data wcss_qcs404_res_init = {
-@@ -1201,6 +1204,7 @@ static const struct wcss_data wcss_qcs40
- 	.ssctl_id = 0x12,
- 	.ops = &q6v5_wcss_qcs404_ops,
- 	.requires_force_stop = false,
-+	.need_auto_boot = true,
- };
- 
- static const struct of_device_id q6v5_wcss_of_match[] = {

target/linux/qualcommax/patches-6.6/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch

@@ -1,120 +0,0 @@
-From 7388400b8bd42f71d040dbf2fdbdcb834fcc0ede Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <[email protected]>
-Date: Sat, 30 Jan 2021 10:50:13 +0530
-Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
-
-Enable remoteproc WCSS PIL driver with glink and ssr subdevices.
-Also enables smp2p and mailboxes required for IPC.
-
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Signed-off-by: Nikhil Prakash V <[email protected]>
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++
- 1 file changed, 81 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -142,6 +142,32 @@
- 		};
- 	};
- 
-+	wcss: smp2p-wcss {
-+		compatible = "qcom,smp2p";
-+		qcom,smem = <435>, <428>;
-+
-+		interrupt-parent = <&intc>;
-+		interrupts = <0 322 1>;
-+
-+		mboxes = <&apcs_glb 9>;
-+
-+		qcom,local-pid = <0>;
-+		qcom,remote-pid = <1>;
-+
-+		wcss_smp2p_out: master-kernel {
-+			qcom,entry-name = "master-kernel";
-+			qcom,smp2p-feature-ssr-ack;
-+			#qcom,smem-state-cells = <1>;
-+		};
-+
-+		wcss_smp2p_in: slave-kernel {
-+			qcom,entry-name = "slave-kernel";
-+
-+			interrupt-controller;
-+			#interrupt-cells = <2>;
-+		};
-+	};
-+
- 	soc: soc@0 {
- 		#address-cells = <1>;
- 		#size-cells = <1>;
-@@ -420,6 +446,11 @@
- 			reg = <0x01937000 0x21000>;
- 		};
- 
-+		tcsr_q6: syscon@1945000 {
-+			compatible = "syscon";
-+			reg = <0x01945000 0xe000>;
-+		};
-+
- 		spmi_bus: spmi@200f000 {
- 			compatible = "qcom,spmi-pmic-arb";
- 			reg = <0x0200f000 0x001000>,
-@@ -967,6 +998,56 @@
- 				      "axi_s_sticky";
- 			status = "disabled";
- 		};
-+
-+		q6v5_wcss: q6v5_wcss@cd00000 {
-+			compatible = "qcom,ipq8074-wcss-pil";
-+			reg = <0x0cd00000 0x4040>,
-+			      <0x004ab000 0x20>;
-+			reg-names = "qdsp6",
-+				    "rmb";
-+			qca,auto-restart;
-+			qca,extended-intc;
-+			interrupts-extended = <&intc 0 325 1>,
-+					      <&wcss_smp2p_in 0 0>,
-+					      <&wcss_smp2p_in 1 0>,
-+					      <&wcss_smp2p_in 2 0>,
-+					      <&wcss_smp2p_in 3 0>;
-+			interrupt-names = "wdog",
-+					  "fatal",
-+					  "ready",
-+					  "handover",
-+					  "stop-ack";
-+
-+			resets = <&gcc GCC_WCSSAON_RESET>,
-+				 <&gcc GCC_WCSS_BCR>,
-+				 <&gcc GCC_WCSS_Q6_BCR>;
-+
-+			reset-names = "wcss_aon_reset",
-+				      "wcss_reset",
-+				      "wcss_q6_reset";
-+
-+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
-+			clock-names = "prng";
-+
-+			qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
-+
-+			qcom,smem-states = <&wcss_smp2p_out 0>,
-+					   <&wcss_smp2p_out 1>;
-+			qcom,smem-state-names = "shutdown",
-+						"stop";
-+
-+			memory-region = <&q6_region>;
-+
-+			glink-edge {
-+				interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
-+				qcom,remote-pid = <1>;
-+				mboxes = <&apcs_glb 8>;
-+
-+				rpm_requests {
-+					qcom,glink-channels = "IPCRTR";
-+				};
-+			};
-+		};
- 	};
- 
- 	timer {

target/linux/qualcommax/patches-6.6/0121-arm64-dts-ipq8074-Add-WLAN-node.patch

@@ -1,135 +0,0 @@
-From a67d1901741c162645eda0dbdc3a2c0c2aff5cf4 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Tue, 21 Dec 2021 14:49:36 +0100
-Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node
-
-IPQ8074 has a AHB based Q6v5 802.11ax radios that are supported
-by the ath11k.
-
-Add the required DT node to enable the built-in radios.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++
- 1 file changed, 111 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -1048,6 +1048,117 @@
- 				};
- 			};
- 		};
-+
-+		wifi: wifi@c0000000 {
-+			compatible = "qcom,ipq8074-wifi";
-+			reg = <0xc000000 0x2000000>;
-+
-+			interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
-+				     <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
-+
-+			interrupt-names = "misc-pulse1",
-+					  "misc-latch",
-+					  "sw-exception",
-+					  "ce0",
-+					  "ce1",
-+					  "ce2",
-+					  "ce3",
-+					  "ce4",
-+					  "ce5",
-+					  "ce6",
-+					  "ce7",
-+					  "ce8",
-+					  "ce9",
-+					  "ce10",
-+					  "ce11",
-+					  "host2wbm-desc-feed",
-+					  "host2reo-re-injection",
-+					  "host2reo-command",
-+					  "host2rxdma-monitor-ring3",
-+					  "host2rxdma-monitor-ring2",
-+					  "host2rxdma-monitor-ring1",
-+					  "reo2ost-exception",
-+					  "wbm2host-rx-release",
-+					  "reo2host-status",
-+					  "reo2host-destination-ring4",
-+					  "reo2host-destination-ring3",
-+					  "reo2host-destination-ring2",
-+					  "reo2host-destination-ring1",
-+					  "rxdma2host-monitor-destination-mac3",
-+					  "rxdma2host-monitor-destination-mac2",
-+					  "rxdma2host-monitor-destination-mac1",
-+					  "ppdu-end-interrupts-mac3",
-+					  "ppdu-end-interrupts-mac2",
-+					  "ppdu-end-interrupts-mac1",
-+					  "rxdma2host-monitor-status-ring-mac3",
-+					  "rxdma2host-monitor-status-ring-mac2",
-+					  "rxdma2host-monitor-status-ring-mac1",
-+					  "host2rxdma-host-buf-ring-mac3",
-+					  "host2rxdma-host-buf-ring-mac2",
-+					  "host2rxdma-host-buf-ring-mac1",
-+					  "rxdma2host-destination-ring-mac3",
-+					  "rxdma2host-destination-ring-mac2",
-+					  "rxdma2host-destination-ring-mac1",
-+					  "host2tcl-input-ring4",
-+					  "host2tcl-input-ring3",
-+					  "host2tcl-input-ring2",
-+					  "host2tcl-input-ring1",
-+					  "wbm2host-tx-completions-ring3",
-+					  "wbm2host-tx-completions-ring2",
-+					  "wbm2host-tx-completions-ring1",
-+					  "tcl2host-status-ring";
-+			qcom,rproc = <&q6v5_wcss>;
-+			status = "disabled";
-+		};
- 	};
- 
- 	timer {

target/linux/qualcommax/patches-6.6/0122-arm64-dts-ipq8074-add-CPU-clock.patch

@@ -1,59 +0,0 @@
-From cb3ef99c1553565e1dc0301ccd5c1c0fa2d15c15 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Fri, 31 Dec 2021 17:56:14 +0100
-Subject: [PATCH] arm64: dts: ipq8074: add CPU clock
-
-Now that CPU clock is exposed and can be controlled, add the necessary
-properties to the CPU nodes.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -5,6 +5,7 @@
- 
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
-+#include <dt-bindings/clock/qcom,apss-ipq.h>
- 
- / {
- 	#address-cells = <2>;
-@@ -38,6 +39,8 @@
- 			reg = <0x0>;
- 			next-level-cache = <&l2_0>;
- 			enable-method = "psci";
-+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+			clock-names = "cpu";
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -46,6 +49,8 @@
- 			enable-method = "psci";
- 			reg = <0x1>;
- 			next-level-cache = <&l2_0>;
-+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+			clock-names = "cpu";
- 		};
- 
- 		cpu2: cpu@2 {
-@@ -54,6 +59,8 @@
- 			enable-method = "psci";
- 			reg = <0x2>;
- 			next-level-cache = <&l2_0>;
-+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+			clock-names = "cpu";
- 		};
- 
- 		cpu3: cpu@3 {
-@@ -62,6 +69,8 @@
- 			enable-method = "psci";
- 			reg = <0x3>;
- 			next-level-cache = <&l2_0>;
-+			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+			clock-names = "cpu";
- 		};
- 
- 		l2_0: l2-cache {

target/linux/qualcommax/patches-6.6/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch

@@ -1,48 +0,0 @@
-From 347ca56e86c99021fad059b9a8ef101245b8507e Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Fri, 31 Dec 2021 20:38:06 +0100
-Subject: [PATCH] arm64: dts: ipq8074: add cooling cells to CPU nodes
-
-Since there is CPU Freq support as well as thermal sensor support
-now for the IPQ8074, add cooling cells to CPU nodes so that they can
-be used as cooling devices using CPU Freq.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -41,6 +41,7 @@
- 			enable-method = "psci";
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
-+			#cooling-cells = <2>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -51,6 +52,7 @@
- 			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
-+			#cooling-cells = <2>;
- 		};
- 
- 		cpu2: cpu@2 {
-@@ -61,6 +63,7 @@
- 			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
-+			#cooling-cells = <2>;
- 		};
- 
- 		cpu3: cpu@3 {
-@@ -71,6 +74,7 @@
- 			next-level-cache = <&l2_0>;
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
-+			#cooling-cells = <2>;
- 		};
- 
- 		l2_0: l2-cache {

target/linux/qualcommax/patches-6.6/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch

@@ -1,121 +0,0 @@
-From 04d2fc6a551bbd972a6428059b45ce79cb9de9d7 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Fri, 6 May 2022 22:38:24 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add QFPROM fuses
-
-Add the QFPROM node and CPR fuses.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 107 ++++++++++++++++++++++++++
- 1 file changed, 107 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -338,6 +338,106 @@
- 			reg = <0x000a4000 0x2000>;
- 			#address-cells = <1>;
- 			#size-cells = <1>;
-+
-+			cpr_efuse_speedbin: speedbin@125 {
-+				reg = <0x125 0x1>;
-+				bits = <0 3>;
-+			};
-+
-+			cpr_efuse_boost_cfg: boost_cfg@125 {
-+				reg = <0x125 0x1>;
-+				bits = <3 3>;
-+			};
-+
-+			cpr_efuse_misc_volt_adj: misc_volt_adj@125 {
-+				reg = <0x125 0x1>;
-+				bits = <3 3>;
-+			};
-+
-+			cpr_efuse_boost_volt: boost_volt@126 {
-+				reg = <0x126 0x1>;
-+				bits = <6 1>;
-+			};
-+
-+			cpr_efuse_revision: revision@23e {
-+				reg = <0x23e 0x1>;
-+				bits = <5 3>;
-+			};
-+
-+			cpr_efuse_ro_sel0: rosel0@249 {
-+				reg = <0x249 0x1>;
-+				bits = <0 4>;
-+			};
-+
-+			cpr_efuse_ro_sel1: rosel1@248 {
-+				reg = <0x248 0x1>;
-+				bits = <4 4>;
-+			};
-+
-+			cpr_efuse_ro_sel2: rosel2@248 {
-+				reg = <0x248 0x2>;
-+				bits = <0 4>;
-+			};
-+
-+			cpr_efuse_ro_sel3: rosel3@249 {
-+				reg = <0x249 0x1>;
-+				bits = <4 4>;
-+			};
-+
-+			cpr_efuse_init_voltage0: ivoltage0@23a {
-+				reg = <0x23a 0x1>;
-+				bits = <2 6>;
-+			};
-+
-+			cpr_efuse_init_voltage1: ivoltage1@239 {
-+				reg = <0x239 0x2>;
-+				bits = <4 6>;
-+			};
-+
-+			cpr_efuse_init_voltage2: ivoltage2@238 {
-+				reg = <0x238 0x2>;
-+				bits = <6 6>;
-+			};
-+
-+			cpr_efuse_init_voltage3: ivoltage3@238 {
-+				reg = <0x238 0x1>;
-+				bits = <0 6>;
-+			};
-+
-+			cpr_efuse_quot0: quot0@244 {
-+				reg = <0x244 0x2>;
-+				bits = <0 12>;
-+			};
-+
-+			cpr_efuse_quot1: quot1@242 {
-+				reg = <0x242 0x2>;
-+				bits = <4 12>;
-+			};
-+
-+			cpr_efuse_quot2: quot2@241 {
-+				reg = <0x241 0x2>;
-+				bits = <0 12>;
-+			};
-+
-+			cpr_efuse_quot3: quot3@245 {
-+				reg = <0x245 0x2>;
-+				bits = <4 12>;
-+			};
-+
-+			cpr_efuse_quot0_offset: quot0_offset@23d {
-+				reg = <0x23d 0x2>;
-+				bits = <6 7>;
-+			};
-+
-+			cpr_efuse_quot1_offset: quot1_offset@23c {
-+				reg = <0x23c 0x2>;
-+				bits = <7 7>;
-+			};
-+
-+			cpr_efuse_quot2_offset: quot2_offset@23c {
-+				reg = <0x23c 0x1>;
-+				bits = <0 7>;
-+			};
- 		};
- 
- 		prng: rng@e3000 {

target/linux/qualcommax/patches-6.6/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch

@@ -1,102 +0,0 @@
-From a20c4e8738a00087aa5d53fe5148ed484e23d229 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Sat, 31 Dec 2022 13:56:26 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add CPU OPP table
-
-Now that there is NVMEM CPUFreq support for IPQ8074, we can add the OPP
-table for SoC.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 52 +++++++++++++++++++++++++++
- 1 file changed, 52 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -42,6 +42,7 @@
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			#cooling-cells = <2>;
-+			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -53,6 +54,7 @@
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			#cooling-cells = <2>;
-+			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
- 		cpu2: cpu@2 {
-@@ -64,6 +66,7 @@
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			#cooling-cells = <2>;
-+			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
- 		cpu3: cpu@3 {
-@@ -75,6 +78,7 @@
- 			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- 			clock-names = "cpu";
- 			#cooling-cells = <2>;
-+			operating-points-v2 = <&cpu_opp_table>;
- 		};
- 
- 		l2_0: l2-cache {
-@@ -84,6 +88,54 @@
- 		};
- 	};
- 
-+	cpu_opp_table: opp-table {
-+		compatible = "operating-points-v2-kryo-cpu";
-+		nvmem-cells = <&cpr_efuse_speedbin>;
-+		opp-shared;
-+
-+		opp-1017600000 {
-+			opp-hz = /bits/ 64 <1017600000>;
-+			opp-microvolt = <1>;
-+			opp-supported-hw = <0xf>;
-+			clock-latency-ns = <200000>;
-+		};
-+
-+		opp-1382400000 {
-+			opp-hz = /bits/ 64 <1382400000>;
-+			opp-microvolt = <2>;
-+			opp-supported-hw = <0xf>;
-+			clock-latency-ns = <200000>;
-+		};
-+
-+		opp-1651200000 {
-+			opp-hz = /bits/ 64 <1651200000>;
-+			opp-microvolt = <3>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <200000>;
-+		};
-+
-+		opp-1843200000 {
-+			opp-hz = /bits/ 64 <1843200000>;
-+			opp-microvolt = <4>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <200000>;
-+		};
-+
-+		opp-1920000000 {
-+			opp-hz = /bits/ 64 <1920000000>;
-+			opp-microvolt = <5>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <200000>;
-+		};
-+
-+		opp-2208000000 {
-+			opp-hz = /bits/ 64 <2208000000>;
-+			opp-microvolt = <6>;
-+			opp-supported-hw = <0x1>;
-+			clock-latency-ns = <200000>;
-+		};
-+	};
-+
- 	pmu {
- 		compatible = "arm,cortex-a53-pmu";
- 		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

target/linux/qualcommax/patches-6.6/0135-arm64-dts-qcom-ipq6018-add-NSS-reserved-memory.patch

@@ -1,27 +0,0 @@
-From 7e102b1eb2ca3eff7a6f33ebeab17825e6f70956 Mon Sep 17 00:00:00 2001
-From: Robert Marko <[email protected]>
-Date: Mon, 4 Nov 2024 22:01:24 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add NSS reserved memory
-
-It seems that despite NSS not being supported in OpenWrt the memory it
-usually uses needs to be reserved anyway for stability reasons.
-
-Signed-off-by: Robert Marko <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -194,6 +194,11 @@
- 			no-map;
- 		};
- 
-+		nss_region: memory@40000000 {
-+			reg = <0x0 0x40000000 0x0 0x01000000>;
-+			no-map;
-+		};
-+
- 		bootloader@4a100000 {
- 			reg = <0x0 0x4a100000 0x0 0x400000>;
- 			no-map;

target/linux/qualcommax/patches-6.6/0136-remoteproc-qcom-wcss-populate-driver-data-for-IPQ601.patch

@@ -1,61 +0,0 @@
-From 9dd19a9ae36bc60d58287d0c52e53024d484e64d Mon Sep 17 00:00:00 2001
-From:   Gokul Sriram Palanisamy <[email protected]>
-Date:   Fri, 29 Jan 2021 22:41:59 +0530
-Subject: [PATCH 2/3] remoteproc: qcom: wcss: populate driver data for IPQ6018
-
-Populate hardcoded param using driver data for IPQ6018 SoCs.
-
-Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 19 +++++++++++++++++--
- 1 file changed, 17 insertions(+), 2 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -969,7 +969,7 @@ static int q6v5_alloc_memory_region(stru
- 	return 0;
- }
- 
--static int ipq8074_init_clock(struct q6v5_wcss *wcss)
-+static int ipq_init_clock(struct q6v5_wcss *wcss)
- {
- 	int ret;
- 
-@@ -1176,7 +1176,7 @@ static void q6v5_wcss_remove(struct plat
- }
- 
- static const struct wcss_data wcss_ipq8074_res_init = {
--	.init_clock = ipq8074_init_clock,
-+	.init_clock = ipq_init_clock,
- 	.q6_firmware_name = "IPQ8074/q6_fw.mdt",
- 	.m3_firmware_name = "IPQ8074/m3_fw.mdt",
- 	.crash_reason_smem = WCSS_CRASH_REASON,
-@@ -1190,6 +1190,20 @@ static const struct wcss_data wcss_ipq80
- 	.need_auto_boot = false,
- };
- 
-+static const struct wcss_data wcss_ipq6018_res_init = {
-+	.init_clock = ipq_init_clock,
-+	.q6_firmware_name = "IPQ6018/q6_fw.mdt",
-+	.m3_firmware_name = "IPQ6018/m3_fw.mdt",
-+	.crash_reason_smem = WCSS_CRASH_REASON,
-+	.aon_reset_required = true,
-+	.wcss_q6_reset_required = true,
-+	.bcr_reset_required = false,
-+	.ssr_name = "q6wcss",
-+	.ops = &q6v5_wcss_ipq8074_ops,
-+	.requires_force_stop = true,
-+	.need_mem_protection = true,
-+};
-+
- static const struct wcss_data wcss_qcs404_res_init = {
- 	.init_clock = qcs404_init_clock,
- 	.init_regulator = qcs404_init_regulator,
-@@ -1209,6 +1223,7 @@ static const struct wcss_data wcss_qcs40
- 
- static const struct of_device_id q6v5_wcss_of_match[] = {
- 	{ .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
-+	{ .compatible = "qcom,ipq6018-wcss-pil", .data = &wcss_ipq6018_res_init },
- 	{ .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init },
- 	{ },
- };

target/linux/qualcommax/patches-6.6/0138-arm64-dts-qcom-ipq6018-add-pwm-node.patch

@@ -1,45 +0,0 @@
-From b4a32d218d424b81a58fbd419e1114b1c1f76168 Mon Sep 17 00:00:00 2001
-From: Devi Priya <[email protected]>
-Date: Thu, 5 Oct 2023 21:35:50 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add pwm node
-
-Describe the PWM block on IPQ6018.
-
-The PWM is in the TCSR area. Make &tcsr "simple-mfd" compatible, and add
-&pwm as child of &tcsr.
-
-Add also ipq6018 specific compatible string.
-
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
-Co-developed-by: Baruch Siach <[email protected]>
-Signed-off-by: Baruch Siach <[email protected]>
-Signed-off-by: Devi Priya <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 ++++++++++++++-
- 1 file changed, 14 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -430,8 +430,21 @@
- 		};
- 
- 		tcsr: syscon@1937000 {
--			compatible = "qcom,tcsr-ipq6018", "syscon";
-+			compatible = "qcom,tcsr-ipq6018", "syscon", "simple-mfd";
- 			reg = <0x0 0x01937000 0x0 0x21000>;
-+			ranges = <0x0 0x0 0x01937000 0x21000>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			pwm: pwm@a010 {
-+				compatible = "qcom,ipq6018-pwm";
-+				reg = <0xa010 0x20>;
-+				clocks = <&gcc GCC_ADSS_PWM_CLK>;
-+				assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
-+				assigned-clock-rates = <100000000>;
-+				#pwm-cells = <2>;
-+				status = "disabled";
-+			};
- 		};
- 
- 		usb2: usb@70f8800 {

target/linux/qualcommax/patches-6.6/0140-dt-bindings-pwm-add-IPQ6018-binding.patch

@@ -1,60 +0,0 @@
-From: Devi Priya <[email protected]>
-Date: Thu, 5 Oct 2023 21:35:48 +0530
-Subject: [PATCH] dt-bindings: pwm: add IPQ6018 binding
-
-DT binding for the PWM block in Qualcomm IPQ6018 SoC.
-
-Reviewed-by: Bjorn Andersson <[email protected]>
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
-Co-developed-by: Baruch Siach <[email protected]>
-Signed-off-by: Baruch Siach <[email protected]>
-Signed-off-by: Devi Priya <[email protected]>
----
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml
-@@ -0,0 +1,45 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Qualcomm IPQ6018 PWM controller
-+
-+maintainers:
-+  - Baruch Siach <[email protected]>
-+
-+properties:
-+  compatible:
-+    const: qcom,ipq6018-pwm
-+
-+  reg:
-+    description: Offset of PWM register in the TCSR block.
-+    maxItems: 1
-+
-+  clocks:
-+    maxItems: 1
-+
-+  "#pwm-cells":
-+    const: 2
-+
-+required:
-+  - compatible
-+  - reg
-+  - clocks
-+  - "#pwm-cells"
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
-+
-+    pwm: pwm@a010 {
-+        compatible = "qcom,ipq6018-pwm";
-+        reg = <0xa010 0x20>;
-+        clocks = <&gcc GCC_ADSS_PWM_CLK>;
-+        assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
-+        assigned-clock-rates = <100000000>;
-+        #pwm-cells = <2>;
-+    };

target/linux/qualcommax/patches-6.6/0141-pwm-driver-for-qualcomm-ipq6018-pwm-block.patch

@@ -1,334 +0,0 @@
-From: Devi Priya <[email protected]>
-Date: Thu, 5 Oct 2023 21:35:47 +0530
-Subject: [PATCH] pwm: driver for qualcomm ipq6018 pwm block
-
-Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on
-driver from downstream Codeaurora kernel tree. Removed support for older
-(V1) variants because I have no access to that hardware.
-
-Tested on IPQ6010 based hardware.
-
-Co-developed-by: Baruch Siach <[email protected]>
-Signed-off-by: Baruch Siach <[email protected]>
-Signed-off-by: Devi Priya <[email protected]>
----
- drivers/pwm/Kconfig   |  12 ++
- drivers/pwm/Makefile  |   1 +
- drivers/pwm/pwm-ipq.c | 282 ++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 295 insertions(+)
- create mode 100644 drivers/pwm/pwm-ipq.c
-
---- a/drivers/pwm/Kconfig
-+++ b/drivers/pwm/Kconfig
-@@ -282,6 +282,18 @@ config PWM_INTEL_LGM
- 	  To compile this driver as a module, choose M here: the module
- 	  will be called pwm-intel-lgm.
- 
-+config PWM_IPQ
-+	tristate "IPQ PWM support"
-+	depends on ARCH_QCOM || COMPILE_TEST
-+	depends on HAVE_CLK && HAS_IOMEM
-+	help
-+	  Generic PWM framework driver for IPQ PWM block which supports
-+	  4 pwm channels. Each of the these channels can be configured
-+	  independent of each other.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called pwm-ipq.
-+
- config PWM_IQS620A
- 	tristate "Azoteq IQS620A PWM support"
- 	depends on MFD_IQS62X || COMPILE_TEST
---- a/drivers/pwm/Makefile
-+++ b/drivers/pwm/Makefile
-@@ -24,6 +24,7 @@ obj-$(CONFIG_PWM_IMX1)		+= pwm-imx1.o
- obj-$(CONFIG_PWM_IMX27)		+= pwm-imx27.o
- obj-$(CONFIG_PWM_IMX_TPM)	+= pwm-imx-tpm.o
- obj-$(CONFIG_PWM_INTEL_LGM)	+= pwm-intel-lgm.o
-+obj-$(CONFIG_PWM_IPQ)		+= pwm-ipq.o
- obj-$(CONFIG_PWM_IQS620A)	+= pwm-iqs620a.o
- obj-$(CONFIG_PWM_JZ4740)	+= pwm-jz4740.o
- obj-$(CONFIG_PWM_KEEMBAY)	+= pwm-keembay.o
---- /dev/null
-+++ b/drivers/pwm/pwm-ipq.c
-@@ -0,0 +1,280 @@
-+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
-+/*
-+ * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/pwm.h>
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/of.h>
-+#include <linux/math64.h>
-+#include <linux/of_device.h>
-+#include <linux/bitfield.h>
-+#include <linux/units.h>
-+
-+/* The frequency range supported is 1 Hz to clock rate */
-+#define IPQ_PWM_MAX_PERIOD_NS	((u64)NSEC_PER_SEC)
-+
-+/*
-+ * The max value specified for each field is based on the number of bits
-+ * in the pwm control register for that field
-+ */
-+#define IPQ_PWM_MAX_DIV		0xFFFF
-+
-+/*
-+ * Two 32-bit registers for each PWM: REG0, and REG1.
-+ * Base offset for PWM #i is at 8 * #i.
-+ */
-+#define IPQ_PWM_REG0			0
-+#define IPQ_PWM_REG0_PWM_DIV		GENMASK(15, 0)
-+#define IPQ_PWM_REG0_HI_DURATION	GENMASK(31, 16)
-+
-+#define IPQ_PWM_REG1			4
-+#define IPQ_PWM_REG1_PRE_DIV		GENMASK(15, 0)
-+/*
-+ * Enable bit is set to enable output toggling in pwm device.
-+ * Update bit is set to reflect the changed divider and high duration
-+ * values in register.
-+ */
-+#define IPQ_PWM_REG1_UPDATE		BIT(30)
-+#define IPQ_PWM_REG1_ENABLE		BIT(31)
-+
-+struct ipq_pwm_chip {
-+	struct pwm_chip chip;
-+	struct clk *clk;
-+	void __iomem *mem;
-+};
-+
-+static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip)
-+{
-+	return container_of(chip, struct ipq_pwm_chip, chip);
-+}
-+
-+static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned int reg)
-+{
-+	struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(pwm->chip);
-+	unsigned int off = 8 * pwm->hwpwm + reg;
-+
-+	return readl(ipq_chip->mem + off);
-+}
-+
-+static void ipq_pwm_reg_write(struct pwm_device *pwm, unsigned int reg,
-+			      unsigned int val)
-+{
-+	struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(pwm->chip);
-+	unsigned int off = 8 * pwm->hwpwm + reg;
-+
-+	writel(val, ipq_chip->mem + off);
-+}
-+
-+static void config_div_and_duty(struct pwm_device *pwm, unsigned int pre_div,
-+				unsigned int pwm_div, unsigned long rate, u64 duty_ns,
-+				bool enable)
-+{
-+	unsigned long hi_dur;
-+	unsigned long val = 0;
-+
-+	/*
-+	 * high duration = pwm duty * (pwm div + 1)
-+	 * pwm duty = duty_ns / period_ns
-+	 */
-+	hi_dur = div64_u64(duty_ns * rate, (pre_div + 1) * NSEC_PER_SEC);
-+
-+	val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) |
-+		FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div);
-+	ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val);
-+
-+	val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div);
-+	ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
-+
-+	/* PWM enable toggle needs a separate write to REG1 */
-+	val |= IPQ_PWM_REG1_UPDATE;
-+	if (enable)
-+		val |= IPQ_PWM_REG1_ENABLE;
-+	ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
-+}
-+
-+static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
-+			 const struct pwm_state *state)
-+{
-+	struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip);
-+	unsigned int pre_div, pwm_div, best_pre_div, best_pwm_div;
-+	unsigned long rate = clk_get_rate(ipq_chip->clk);
-+	u64 period_ns, duty_ns, period_rate;
-+	u64 min_diff;
-+
-+	if (state->polarity != PWM_POLARITY_NORMAL)
-+		return -EINVAL;
-+
-+	if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate))
-+		return -ERANGE;
-+
-+	period_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS);
-+	duty_ns = min(state->duty_cycle, period_ns);
-+
-+	/*
-+	 * period_ns is 1G or less. As long as rate is less than 16 GHz,
-+	 * period_rate does not overflow. Make that explicit.
-+	 */
-+	if ((unsigned long long)rate > 16ULL * GIGA)
-+		return -EINVAL;
-+	period_rate = period_ns * rate;
-+	best_pre_div = IPQ_PWM_MAX_DIV;
-+	best_pwm_div = IPQ_PWM_MAX_DIV;
-+	/*
-+	 * We don't need to consider pre_div values smaller than
-+	 *
-+	 *                              period_rate
-+	 *  pre_div_min := ------------------------------------
-+	 *                 NSEC_PER_SEC * (IPQ_PWM_MAX_DIV + 1)
-+	 *
-+	 * because pre_div = pre_div_min results in a better
-+	 * approximation.
-+	 */
-+	pre_div = div64_u64(period_rate,
-+			    (u64)NSEC_PER_SEC * (IPQ_PWM_MAX_DIV + 1));
-+	min_diff = period_rate;
-+
-+	for (; pre_div <= IPQ_PWM_MAX_DIV; pre_div++) {
-+		u64 remainder;
-+
-+		pwm_div = div64_u64_rem(period_rate,
-+					(u64)NSEC_PER_SEC * (pre_div + 1), &remainder);
-+		/* pwm_div is unsigned; the check below catches underflow */
-+		pwm_div--;
-+
-+		/*
-+		 * Swapping values for pre_div and pwm_div produces the same
-+		 * period length. So we can skip all settings with pre_div >
-+		 * pwm_div which results in bigger constraints for selecting
-+		 * the duty_cycle than with the two values swapped.
-+		 */
-+		if (pre_div > pwm_div)
-+			break;
-+
-+		/*
-+		 * Make sure we can do 100% duty cycle where
-+		 * hi_dur == pwm_div + 1
-+		 */
-+		if (pwm_div > IPQ_PWM_MAX_DIV - 1)
-+			continue;
-+
-+		if (remainder < min_diff) {
-+			best_pre_div = pre_div;
-+			best_pwm_div = pwm_div;
-+			min_diff = remainder;
-+
-+			if (min_diff == 0) /* bingo */
-+				break;
-+		}
-+	}
-+
-+	/* config divider values for the closest possible frequency */
-+	config_div_and_duty(pwm, best_pre_div, best_pwm_div,
-+			    rate, duty_ns, state->enabled);
-+
-+	return 0;
-+}
-+
-+static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
-+			     struct pwm_state *state)
-+{
-+	struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip);
-+	unsigned long rate = clk_get_rate(ipq_chip->clk);
-+	unsigned int pre_div, pwm_div, hi_dur;
-+	u64 effective_div, hi_div;
-+	u32 reg0, reg1;
-+
-+	reg0 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG0);
-+	reg1 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG1);
-+
-+	state->polarity = PWM_POLARITY_NORMAL;
-+	state->enabled = reg1 & IPQ_PWM_REG1_ENABLE;
-+
-+	pwm_div = FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0);
-+	hi_dur = FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0);
-+	pre_div = FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1);
-+
-+	/* No overflow here, both pre_div and pwm_div <= 0xffff */
-+	effective_div = (u64)(pre_div + 1) * (pwm_div + 1);
-+	state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, rate);
-+
-+	hi_div = hi_dur * (pre_div + 1);
-+	state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate);
-+
-+	return 0;
-+}
-+
-+static const struct pwm_ops ipq_pwm_ops = {
-+	.apply = ipq_pwm_apply,
-+	.get_state = ipq_pwm_get_state,
-+	.owner = THIS_MODULE,
-+};
-+
-+static int ipq_pwm_probe(struct platform_device *pdev)
-+{
-+	struct ipq_pwm_chip *pwm;
-+	struct device *dev = &pdev->dev;
-+	int ret;
-+
-+	pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
-+	if (!pwm)
-+		return -ENOMEM;
-+
-+	platform_set_drvdata(pdev, pwm);
-+
-+	pwm->mem = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(pwm->mem))
-+		return dev_err_probe(dev, PTR_ERR(pwm->mem),
-+				"regs map failed");
-+
-+	pwm->clk = devm_clk_get(dev, NULL);
-+	if (IS_ERR(pwm->clk))
-+		return dev_err_probe(dev, PTR_ERR(pwm->clk),
-+				"failed to get clock");
-+
-+	ret = clk_prepare_enable(pwm->clk);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "clock enable failed");
-+
-+	pwm->chip.dev = dev;
-+	pwm->chip.ops = &ipq_pwm_ops;
-+	pwm->chip.npwm = 4;
-+
-+	ret = pwmchip_add(&pwm->chip);
-+	if (ret < 0) {
-+		dev_err_probe(dev, ret, "pwmchip_add() failed\n");
-+		clk_disable_unprepare(pwm->clk);
-+	}
-+
-+	return ret;
-+}
-+
-+static void ipq_pwm_remove(struct platform_device *pdev)
-+{
-+	struct ipq_pwm_chip *pwm = platform_get_drvdata(pdev);
-+
-+	pwmchip_remove(&pwm->chip);
-+	clk_disable_unprepare(pwm->clk);
-+}
-+
-+static const struct of_device_id pwm_ipq_dt_match[] = {
-+	{ .compatible = "qcom,ipq6018-pwm", },
-+	{}
-+};
-+MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match);
-+
-+static struct platform_driver ipq_pwm_driver = {
-+	.driver = {
-+		.name = "ipq-pwm",
-+		.of_match_table = pwm_ipq_dt_match,
-+	},
-+	.probe = ipq_pwm_probe,
-+	.remove_new = ipq_pwm_remove,
-+};
-+
-+module_platform_driver(ipq_pwm_driver);
-+
-+MODULE_LICENSE("Dual BSD/GPL");

target/linux/qualcommax/patches-6.6/0142-dt-bindings-mfd-qcom-tcsr-Add-simple-mfd-support-for-IPQ6018.patch

@@ -1,148 +0,0 @@
-From: Devi Priya <[email protected]>
-Subject: [PATCH] dt-bindings: mfd: qcom,tcsr: Add simple-mfd support for IPQ6018
-Date: Thu, 5 Oct 2023 21:35:49 +0530
-
-Update the binding to include pwm as the child node to TCSR block and
-add simple-mfd support for IPQ6018.
-
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
-Signed-off-by: Devi Priya <[email protected]>
----
- .../devicetree/bindings/mfd/qcom,tcsr.yaml    | 112 +++++++++++++-----
- 1 file changed, 81 insertions(+), 31 deletions(-)
-
---- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
-+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
-@@ -15,49 +15,101 @@ description:
- 
- properties:
-   compatible:
--    items:
--      - enum:
--          - qcom,msm8976-tcsr
--          - qcom,msm8998-tcsr
--          - qcom,qcs404-tcsr
--          - qcom,sc7180-tcsr
--          - qcom,sc7280-tcsr
--          - qcom,sc8280xp-tcsr
--          - qcom,sdm630-tcsr
--          - qcom,sdm845-tcsr
--          - qcom,sdx55-tcsr
--          - qcom,sdx65-tcsr
--          - qcom,sm8150-tcsr
--          - qcom,sm8450-tcsr
--          - qcom,tcsr-apq8064
--          - qcom,tcsr-apq8084
--          - qcom,tcsr-ipq5332
--          - qcom,tcsr-ipq6018
--          - qcom,tcsr-ipq8064
--          - qcom,tcsr-ipq8074
--          - qcom,tcsr-ipq9574
--          - qcom,tcsr-mdm9615
--          - qcom,tcsr-msm8226
--          - qcom,tcsr-msm8660
--          - qcom,tcsr-msm8916
--          - qcom,tcsr-msm8953
--          - qcom,tcsr-msm8960
--          - qcom,tcsr-msm8974
--          - qcom,tcsr-msm8996
--      - const: syscon
-+    oneOf:
-+      - items:
-+          - enum:
-+              - qcom,msm8976-tcsr
-+              - qcom,msm8998-tcsr
-+              - qcom,qcs404-tcsr
-+              - qcom,sc7180-tcsr
-+              - qcom,sc7280-tcsr
-+              - qcom,sc8280xp-tcsr
-+              - qcom,sdm630-tcsr
-+              - qcom,sdm845-tcsr
-+              - qcom,sdx55-tcsr
-+              - qcom,sdx65-tcsr
-+              - qcom,sm4450-tcsr
-+              - qcom,sm8150-tcsr
-+              - qcom,sm8450-tcsr
-+              - qcom,tcsr-apq8064
-+              - qcom,tcsr-apq8084
-+              - qcom,tcsr-ipq5332
-+              - qcom,tcsr-ipq8064
-+              - qcom,tcsr-ipq8074
-+              - qcom,tcsr-ipq9574
-+              - qcom,tcsr-mdm9615
-+              - qcom,tcsr-msm8226
-+              - qcom,tcsr-msm8660
-+              - qcom,tcsr-msm8916
-+              - qcom,tcsr-msm8953
-+              - qcom,tcsr-msm8960
-+              - qcom,tcsr-msm8974
-+              - qcom,tcsr-msm8996
-+          - const: syscon
-+      - items:
-+          - const: qcom,tcsr-ipq6018
-+          - const: syscon
-+          - const: simple-mfd
- 
-   reg:
-     maxItems: 1
- 
-+  ranges: true
-+
-+  "#address-cells":
-+    const: 1
-+
-+  "#size-cells":
-+    const: 1
-+
-+patternProperties:
-+  "pwm@[a-f0-9]+$":
-+    type: object
-+    $ref: /schemas/pwm/qcom,ipq6018-pwm.yaml
-+
-+
- required:
-   - compatible
-   - reg
- 
-+allOf:
-+  - if:
-+      not:
-+        properties:
-+          compatible:
-+            contains:
-+              enum:
-+                - qcom,tcsr-ipq6018
-+    then:
-+      patternProperties:
-+        "pwm@[a-f0-9]+$": false
-+
- additionalProperties: false
- 
- examples:
-+  # Example 1 - Syscon node found on MSM8960
-   - |
-     syscon@1a400000 {
-         compatible = "qcom,tcsr-msm8960", "syscon";
-         reg = <0x1a400000 0x100>;
-     };
-+  # Example 2 - Syscon node found on IPQ6018
-+  - |
-+    #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
-+
-+    syscon@1937000 {
-+        compatible = "qcom,tcsr-ipq6018", "syscon", "simple-mfd";
-+        reg = <0x01937000 0x21000>;
-+        ranges = <0 0x1937000 0x21000>;
-+        #address-cells = <1>;
-+        #size-cells = <1>;
-+
-+        pwm: pwm@a010 {
-+            compatible = "qcom,ipq6018-pwm";
-+            reg = <0xa010 0x20>;
-+            clocks = <&gcc GCC_ADSS_PWM_CLK>;
-+            assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
-+            assigned-clock-rates = <100000000>;
-+            #pwm-cells = <2>;
-+        };
-+    };
-\ No newline at end of file

target/linux/qualcommax/patches-6.6/0150-dt-bindings-nvmem-add-IPQ5018-compatible.patch

@@ -1,22 +0,0 @@
-From: Sricharan Ramabadhran <[email protected]>
-Subject: [PATCH V2 1/1] dt-bindings: nvmem: Add compatible for IPQ5018
-Date: Fri, 15 Sep 2023 17:31:20 +0530
-
-Document the QFPROM on IPQ5018.
-
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
-Signed-off-by: Sricharan Ramabadhran <[email protected]>
----
- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
-+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
-@@ -18,6 +18,7 @@ properties:
-       - enum:
-           - qcom,apq8064-qfprom
-           - qcom,apq8084-qfprom
-+          - qcom,ipq5018-qfprom
-           - qcom,ipq5332-qfprom
-           - qcom,ipq6018-qfprom
-           - qcom,ipq8064-qfprom

target/linux/qualcommax/patches-6.6/0151-dt-bindings-thermal-qcom-tsens-Add-ipq5018-compatible.patch

@@ -1,26 +0,0 @@
-From: Sricharan Ramabadhran <[email protected]>
-Date: Fri, 22 Sep 2023 17:21:13 +0530
-Subject: [PATCH] dt-bindings: thermal: qcom-tsens: Add ipq5018 compatible
-
-IPQ5018 has tsens v1.0 block with 4 sensors and 1 interrupt.
-
-Signed-off-by: Sricharan Ramabadhran <[email protected]>
----
---- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
-+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
-@@ -39,6 +39,7 @@ properties:
-       - description: v1 of TSENS
-         items:
-           - enum:
-+              - qcom,ipq5018-tsens
-               - qcom,msm8956-tsens
-               - qcom,msm8976-tsens
-               - qcom,qcs404-tsens
-@@ -232,6 +233,7 @@ allOf:
-         compatible:
-           contains:
-             enum:
-+              - qcom,ipq5018-tsens
-               - qcom,ipq8064-tsens
-               - qcom,msm8960-tsens
-               - qcom,tsens-v0_1

target/linux/qualcommax/patches-6.6/0152-thermal-qcom-add-new-feat-for-soc-without-rpm.patch

@@ -1,45 +0,0 @@
-From: Sricharan Ramabadhran <[email protected]>
-Subject: [PATCH] thermal/drivers/qcom: Add new feat for soc without rpm
-Date: Fri, 22 Sep 2023 17:21:14 +0530
-
-In IPQ5018, Tsens IP doesn't have RPM. Hence the early init to
-enable tsens would not be done. So add a flag for that in feat
-and skip enable checks. Without this, tsens probe fails.
-
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Signed-off-by: Sricharan Ramabadhran <[email protected]>
----
- drivers/thermal/qcom/tsens.c | 2 +-
- drivers/thermal/qcom/tsens.h | 3 +++
- 2 files changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -974,7 +974,7 @@ int __init init_common(struct tsens_priv
- 	ret = regmap_field_read(priv->rf[TSENS_EN], &enabled);
- 	if (ret)
- 		goto err_put_device;
--	if (!enabled) {
-+	if (!enabled && !(priv->feat->ignore_enable)) {
- 		dev_err(dev, "%s: device not enabled\n", __func__);
- 		ret = -ENODEV;
- 		goto err_put_device;
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -505,6 +505,8 @@ enum regfield_ids {
-  * @srot_split: does the IP neatly splits the register space into SROT and TM,
-  *              with SROT only being available to secure boot firmware?
-  * @has_watchdog: does this IP support watchdog functionality?
-+ * @ignore_enable: does this IP reside in a soc that does not have rpm to
-+ *                 do pre-init.
-  * @max_sensors: maximum sensors supported by this version of the IP
-  * @trip_min_temp: minimum trip temperature supported by this version of the IP
-  * @trip_max_temp: maximum trip temperature supported by this version of the IP
-@@ -516,6 +518,7 @@ struct tsens_features {
- 	unsigned int adc:1;
- 	unsigned int srot_split:1;
- 	unsigned int has_watchdog:1;
-+	unsigned int ignore_enable:1;
- 	unsigned int max_sensors;
- 	int trip_min_temp;
- 	int trip_max_temp;

target/linux/qualcommax/patches-6.6/0153-thermal-qcom-tsens-add-support-for-IPQ5018-tsens.patch

@@ -1,118 +0,0 @@
-From: Sricharan Ramabadhran <[email protected]>
-Subject: [PATCH] thermal/drivers/tsens: Add support for IPQ5018 tsens
-Date: Fri, 22 Sep 2023 17:21:15 +0530
-
-IPQ5018 has tsens IP V1.0, 4 sensors and 1 interrupt.
-The soc does not have a RPM, hence tsens has to be reset and
-enabled in the driver init. Adding the driver support for same.
-
-Signed-off-by: Sricharan Ramabadhran <[email protected]>
----
- drivers/thermal/qcom/tsens-v1.c | 60 +++++++++++++++++++++++++++++++++
- drivers/thermal/qcom/tsens.c    |  3 ++
- drivers/thermal/qcom/tsens.h    |  2 +-
- 3 files changed, 64 insertions(+), 1 deletion(-)
-
---- a/drivers/thermal/qcom/tsens-v1.c
-+++ b/drivers/thermal/qcom/tsens-v1.c
-@@ -79,6 +79,18 @@ static struct tsens_features tsens_v1_fe
- 	.trip_max_temp	= 120000,
- };
- 
-+static struct tsens_features tsens_v1_ipq5018_feat = {
-+	.ver_major	= VER_1_X,
-+	.crit_int	= 0,
-+	.combo_int	= 0,
-+	.adc		= 1,
-+	.srot_split	= 1,
-+	.max_sensors	= 11,
-+	.trip_min_temp	= -40000,
-+	.trip_max_temp	= 120000,
-+	.ignore_enable	= 1,
-+};
-+
- static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
- 	/* ----- SROT ------ */
- 	/* VERSION */
-@@ -150,6 +162,41 @@ static int __init init_8956(struct tsens
- 	return init_common(priv);
- }
- 
-+static int __init init_ipq5018(struct tsens_priv *priv)
-+{
-+	int ret;
-+	u32 mask;
-+
-+	ret = init_common(priv);
-+	if (ret < 0) {
-+		dev_err(priv->dev, "Init common failed %d\n", ret);
-+		return ret;
-+	}
-+
-+	ret = regmap_field_write(priv->rf[TSENS_SW_RST], 1);
-+	if (ret) {
-+		dev_err(priv->dev, "Reset failed\n");
-+		return ret;
-+	}
-+
-+	mask = GENMASK(priv->num_sensors, 0);
-+	ret = regmap_field_update_bits(priv->rf[SENSOR_EN], mask, mask);
-+	if (ret) {
-+		dev_err(priv->dev, "Sensor Enable failed\n");
-+		return ret;
-+	}
-+
-+	ret = regmap_field_write(priv->rf[TSENS_EN], 1);
-+	if (ret) {
-+		dev_err(priv->dev, "Enable failed\n");
-+		return ret;
-+	}
-+
-+	ret = regmap_field_write(priv->rf[TSENS_SW_RST], 0);
-+
-+	return ret;
-+}
-+
- static const struct tsens_ops ops_generic_v1 = {
- 	.init		= init_common,
- 	.calibrate	= calibrate_v1,
-@@ -194,3 +241,16 @@ struct tsens_plat_data data_8976 = {
- 	.feat		= &tsens_v1_feat,
- 	.fields		= tsens_v1_regfields,
- };
-+
-+const struct tsens_ops ops_ipq5018 = {
-+	.init		= init_ipq5018,
-+	.calibrate	= tsens_calibrate_common,
-+	.get_temp	= get_temp_tsens_valid,
-+};
-+
-+struct tsens_plat_data data_ipq5018 = {
-+	.num_sensors	= 5,
-+	.ops		= &ops_ipq5018,
-+	.feat		= &tsens_v1_ipq5018_feat,
-+	.fields		= tsens_v1_regfields,
-+};
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -1101,6 +1101,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, t
- 
- static const struct of_device_id tsens_table[] = {
- 	{
-+		.compatible = "qcom,ipq5018-tsens",
-+		.data = &data_ipq5018,
-+	}, {
- 		.compatible = "qcom,ipq8064-tsens",
- 		.data = &data_8960,
- 	}, {
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -645,7 +645,7 @@ extern struct tsens_plat_data data_8960;
- extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8974, data_9607;
- 
- /* TSENS v1 targets */
--extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_8956;
-+extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_8956, data_ipq5018;
- 
- /* TSENS v2 targets */
- extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;

target/linux/qualcommax/patches-6.6/0154-dts-qcom-IPQ5018-add-tsens-node.patch

@@ -1,200 +0,0 @@
-From: Sricharan Ramabadhran <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add tsens node
-Date: Fri, 22 Sep 2023 17:21:16 +0530
-
-IPQ5018 has tsens V1.0 IP with 4 sensors.
-There is no RPM, so tsens has to be manually enabled. Adding the tsens
-and nvmem node and IPQ5018 has 4 thermal sensors (zones). With the
-critical temperature being 120'C and action is to reboot. Adding all
-the 4 zones here.
-
-Signed-off-by: Sricharan Ramabadhran <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 169 ++++++++++++++++++++++++++
- 1 file changed, 169 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -149,6 +149,117 @@
- 			status = "disabled";
- 		};
- 
-+		qfprom: qfprom@a0000 {
-+			compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
-+			reg = <0xa0000 0x1000>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			tsens_mode: mode@249 {
-+				reg = <0x249 1>;
-+				bits = <0 3>;
-+			};
-+
-+			tsens_base1: base1@249 {
-+				reg = <0x249 2>;
-+				bits = <3 8>;
-+			};
-+
-+			tsens_base2: base2@24a {
-+				reg = <0x24a 2>;
-+				bits = <3 8>;
-+			};
-+
-+			tsens_s0_p1: s0-p1@24b {
-+				reg = <0x24b 0x2>;
-+				bits = <2 6>;
-+			};
-+
-+			tsens_s0_p2: s0-p2@24c {
-+				reg = <0x24c 0x1>;
-+				bits = <1 6>;
-+			};
-+
-+			tsens_s1_p1: s1-p1@24c {
-+				reg = <0x24c 0x2>;
-+				bits = <7 6>;
-+			};
-+
-+			tsens_s1_p2: s1-p2@24d {
-+				reg = <0x24d 0x2>;
-+				bits = <5 6>;
-+			};
-+
-+			tsens_s2_p1: s2-p1@24e {
-+				reg = <0x24e 0x2>;
-+				bits = <3 6>;
-+			};
-+
-+			tsens_s2_p2: s2-p2@24f {
-+				reg = <0x24f 0x1>;
-+				bits = <1 6>;
-+			};
-+
-+			tsens_s3_p1: s3-p1@24f {
-+				reg = <0x24f 0x2>;
-+				bits = <7 6>;
-+			};
-+
-+			tsens_s3_p2: s3-p2@250 {
-+				reg = <0x250 0x2>;
-+				bits = <5 6>;
-+			};
-+
-+			tsens_s4_p1: s4-p1@251 {
-+				reg = <0x251 0x2>;
-+				bits = <3 6>;
-+			};
-+
-+			tsens_s4_p2: s4-p2@254 {
-+				reg = <0x254 0x1>;
-+				bits = <0 6>;
-+			};
-+		};
-+
-+		tsens: thermal-sensor@4a9000 {
-+			compatible = "qcom,ipq5018-tsens";
-+			reg = <0x4a9000 0x1000>, /* TM */
-+			      <0x4a8000 0x1000>; /* SROT */
-+
-+			nvmem-cells = <&tsens_mode>,
-+				      <&tsens_base1>,
-+				      <&tsens_base2>,
-+				      <&tsens_s0_p1>,
-+				      <&tsens_s0_p2>,
-+				      <&tsens_s1_p1>,
-+				      <&tsens_s1_p2>,
-+				      <&tsens_s2_p1>,
-+				      <&tsens_s2_p2>,
-+				      <&tsens_s3_p1>,
-+				      <&tsens_s3_p2>,
-+				      <&tsens_s4_p1>,
-+				      <&tsens_s4_p2>;
-+
-+			nvmem-cell-names = "mode",
-+					   "base1",
-+					   "base2",
-+					   "s0_p1",
-+					   "s0_p2",
-+					   "s1_p1",
-+					   "s1_p2",
-+					   "s2_p1",
-+					   "s2_p2",
-+					   "s3_p1",
-+					   "s3_p2",
-+					   "s4_p1",
-+					   "s4_p2";
-+
-+			interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
-+			interrupt-names = "uplow";
-+			#qcom,sensors = <5>;
-+			#thermal-sensor-cells = <1>;
-+		};
-+
- 		tlmm: pinctrl@1000000 {
- 			compatible = "qcom,ipq5018-tlmm";
- 			reg = <0x01000000 0x300000>;
-@@ -391,6 +502,64 @@
- 			};
- 		};
- 	};
-+
-+	thermal-zones {
-+		cpu-thermal {
-+			polling-delay-passive = <0>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsens 2>;
-+
-+			trips {
-+				cpu-critical {
-+					temperature = <120000>;
-+					hysteresis = <2>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		gephy-thermal {
-+			polling-delay-passive = <0>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsens 4>;
-+
-+			trips {
-+				gephy-critical {
-+					temperature = <120000>;
-+					hysteresis = <2>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		top-glue-thermal {
-+			polling-delay-passive = <0>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsens 3>;
-+
-+			trips {
-+				top_glue-critical {
-+					temperature = <120000>;
-+					hysteresis = <2>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+
-+		ubi32-thermal {
-+			polling-delay-passive = <0>;
-+			polling-delay = <0>;
-+			thermal-sensors = <&tsens 1>;
-+
-+			trips {
-+				ubi32-critical {
-+					temperature = <120000>;
-+					hysteresis = <2>;
-+					type = "critical";
-+				};
-+			};
-+		};
-+	};
- 
- 	timer {
- 		compatible = "arm,armv8-timer";

target/linux/qualcommax/patches-6.6/0155-dt-bindings-phy-qcom-uniphy-pcie-Document-PCIe-uniphy.patch

@@ -1,85 +0,0 @@
-From: Varadarajan Narayanan <[email protected]>
-Date: Thu, 2 Jan 2025 17:00:15 +0530
-Subject: [PATCH] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
-
-From: Nitheesh Sekar <[email protected]>
-
-Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.
-
-Signed-off-by: Nitheesh Sekar <[email protected]>
-Signed-off-by: Varadarajan Narayanan <[email protected]>
----
---- /dev/null
-+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
-@@ -0,0 +1,71 @@
-+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Qualcomm UNIPHY PCIe 28LP PHY
-+
-+maintainers:
-+  - Nitheesh Sekar <[email protected]>
-+  - Varadarajan Narayanan <[email protected]>
-+
-+description:
-+  PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
-+
-+properties:
-+  compatible:
-+    enum:
-+      - qcom,ipq5332-uniphy-pcie-phy
-+
-+  reg:
-+    maxItems: 1
-+
-+  clocks:
-+    items:
-+      - description: pcie pipe clock
-+      - description: pcie ahb clock
-+
-+  resets:
-+    items:
-+      - description: phy reset
-+      - description: ahb reset
-+      - description: cfg reset
-+
-+  "#phy-cells":
-+    const: 0
-+
-+  "#clock-cells":
-+    const: 0
-+
-+  num-lanes: true
-+
-+required:
-+  - compatible
-+  - reg
-+  - clocks
-+  - resets
-+  - "#phy-cells"
-+  - "#clock-cells"
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
-+
-+    pcie0_phy: phy@4b0000 {
-+        compatible = "qcom,ipq5332-uniphy-pcie-phy";
-+        reg = <0x004b0000 0x800>;
-+
-+        clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
-+                 <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
-+
-+        resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
-+                 <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
-+                 <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
-+
-+        #clock-cells = <0>;
-+
-+        #phy-cells = <0>;
-+    };

target/linux/qualcommax/patches-6.6/0156-phy-qcom-Introduce-PCIe-UNIPHY-28LP-driver.patch

@@ -1,332 +0,0 @@
-From: Varadarajan Narayanan <[email protected]>
-Date: Thu, 2 Jan 2025 17:00:16 +0530
-Subject: [PATCH] phy: qcom: Introduce PCIe UNIPHY 28LP driver
-
-From: Nitheesh Sekar <[email protected]>
-
-Add Qualcomm PCIe UNIPHY 28LP driver support present
-in Qualcomm IPQ5332 SoC and the phy init sequence.
-
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Signed-off-by: Nitheesh Sekar <[email protected]>
-Signed-off-by: Varadarajan Narayanan <[email protected]>
----
---- a/drivers/phy/qualcomm/Kconfig
-+++ b/drivers/phy/qualcomm/Kconfig
-@@ -154,6 +154,18 @@ config PHY_QCOM_M31_USB
- 	  management. This driver is required even for peripheral only or
- 	  host only mode configurations.
- 
-+config PHY_QCOM_UNIPHY_PCIE_28LP
-+	bool "PCIE UNIPHY 28LP PHY driver"
-+	depends on ARCH_QCOM
-+	depends on HAS_IOMEM
-+	depends on OF
-+	select GENERIC_PHY
-+	help
-+	  Enable this to support the PCIe UNIPHY 28LP phy transceiver that
-+	  is used with PCIe controllers on Qualcomm IPQ5332 chips. It
-+	  handles PHY initialization, clock management required after
-+	  resetting the hardware and power management.
-+
- config PHY_QCOM_USB_HS
- 	tristate "Qualcomm USB HS PHY module"
- 	depends on USB_ULPI_BUS
---- a/drivers/phy/qualcomm/Makefile
-+++ b/drivers/phy/qualcomm/Makefile
-@@ -17,6 +17,7 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY)	+=
- obj-$(CONFIG_PHY_QCOM_QUSB2)		+= phy-qcom-qusb2.o
- obj-$(CONFIG_PHY_QCOM_SNPS_EUSB2)	+= phy-qcom-snps-eusb2.o
- obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER)	+= phy-qcom-eusb2-repeater.o
-+obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP)	+= phy-qcom-uniphy-pcie-28lp.o
- obj-$(CONFIG_PHY_QCOM_USB_HS) 		+= phy-qcom-usb-hs.o
- obj-$(CONFIG_PHY_QCOM_USB_HSIC) 	+= phy-qcom-usb-hsic.o
- obj-$(CONFIG_PHY_QCOM_USB_HS_28NM)	+= phy-qcom-usb-hs-28nm.o
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
-@@ -0,0 +1,285 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright (c) 2025, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/of.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
-+
-+#define RST_ASSERT_DELAY_MIN_US		100
-+#define RST_ASSERT_DELAY_MAX_US		150
-+#define PIPE_CLK_DELAY_MIN_US		5000
-+#define PIPE_CLK_DELAY_MAX_US		5100
-+#define CLK_EN_DELAY_MIN_US		30
-+#define CLK_EN_DELAY_MAX_US		50
-+#define CDR_CTRL_REG_1		0x80
-+#define CDR_CTRL_REG_2		0x84
-+#define CDR_CTRL_REG_3		0x88
-+#define CDR_CTRL_REG_4		0x8c
-+#define CDR_CTRL_REG_5		0x90
-+#define CDR_CTRL_REG_6		0x94
-+#define CDR_CTRL_REG_7		0x98
-+#define SSCG_CTRL_REG_1		0x9c
-+#define SSCG_CTRL_REG_2		0xa0
-+#define SSCG_CTRL_REG_3		0xa4
-+#define SSCG_CTRL_REG_4		0xa8
-+#define SSCG_CTRL_REG_5		0xac
-+#define SSCG_CTRL_REG_6		0xb0
-+#define PCS_INTERNAL_CONTROL_2	0x2d8
-+
-+#define PHY_CFG_PLLCFG				0x220
-+#define PHY_CFG_EIOS_DTCT_REG			0x3e4
-+#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME		0x3e8
-+
-+#define PHY_MODE_FIXED		0x1
-+
-+enum qcom_uniphy_pcie_type {
-+	PHY_TYPE_PCIE = 1,
-+	PHY_TYPE_PCIE_GEN2,
-+	PHY_TYPE_PCIE_GEN3,
-+};
-+
-+struct qcom_uniphy_pcie_regs {
-+	u32 offset;
-+	u32 val;
-+};
-+
-+struct qcom_uniphy_pcie_data {
-+	int lane_offset; /* offset between the lane register bases */
-+	u32 phy_type;
-+	const struct qcom_uniphy_pcie_regs *init_seq;
-+	u32 init_seq_num;
-+	u32 pipe_clk_rate;
-+};
-+
-+struct qcom_uniphy_pcie {
-+	struct phy phy;
-+	struct device *dev;
-+	const struct qcom_uniphy_pcie_data *data;
-+	struct clk_bulk_data *clks;
-+	int num_clks;
-+	struct reset_control *resets;
-+	void __iomem *base;
-+	int lanes;
-+};
-+
-+#define phy_to_dw_phy(x)	container_of((x), struct qca_uni_pcie_phy, phy)
-+
-+static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
-+	{
-+		.offset = PHY_CFG_PLLCFG,
-+		.val = 0x30,
-+	}, {
-+		.offset = PHY_CFG_EIOS_DTCT_REG,
-+		.val = 0x53ef,
-+	}, {
-+		.offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME,
-+		.val = 0xcf,
-+	},
-+};
-+
-+static const struct qcom_uniphy_pcie_data ipq5332_data = {
-+	.lane_offset	= 0x800,
-+	.phy_type	= PHY_TYPE_PCIE_GEN3,
-+	.init_seq	= ipq5332_regs,
-+	.init_seq_num	= ARRAY_SIZE(ipq5332_regs),
-+	.pipe_clk_rate	= 250000000,
-+};
-+
-+static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
-+{
-+	const struct qcom_uniphy_pcie_data *data = phy->data;
-+	const struct qcom_uniphy_pcie_regs *init_seq;
-+	void __iomem *base = phy->base;
-+	int lane, i;
-+
-+	for (lane = 0; lane < phy->lanes; lane++) {
-+		init_seq = data->init_seq;
-+
-+		for (i = 0; i < data->init_seq_num; i++)
-+			writel(init_seq[i].val, base + init_seq[i].offset);
-+
-+		base += data->lane_offset;
-+	}
-+}
-+
-+static int qcom_uniphy_pcie_power_off(struct phy *x)
-+{
-+	struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
-+
-+	clk_bulk_disable_unprepare(phy->num_clks, phy->clks);
-+
-+	return reset_control_assert(phy->resets);
-+}
-+
-+static int qcom_uniphy_pcie_power_on(struct phy *x)
-+{
-+	struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
-+	int ret;
-+
-+	ret = reset_control_assert(phy->resets);
-+	if (ret) {
-+		dev_err(phy->dev, "reset assert failed (%d)\n", ret);
-+		return ret;
-+	}
-+
-+	usleep_range(RST_ASSERT_DELAY_MIN_US, RST_ASSERT_DELAY_MAX_US);
-+
-+	ret = reset_control_deassert(phy->resets);
-+	if (ret) {
-+		dev_err(phy->dev, "reset deassert failed (%d)\n", ret);
-+		return ret;
-+	}
-+
-+	usleep_range(PIPE_CLK_DELAY_MIN_US, PIPE_CLK_DELAY_MAX_US);
-+
-+	ret = clk_bulk_prepare_enable(phy->num_clks, phy->clks);
-+	if (ret) {
-+		dev_err(phy->dev, "clk prepare and enable failed %d\n", ret);
-+		return ret;
-+	}
-+
-+	usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US);
-+
-+	qcom_uniphy_pcie_init(phy);
-+	return 0;
-+}
-+
-+static inline int qcom_uniphy_pcie_get_resources(struct platform_device *pdev,
-+						 struct qcom_uniphy_pcie *phy)
-+{
-+	struct resource *res;
-+
-+	phy->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
-+	if (IS_ERR(phy->base))
-+		return PTR_ERR(phy->base);
-+
-+	phy->num_clks = devm_clk_bulk_get_all(phy->dev, &phy->clks);
-+	if (phy->num_clks < 0)
-+		return phy->num_clks;
-+
-+	phy->resets = devm_reset_control_array_get_exclusive(phy->dev);
-+	if (IS_ERR(phy->resets))
-+		return PTR_ERR(phy->resets);
-+
-+	return 0;
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ *         +---------------+
-+ *         |   PHY block   |<<---------------------------------------+
-+ *         |               |                                         |
-+ *         |   +-------+   |                   +-----+               |
-+ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ *    clk  |   +-------+   |                   +-----+
-+ *         +---------------+
-+ */
-+static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id)
-+{
-+	const struct qcom_uniphy_pcie_data *data = phy->data;
-+	struct clk_hw *hw;
-+	char name[64];
-+
-+	snprintf(name, sizeof(name), "phy%d_pipe_clk_src", id);
-+	hw = devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0,
-+					     data->pipe_clk_rate);
-+	if (IS_ERR(hw))
-+		return dev_err_probe(phy->dev, PTR_ERR(hw),
-+				     "Unable to register %s\n", name);
-+
-+	return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw);
-+}
-+
-+static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
-+	{
-+		.compatible = "qcom,ipq5332-uniphy-pcie-phy",
-+		.data = &ipq5332_data,
-+	}, {
-+		/* Sentinel */
-+	},
-+};
-+MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table);
-+
-+static const struct phy_ops pcie_ops = {
-+	.power_on	= qcom_uniphy_pcie_power_on,
-+	.power_off	= qcom_uniphy_pcie_power_off,
-+	.owner          = THIS_MODULE,
-+};
-+
-+static int qcom_uniphy_pcie_probe(struct platform_device *pdev)
-+{
-+	struct phy_provider *phy_provider;
-+	struct device *dev = &pdev->dev;
-+	struct qcom_uniphy_pcie *phy;
-+	struct phy *generic_phy;
-+	int ret;
-+
-+	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
-+	if (!phy)
-+		return -ENOMEM;
-+
-+	platform_set_drvdata(pdev, phy);
-+	phy->dev = &pdev->dev;
-+
-+	phy->data = of_device_get_match_data(dev);
-+	if (!phy->data)
-+		return -EINVAL;
-+
-+	phy->lanes = 1;
-+	ret = of_property_read_u32(dev->of_node, "num-lanes", &phy->lanes);
-+
-+	ret = qcom_uniphy_pcie_get_resources(pdev, phy);
-+	if (ret < 0)
-+		return dev_err_probe(&pdev->dev, ret,
-+				     "failed to get resources: %d\n", ret);
-+
-+	generic_phy = devm_phy_create(phy->dev, NULL, &pcie_ops);
-+	if (IS_ERR(generic_phy))
-+		return PTR_ERR(generic_phy);
-+
-+	phy_set_drvdata(generic_phy, phy);
-+
-+	ret = phy_pipe_clk_register(phy, generic_phy->id);
-+	if (ret)
-+		dev_err(&pdev->dev, "failed to register phy pipe clk\n");
-+
-+	phy_provider = devm_of_phy_provider_register(phy->dev,
-+						     of_phy_simple_xlate);
-+	if (IS_ERR(phy_provider))
-+		return PTR_ERR(phy_provider);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver qcom_uniphy_pcie_driver = {
-+	.probe		= qcom_uniphy_pcie_probe,
-+	.driver		= {
-+		.name	= "qcom-uniphy-pcie",
-+		.of_match_table = qcom_uniphy_pcie_id_table,
-+	},
-+};
-+
-+module_platform_driver(qcom_uniphy_pcie_driver);
-+
-+MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver");
-+MODULE_LICENSE("GPL");

target/linux/qualcommax/patches-6.6/0157-dt-bindings-phy-qcom-uniphy-pcie-add-IPQ5018-compatible.patch

@@ -1,25 +0,0 @@
-From: George Moussalem <[email protected]>
-Date: Tue, 07 Jan 2025 17:34:13 +0400
-Subject: [PATCH] phy: qualcomm: qcom-uniphy-pcie add IPQ5018 compatible
-
-The Qualcomm UNIPHY PCIe PHY 28lp part of the IPQ5332 SoC is also present on
-the IPQ5018 SoC, so adding the compatible for IPQ5018.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
-+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
-@@ -11,11 +11,12 @@ maintainers:
-   - Varadarajan Narayanan <[email protected]>
- 
- description:
--  PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
-+  PCIe and USB combo PHY found in Qualcomm IPQ5018 and IPQ5332 SoCs
- 
- properties:
-   compatible:
-     enum:
-+      - qcom,ipq5018-uniphy-pcie-phy
-       - qcom,ipq5332-uniphy-pcie-phy
- 
-   reg:

target/linux/qualcommax/patches-6.6/0158-phy-qcom-uniphy-pcie-28lp-add-support-for-IPQ5018.patch

@@ -1,77 +0,0 @@
-From: George Moussalem <[email protected]>
-Date: Tue, 07 Jan 2025 17:34:13 +0400
-Subject: [PATCH] phy: qualcomm: qcom-uniphy-pcie 28lp add support for IPQ5018
-
-The Qualcomm UNIPHY PCIe PHY 28lp is found on both IPQ5332 and IPQ5018.
-Adding the PHY init sequence, pipe clock rate, and compatible for IPQ5018.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
-+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
-@@ -76,6 +76,40 @@ struct qcom_uniphy_pcie {
- 
- #define phy_to_dw_phy(x)	container_of((x), struct qca_uni_pcie_phy, phy)
- 
-+static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = {
-+	{
-+		.offset = SSCG_CTRL_REG_4,
-+		.val = 0x1cb9,
-+	}, {
-+		.offset = SSCG_CTRL_REG_5,
-+		.val = 0x023a,
-+	}, {
-+		.offset = SSCG_CTRL_REG_3,
-+		.val = 0xd360,
-+	}, {
-+		.offset = SSCG_CTRL_REG_1,
-+		.val = 0x1,
-+	}, {
-+		.offset = SSCG_CTRL_REG_2,
-+		.val = 0xeb,
-+	}, {
-+		.offset = CDR_CTRL_REG_4,
-+		.val = 0x3f9,
-+	}, {
-+		.offset = CDR_CTRL_REG_5,
-+		.val = 0x1c9,
-+	}, {
-+		.offset = CDR_CTRL_REG_2,
-+		.val = 0x419,
-+	}, {
-+		.offset = CDR_CTRL_REG_1,
-+		.val = 0x200,
-+	}, {
-+		.offset = PCS_INTERNAL_CONTROL_2,
-+		.val = 0xf101,
-+	},
-+};
-+
- static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
- 	{
- 		.offset = PHY_CFG_PLLCFG,
-@@ -89,6 +123,14 @@ static const struct qcom_uniphy_pcie_reg
- 	},
- };
- 
-+static const struct qcom_uniphy_pcie_data ipq5018_data = {
-+	.lane_offset	= 0x800,
-+	.phy_type	= PHY_TYPE_PCIE_GEN2,
-+	.init_seq	= ipq5018_regs,
-+	.init_seq_num	= ARRAY_SIZE(ipq5018_regs),
-+	.pipe_clk_rate	= 125000000,
-+};
-+
- static const struct qcom_uniphy_pcie_data ipq5332_data = {
- 	.lane_offset	= 0x800,
- 	.phy_type	= PHY_TYPE_PCIE_GEN3,
-@@ -212,6 +254,9 @@ static inline int phy_pipe_clk_register(
- 
- static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
- 	{
-+		.compatible = "qcom,ipq5018-uniphy-pcie-phy",
-+		.data = &ipq5018_data,
-+	}, {
- 		.compatible = "qcom,ipq5332-uniphy-pcie-phy",
- 		.data = &ipq5332_data,
- 	}, {

target/linux/qualcommax/patches-6.6/0162-arm64-dts-qcom-ipq5018-Add-PCIe-related-nodes.patch

@@ -1,372 +0,0 @@
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-Date: Sat, 26 Apr 2025 12:47:20 +0400
-Subject: [PATCH v9 1/2] arm64: dts: qcom: ipq5018: Add PCIe related nodes
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-From: George Moussalem <[email protected]>
-
-From: Nitheesh Sekar <[email protected]>
-
-Add phy and controller nodes for a 2-lane Gen2 and
-a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
-one global interrupt.
-
-NOTE: the PCIe controller supports gen3, yet the phy is limited to gen2.
-
-Signed-off-by: Nitheesh Sekar <[email protected]>
-Signed-off-by: Sricharan R <[email protected]>
-Reviewed-by: Manivannan Sadhasivam <[email protected]>
-Reviewed-by: Dmitry Baryshkov <[email protected]>
-Reviewed-by: Konrad Dybcio <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 238 +++++++++++++++++++++++++++++++++-
- 1 file changed, 236 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -260,6 +260,40 @@
- 			#thermal-sensor-cells = <1>;
- 		};
- 
-+		pcie1_phy: phy@7e000 {
-+			compatible = "qcom,ipq5018-uniphy-pcie-phy";
-+			reg = <0x0007e000 0x800>;
-+
-+			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
-+
-+			resets = <&gcc GCC_PCIE1_PHY_BCR>,
-+				 <&gcc GCC_PCIE1PHY_PHY_BCR>;
-+
-+			#clock-cells = <0>;
-+			#phy-cells = <0>;
-+
-+			num-lanes = <1>;
-+
-+			status = "disabled";
-+		};
-+
-+		pcie0_phy: phy@86000 {
-+			compatible = "qcom,ipq5018-uniphy-pcie-phy";
-+			reg = <0x00086000 0x1000>;
-+
-+			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-+
-+			resets = <&gcc GCC_PCIE0_PHY_BCR>,
-+				 <&gcc GCC_PCIE0PHY_PHY_BCR>;
-+
-+			#clock-cells = <0>;
-+			#phy-cells = <0>;
-+
-+			num-lanes = <2>;
-+
-+			status = "disabled";
-+		};
-+
- 		tlmm: pinctrl@1000000 {
- 			compatible = "qcom,ipq5018-tlmm";
- 			reg = <0x01000000 0x300000>;
-@@ -283,8 +317,8 @@
- 			reg = <0x01800000 0x80000>;
- 			clocks = <&xo_board_clk>,
- 				 <&sleep_clk>,
--				 <0>,
--				 <0>,
-+				 <&pcie0_phy>,
-+				 <&pcie1_phy>,
- 				 <0>,
- 				 <0>,
- 				 <0>,
-@@ -501,6 +535,208 @@
- 				status = "disabled";
- 			};
- 		};
-+
-+		pcie1: pcie@80000000 {
-+			compatible = "qcom,pcie-ipq5018";
-+			reg = <0x80000000 0xf1d>,
-+			      <0x80000f20 0xa8>,
-+			      <0x80001000 0x1000>,
-+			      <0x00078000 0x3000>,
-+			      <0x80100000 0x1000>,
-+			      <0x0007b000 0x1000>;
-+			reg-names = "dbi",
-+				    "elbi",
-+				    "atu",
-+				    "parf",
-+				    "config",
-+				    "mhi";
-+			device_type = "pci";
-+			linux,pci-domain = <1>;
-+			bus-range = <0x00 0xff>;
-+			num-lanes = <1>;
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+
-+			/* The controller supports Gen3, but the connected PHY is Gen2-capable */
-+			max-link-speed = <2>;
-+
-+			phys = <&pcie1_phy>;
-+			phy-names ="pciephy";
-+
-+			ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>,
-+				 <0x02000000 0 0x80300000 0x80300000 0 0x10000000>;
-+
-+			msi-map = <0x0 &v2m0 0x0 0xff8>;
-+
-+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "msi0",
-+					  "msi1",
-+					  "msi2",
-+					  "msi3",
-+					  "msi4",
-+					  "msi5",
-+					  "msi6",
-+					  "msi7",
-+					  "global";
-+
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 0x7>;
-+			interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>,
-+					<0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>,
-+					<0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>,
-+					<0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>;
-+
-+			clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
-+				 <&gcc GCC_PCIE1_AXI_M_CLK>,
-+				 <&gcc GCC_PCIE1_AXI_S_CLK>,
-+				 <&gcc GCC_PCIE1_AHB_CLK>,
-+				 <&gcc GCC_PCIE1_AUX_CLK>,
-+				 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>;
-+			clock-names = "iface",
-+				      "axi_m",
-+				      "axi_s",
-+				      "ahb",
-+				      "aux",
-+				      "axi_bridge";
-+
-+			resets = <&gcc GCC_PCIE1_PIPE_ARES>,
-+				 <&gcc GCC_PCIE1_SLEEP_ARES>,
-+				 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
-+				 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
-+				 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
-+				 <&gcc GCC_PCIE1_AHB_ARES>,
-+				 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>,
-+				 <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>;
-+			reset-names = "pipe",
-+				      "sleep",
-+				      "sticky",
-+				      "axi_m",
-+				      "axi_s",
-+				      "ahb",
-+				      "axi_m_sticky",
-+				      "axi_s_sticky";
-+
-+			status = "disabled";
-+
-+			pcie@0 {
-+				device_type = "pci";
-+				reg = <0x0 0x0 0x0 0x0 0x0>;
-+				bus-range = <0x01 0xff>;
-+
-+				#address-cells = <3>;
-+				#size-cells = <2>;
-+				ranges;
-+			};
-+		};
-+
-+		pcie0: pcie@a0000000 {
-+			compatible = "qcom,pcie-ipq5018";
-+			reg = <0xa0000000 0xf1d>,
-+			      <0xa0000f20 0xa8>,
-+			      <0xa0001000 0x1000>,
-+			      <0x00080000 0x3000>,
-+			      <0xa0100000 0x1000>,
-+			      <0x00083000 0x1000>;
-+			reg-names = "dbi",
-+				    "elbi",
-+				    "atu",
-+				    "parf",
-+				    "config",
-+				    "mhi";
-+			device_type = "pci";
-+			linux,pci-domain = <0>;
-+			bus-range = <0x00 0xff>;
-+			num-lanes = <2>;
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+
-+			/* The controller supports Gen3, but the connected PHY is Gen2-capable */
-+			max-link-speed = <2>;
-+
-+			phys = <&pcie0_phy>;
-+			phy-names ="pciephy";
-+
-+			ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
-+				 <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
-+
-+			msi-map = <0x0 &v2m0 0x0 0xff8>;
-+
-+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "msi0",
-+					  "msi1",
-+					  "msi2",
-+					  "msi3",
-+					  "msi4",
-+					  "msi5",
-+					  "msi6",
-+					  "msi7",
-+					  "global";
-+
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 0x7>;
-+			interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
-+					<0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
-+					<0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
-+					<0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
-+
-+			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
-+				 <&gcc GCC_PCIE0_AXI_M_CLK>,
-+				 <&gcc GCC_PCIE0_AXI_S_CLK>,
-+				 <&gcc GCC_PCIE0_AHB_CLK>,
-+				 <&gcc GCC_PCIE0_AUX_CLK>,
-+				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
-+			clock-names = "iface",
-+				      "axi_m",
-+				      "axi_s",
-+				      "ahb",
-+				      "aux",
-+				      "axi_bridge";
-+
-+			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
-+				 <&gcc GCC_PCIE0_SLEEP_ARES>,
-+				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
-+				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
-+				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
-+				 <&gcc GCC_PCIE0_AHB_ARES>,
-+				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
-+				 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
-+			reset-names = "pipe",
-+				      "sleep",
-+				      "sticky",
-+				      "axi_m",
-+				      "axi_s",
-+				      "ahb",
-+				      "axi_m_sticky",
-+				      "axi_s_sticky";
-+
-+			status = "disabled";
-+
-+			pcie@0 {
-+				device_type = "pci";
-+				reg = <0x0 0x0 0x0 0x0 0x0>;
-+				bus-range = <0x01 0xff>;
-+
-+				#address-cells = <3>;
-+				#size-cells = <2>;
-+				ranges;
-+			};
-+		};
- 	};
- 
- 	thermal-zones {

target/linux/qualcommax/patches-6.6/0301-dt-bindings-mfd-qcom-tcsr-add-IPQ5018-compatible.patch

@@ -1,18 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] dt-bindings: mfd: qcom,tcsr: Add IPQ5018 compatible
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Document the qcom,tcsr-ipq5018 compatible.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
-+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
-@@ -33,6 +33,7 @@ properties:
-               - qcom,sm8450-tcsr
-               - qcom,tcsr-apq8064
-               - qcom,tcsr-apq8084
-+              - qcom,tcsr-ipq5018
-               - qcom,tcsr-ipq5332
-               - qcom,tcsr-ipq8064
-               - qcom,tcsr-ipq8074

target/linux/qualcommax/patches-6.6/0302-arm64-dts-qcom-IPQ5018-add-TCSR-node.patch

@@ -1,22 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add TCSR node
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add TCSR node.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -335,6 +335,11 @@
- 			#hwlock-cells = <1>;
- 		};
- 
-+		tcsr: syscon@1937000 {
-+			compatible = "qcom,tcsr-ipq5018", "syscon", "simple-mfd";
-+			reg = <0x01937000 0x21000>;
-+		};
-+
- 		sdhc_1: mmc@7804000 {
- 			compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
- 			reg = <0x7804000 0x1000>;

target/linux/qualcommax/patches-6.6/0303-arm64-dts-qcom-IPQ5018-enable-the-download-mode-support.patch

@@ -1,19 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: enable the download mode support
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-IPQ5018 also supports the download mode to collect the RAM dumps if system crashes, to perform
-the post mortem analysis. Add support for the same.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -82,6 +82,7 @@
- 		scm {
- 			compatible = "qcom,scm-ipq5018", "qcom,scm";
- 			qcom,sdi-enabled;
-+			qcom,dload-mode = <&tcsr 0x6100>;
- 		};
- 	};
- 

target/linux/qualcommax/patches-6.6/0304-dt-bindings-pwm-add-IPQ5018-compatible.patch

@@ -1,22 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] dt-bindings: mfd: qcom,tcsr: Add IPQ5018 compatible
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add compatible for IPQ5018.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml
-+++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml
-@@ -11,7 +11,10 @@ maintainers:
- 
- properties:
-   compatible:
--    const: qcom,ipq6018-pwm
-+    items:
-+      - enum:
-+          - qcom,ipq5018-pwm
-+      - const: qcom,ipq6018-pwm
- 
-   reg:
-     description: Offset of PWM register in the TCSR block.

target/linux/qualcommax/patches-6.6/0305-pinctrl-qcom-IPQ5018-update-pwm-groups.patch

@@ -1,65 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] pinctrl: qcom: IPQ5018: update pwm groups
-Date: Wed, 27 Nov 2024 09:14:11 +0400
-
-GPIO 1, 30, and 46 are used to control PWM1, PWM3, and PWM0 respectively which
-in turn drive the PWM led, so let's update the pwm# and pingroups accordingly.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c
-+++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
-@@ -541,7 +541,7 @@ static const char * const qdss_tracectl_
- };
- 
- static const char * const pwm0_groups[] = {
--	"gpio42",
-+	"gpio42", "gpio46",
- };
- 
- static const char * const qdss_cti_trig_out_b0_groups[] = {
-@@ -549,7 +549,7 @@ static const char * const qdss_cti_trig_
- };
- 
- static const char * const pwm1_groups[] = {
--	"gpio43",
-+	"gpio43", "gpio1",
- };
- 
- static const char * const qdss_cti_trig_in_b0_groups[] = {
-@@ -565,7 +565,7 @@ static const char * const qdss_cti_trig_
- };
- 
- static const char * const pwm3_groups[] = {
--	"gpio45",
-+	"gpio45", "gpio30",
- };
- 
- static const char * const qdss_cti_trig_in_b1_groups[] = {
-@@ -679,7 +679,7 @@ static const struct pinfunction ipq5018_
- 
- static const struct msm_pingroup ipq5018_groups[] = {
- 	PINGROUP(0, atest_char, _, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _),
--	PINGROUP(1, atest_char, _, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _),
-+	PINGROUP(1, atest_char, pwm1, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _),
- 	PINGROUP(2, atest_char, _, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _),
- 	PINGROUP(3, atest_char, _, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _),
- 	PINGROUP(4, sdc1_data, qspi_data, blsp1_spi1, btss, dbg_out, qdss_traceclk_a, _, burn0, _),
-@@ -708,7 +708,7 @@ static const struct msm_pingroup ipq5018
- 	PINGROUP(27, audio_txmclk, wsa_swrm, audio_txmclk, blsp2_spi, btss, _, qdss_tracedata_b, _, _),
- 	PINGROUP(28, audio_txbclk, wsa_swrm, blsp0_uart1, btss, qdss_tracedata_b, _, _, _, _),
- 	PINGROUP(29, audio_txfsync, _, blsp0_uart1, _, qdss_tracedata_b, _, _, _, _),
--	PINGROUP(30, audio_txd, led2, led0, _, _, _, _, _, _),
-+	PINGROUP(30, audio_txd, led2, led0, pwm3, _, _, _, _, _),
- 	PINGROUP(31, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
- 	PINGROUP(32, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),
- 	PINGROUP(33, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),
-@@ -724,7 +724,7 @@ static const struct msm_pingroup ipq5018
- 	PINGROUP(43, pwm1, qdss_cti_trig_in_b0, wci_txd, wci_rxd, xfem, _, _, _, _),
- 	PINGROUP(44, pwm2, qdss_cti_trig_out_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
- 	PINGROUP(45, pwm3, qdss_cti_trig_in_b1, wci_txd, wci_rxd, xfem, _, _, _, _),
--	PINGROUP(46, led0, _, _, _, _, _, _, _, _),
-+	PINGROUP(46, led0, pwm0, _, _, _, _, _, _, _),
- };
- 
- static const struct msm_pinctrl_soc_data ipq5018_pinctrl = {

target/linux/qualcommax/patches-6.6/0306-arm64-dts-qcom-ipq5018-Add-PWM-node.patch

@@ -1,27 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PWM node
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add PWM node.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -341,6 +341,16 @@
- 			reg = <0x01937000 0x21000>;
- 		};
- 
-+		pwm: pwm@1941010 {
-+			compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm";
-+			reg = <0x01941010 0x20>;
-+			clocks = <&gcc GCC_ADSS_PWM_CLK>;
-+			assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
-+			assigned-clock-rates = <100000000>;
-+			#pwm-cells = <2>;
-+			status = "disabled";
-+		};
-+
- 		sdhc_1: mmc@7804000 {
- 			compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
- 			reg = <0x7804000 0x1000>;

target/linux/qualcommax/patches-6.6/0324-arm64-dts-qcom-ipq5018-Add-crypto-nodes.patch

@@ -1,41 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add crypto nodes
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add dma controller and crypto nodes.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -295,6 +295,30 @@
- 			status = "disabled";
- 		};
- 
-+		cryptobam: dma-controller@704000 {
-+			compatible = "qcom,bam-v1.7.0";
-+			reg = <0x00704000 0x20000>;
-+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
-+			clock-names = "bam_clk";
-+			#dma-cells = <1>;
-+			qcom,ee = <1>;
-+			qcom,controlled-remotely;
-+			status = "disabled";
-+		};
-+
-+		crypto: crypto@73a000 {
-+			compatible = "qcom,crypto-v5.1";
-+			reg = <0x0073a000 0x6000>;
-+			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
-+				 <&gcc GCC_CRYPTO_AXI_CLK>,
-+				 <&gcc GCC_CRYPTO_CLK>;
-+			clock-names = "iface", "bus", "core";
-+			dmas = <&cryptobam 2>, <&cryptobam 3>;
-+			dma-names = "rx", "tx";
-+			status = "disabled";
-+		};
-+
- 		tlmm: pinctrl@1000000 {
- 			compatible = "qcom,ipq5018-tlmm";
- 			reg = <0x01000000 0x300000>;

target/linux/qualcommax/patches-6.6/0337-arm64-dts-qcom-ipq5018-Add-PRNG-node.patch

@@ -1,25 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PRNG node
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add PRNG node.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -222,6 +222,14 @@
- 			};
- 		};
- 
-+		prng: rng@e3000 {
-+			compatible = "qcom,prng-ee";
-+			reg = <0x000e3000 0x1000>;
-+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
-+			clock-names = "core";
-+			status = "disabled";
-+		};
-+
- 		tsens: thermal-sensor@4a9000 {
- 			compatible = "qcom,ipq5018-tsens";
- 			reg = <0x4a9000 0x1000>, /* TM */

target/linux/qualcommax/patches-6.6/0339-arm64-dts-qcom-ipq5018-Add-QUP1-UART2-node.patch

@@ -1,27 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add QUP1-UART2 node
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add QUP1-UART2 node.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -420,6 +420,16 @@
- 			status = "disabled";
- 		};
- 
-+		blsp1_uart2: serial@78b0000 {
-+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+			reg = <0x078b0000 0x200>;
-+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
-+					<&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
-+			status = "disabled";
-+		};
-+
- 		blsp1_spi1: spi@78b5000 {
- 			compatible = "qcom,spi-qup-v2.2.1";
- 			#address-cells = <1>;

target/linux/qualcommax/patches-6.6/0340-arm64-dts-qcom-ipq5018-Add-QUP3-I2C-node.patch

@@ -1,32 +0,0 @@
-From: George Moussalem <[email protected]>
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add QUP3 I2C node
-Date: Sun, 06 Oct 2024 16:34:11 +0400
-
-Add QUP3-I2C node.
-
-Signed-off-by: George Moussalem <[email protected]>
----
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -444,6 +444,21 @@
- 			status = "disabled";
- 		};
- 
-+		blsp1_i2c3: i2c@78b7000 {
-+			compatible = "qcom,i2c-qup-v2.2.1";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x078b7000 0x600>;
-+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
-+				 <&gcc GCC_BLSP1_AHB_CLK>;
-+			clock-names = "core", "iface";
-+			clock-frequency = <400000>;
-+			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
-+			dma-names = "tx", "rx";
-+			status = "disabled";
-+		};
-+
- 		usb: usb@8af8800 {
- 			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
- 			reg = <0x08af8800 0x400>;

target/linux/qualcommax/patches-6.6/0400-mtd-rawnand-add-support-for-TH58NYG3S0HBAI4.patch

@@ -1,42 +0,0 @@
-From 8d8b37d3af2bdccf0a37d2017d876bfc6ce42552 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <[email protected]>
-Date: Fri, 20 Oct 2023 23:18:21 +0800
-Subject: [PATCH 1/1] mtd: rawnand: add support for TH58NYG3S0HBAI4 NAND flash
-
-The Toshiba TH58NYG3S0HBAI4 is detected with 128 byte OOB while the flash
-has 256 bytes OOB. Since it is not an ONFI compliant NAND, the model name
-cannot be read from anywhere, add a static NAND ID entry to correct this.
-
-However, the NAND ID of this flash is inconsistent with the datasheet.
-The actual NAND ID is only 4 ID bytes, the last ID byte is missing.
-
-Datasheet available at (the ID table is on page 50):
-https://europe.kioxia.com/content/dam/kioxia/newidr/productinfo/datasheet/201910/DST_TH58NYG3S0HBAI4-TDE_EN_31565.pdf
-
-Datasheet NAND ID: {0x98, 0xa3, 0x91, 0x26, 0x76}
-Actual NAND ID: {0x98, 0xa3, 0x91, 0x26}
-
-It seems that this flash may be counterfeit, but another Toshiba flash
-also has the same problem. Maybe the driver has a bug, or some Toshiba
-nand flash is like this. Anyway, add a static NAND ID entry with only
-4 ID bytes as a hack to make sure it works.
-
-Tested on Arcadyan AW1000 flashed with OpenWrt.
-
-Signed-off-by: Chukun Pan <[email protected]>
----
- drivers/mtd/nand/raw/nand_ids.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/mtd/nand/raw/nand_ids.c
-+++ b/drivers/mtd/nand/raw/nand_ids.c
-@@ -58,6 +58,9 @@ struct nand_flash_dev nand_flash_ids[] =
- 		{ .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} },
- 		  SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664,
- 		  NAND_ECC_INFO(40, SZ_1K) },
-+	{"TH58NYG3S0HBAI4 8G 1.8V 8-bit", /* Last ID bytes missing */
-+		{ .id = {0x98, 0xa3, 0x91, 0x26} },
-+		  SZ_4K, SZ_1K, SZ_256K, 0, 4, 256, NAND_ECC_INFO(8, SZ_512) },
- 	{"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
- 		{ .id = {0x98, 0xdc, 0x91, 0x15, 0x76} },
- 		  SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) },

target/linux/qualcommax/patches-6.6/0401-spi-spi-qpic-snand-default-to-4-bit-ECC.patch

@@ -1,46 +0,0 @@
-From 2e1ab53e8fcf708db51f560f7846802d406ee57d Mon Sep 17 00:00:00 2001
-From: George Moussalem <[email protected]>
-Date: Thu, 15 May 2025 22:47:43 +0200
-Subject: [PATCH] spi: spi-qpic-snand: default to 4-bit ECC
-
-There are NAND IC-s that define 1-bit ECC as the minimal strength,
-however that is unsupported by QPIC-SNAND as it only supports 4 or 8 bit
-ECC.
-
-Since most of these chips also support 4-bit ECC just fine, instead of
-erroring out if 1-bit ECC is requested lets instead default to 4-bit ECC.
-
-Fixes: 01b72ce61e8f ("qualcommax: ipq50xx: remove ECC user config from board files")
-Signed-off-by: George Moussalem <[email protected]>
-Signed-off-by: Robert Marko <[email protected]>
----
- drivers/spi/spi-qpic-snand.c | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
---- a/drivers/spi/spi-qpic-snand.c
-+++ b/drivers/spi/spi-qpic-snand.c
-@@ -296,6 +296,24 @@ static int qcom_spi_ecc_init_ctx_pipelin
- 		ecc_cfg->spare_bytes = 2;
- 		break;
- 
-+	case 1:
-+	case 2:
-+		/*
-+		 * Many chips have set a minimum ECC strength requirement
-+		 * lower than 4-bits but also support higher strength, so
-+		 * check if ecc_cfg was set by chip reqs and try 4-bits.
-+		 */
-+		if (reqs->strength) {
-+			dev_warn(snandc->dev,
-+			         "ECC strength requirement of %u-bit(s) is unsupported, trying 4-bits\n",
-+			         reqs->strength);
-+			ecc_cfg->ecc_mode = ECC_MODE_4BIT;
-+			ecc_cfg->ecc_bytes_hw = 7;
-+			ecc_cfg->spare_bytes = 4;
-+			break;
-+		} else
-+			fallthrough;
-+
- 	default:
- 		dev_err(snandc->dev,
- 			"only 4 or 8 bits ECC strength is supported\n");

target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch

@@ -1,52 +0,0 @@
-From c2019f64539dd24e6e0da3cea2219d6f9e6b03e4 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:11 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq5018: Add SPI nand node
-
-Add SPI NAND support for IPQ5018 SoC.
-
-Signed-off-by: Ziyang Huang <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
- 1 file changed, 40 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -459,6 +459,36 @@
- 			status = "disabled";
- 		};
- 
-+		qpic_bam: dma@7984000 {
-+			compatible = "qcom,bam-v1.7.0";
-+			reg = <0x07984000 0x1c000>;
-+			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&gcc GCC_QPIC_AHB_CLK>;
-+			clock-names = "bam_clk";
-+			#dma-cells = <1>;
-+			qcom,ee = <0>;
-+			status = "disabled";
-+		};
-+
-+		qpic_nand: qpic-nand@79b0000 {
-+			compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand";
-+			reg = <0x079b0000 0x10000>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			clocks = <&gcc GCC_QPIC_CLK>,
-+				 <&gcc GCC_QPIC_AHB_CLK>,
-+				 <&gcc GCC_QPIC_IO_MACRO_CLK>;
-+			clock-names = "core", "aon", "iom";
-+
-+			dmas = <&qpic_bam 0>,
-+			       <&qpic_bam 1>,
-+			       <&qpic_bam 2>,
-+			       <&qpic_bam 3>;
-+			dma-names = "tx", "rx", "cmd", "status";
-+
-+			status = "disabled";
-+		};
-+
- 		usb: usb@8af8800 {
- 			compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
- 			reg = <0x08af8800 0x400>;

target/linux/qualcommax/patches-6.6/0701-dt-bindings-clock-qcom-Add-CMN-PLL-clock-controller-.patch

@@ -1,113 +0,0 @@
-From 7b89dbf5c7dcd8a9c131721e93c1292e5993968b Mon Sep 17 00:00:00 2001
-From: Luo Jie <[email protected]>
-Date: Tue, 20 Aug 2024 22:02:42 +0800
-Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL clock controller
- for IPQ SoC
-
-The CMN PLL controller provides clocks to networking hardware blocks
-on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi,
-and produces output clocks at fixed rates. These output rates are
-predetermined, and are unrelated to the input clock rate. The output
-clocks are supplied to the Ethernet hardware such as PPE (packet
-process engine) and the externally connected switch or PHY device.
-
-Signed-off-by: Luo Jie <[email protected]>
-Reviewed-by: Krzysztof Kozlowski <[email protected]>
----
- .../bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 70 +++++++++++++++++++
- include/dt-bindings/clock/qcom,ipq-cmn-pll.h  | 15 ++++
- 2 files changed, 85 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
- create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
-@@ -0,0 +1,70 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Qualcomm CMN PLL Clock Controller on IPQ SoC
-+
-+maintainers:
-+  - Bjorn Andersson <[email protected]>
-+  - Luo Jie <[email protected]>
-+
-+description:
-+  The CMN PLL clock controller expects a reference input clock.
-+  This reference clock is from the on-board Wi-Fi. The CMN PLL
-+  supplies a number of fixed rate output clocks to the Ethernet
-+  devices including PPE (packet process engine) and the connected
-+  switch or PHY device.
-+
-+properties:
-+  compatible:
-+    enum:
-+      - qcom,ipq9574-cmn-pll
-+
-+  reg:
-+    maxItems: 1
-+
-+  clocks:
-+    items:
-+      - description: The reference clock. The supported clock rates include
-+          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
-+      - description: The AHB clock
-+      - description: The SYS clock
-+    description:
-+      The reference clock is the source clock of CMN PLL, which is from the
-+      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
-+      clock registers.
-+
-+  clock-names:
-+    items:
-+      - const: ref
-+      - const: ahb
-+      - const: sys
-+
-+  "#clock-cells":
-+    const: 1
-+
-+required:
-+  - compatible
-+  - reg
-+  - clocks
-+  - clock-names
-+  - "#clock-cells"
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
-+
-+    clock-controller@9b000 {
-+        compatible = "qcom,ipq9574-cmn-pll";
-+        reg = <0x0009b000 0x800>;
-+        clocks = <&cmn_pll_ref_clk>,
-+                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
-+                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
-+        clock-names = "ref", "ahb", "sys";
-+        #clock-cells = <1>;
-+    };
-+...
---- /dev/null
-+++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
-+#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
-+
-+/* The output clocks from CMN PLL of IPQ9574. */
-+#define PPE_353MHZ_CLK			0
-+#define ETH0_50MHZ_CLK			1
-+#define ETH1_50MHZ_CLK			2
-+#define ETH2_50MHZ_CLK			3
-+#define ETH_25MHZ_CLK			4
-+#endif

target/linux/qualcommax/patches-6.6/0702-clk-qcom-Add-CMN-PLL-clock-controller-driver-for-IPQ.patch

@@ -1,288 +0,0 @@
-From a7e8397e2db6133e3435054a3f312dbd9cab05ed Mon Sep 17 00:00:00 2001
-From: Luo Jie <[email protected]>
-Date: Tue, 20 Aug 2024 22:02:43 +0800
-Subject: [PATCH] clk: qcom: Add CMN PLL clock controller driver for IPQ
- SoC
-
-The CMN PLL clock controller supplies clocks to the hardware
-blocks that together make up the Ethernet function on Qualcomm
-IPQ SoCs. The driver is initially supported for IPQ9574 SoC.
-
-The CMN PLL clock controller expects a reference input clock
-from the on-board Wi-Fi block acting as clock source. The input
-reference clock needs to be configured to one of the supported
-clock rates.
-
-The controller supplies a number of fixed-rate output clocks.
-For the IPQ9574, there is one output clock of 353 MHZ to PPE
-(Packet Process Engine) hardware block, three 50 MHZ output
-clocks and an additional 25 MHZ output clock supplied to the
-connected Ethernet devices.
-
-Signed-off-by: Luo Jie <[email protected]>
----
- drivers/clk/qcom/Kconfig           |  10 ++
- drivers/clk/qcom/Makefile          |   1 +
- drivers/clk/qcom/clk-ipq-cmn-pll.c | 227 +++++++++++++++++++++++++++++
- 3 files changed, 238 insertions(+)
- create mode 100644 drivers/clk/qcom/clk-ipq-cmn-pll.c
-
---- a/drivers/clk/qcom/Kconfig
-+++ b/drivers/clk/qcom/Kconfig
-@@ -139,6 +139,16 @@ config IPQ_APSS_6018
- 	  Say Y if you want to support CPU frequency scaling on
- 	  ipq based devices.
- 
-+config IPQ_CMN_PLL
-+	tristate "IPQ CMN PLL Clock Controller"
-+	depends on IPQ_GCC_9574
-+	help
-+	  Support for CMN PLL clock controller on IPQ platform. The
-+	  CMN PLL feeds the reference clocks to the Ethernet devices
-+	  based on IPQ SoC.
-+	  Say Y or M if you want to support CMN PLL clock on the IPQ
-+	  based devices.
-+
- config IPQ_GCC_4019
- 	tristate "IPQ4019 Global Clock Controller"
- 	help
---- a/drivers/clk/qcom/Makefile
-+++ b/drivers/clk/qcom/Makefile
-@@ -23,6 +23,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8
- obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
- obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
- obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
-+obj-$(CONFIG_IPQ_CMN_PLL) += clk-ipq-cmn-pll.o
- obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
- obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
- obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
---- /dev/null
-+++ b/drivers/clk/qcom/clk-ipq-cmn-pll.c
-@@ -0,0 +1,227 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
-+ */
-+
-+/*
-+ * CMN PLL block expects the reference clock from on-board Wi-Fi block, and
-+ * supplies fixed rate clocks as output to the Ethernet hardware blocks.
-+ * The Ethernet related blocks include PPE (packet process engine) and the
-+ * external connected PHY (or switch) chip receiving clocks from the CMN PLL.
-+ *
-+ * On the IPQ9574 SoC, There are three clocks with 50 MHZ, one clock with
-+ * 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
-+ * and one clock with 353 MHZ to PPE.
-+ *
-+ *               +---------+
-+ *               |   GCC   |
-+ *               +--+---+--+
-+ *           AHB CLK|   |SYS CLK
-+ *                  V   V
-+ *          +-------+---+------+
-+ *          |                  +-------------> eth0-50mhz
-+ * REF CLK  |     IPQ9574      |
-+ * -------->+                  +-------------> eth1-50mhz
-+ *          |  CMN PLL block   |
-+ *          |                  +-------------> eth2-50mhz
-+ *          |                  |
-+ *          +---------+--------+-------------> eth-25mhz
-+ *                    |
-+ *                    V
-+ *                    ppe-353mhz
-+ */
-+
-+#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
-+#include <linux/bitfield.h>
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+
-+#define CMN_PLL_REFCLK_SRC_SELECTION		0x28
-+#define CMN_PLL_REFCLK_SRC_DIV			GENMASK(9, 8)
-+
-+#define CMN_PLL_REFCLK_CONFIG			0x784
-+#define CMN_PLL_REFCLK_EXTERNAL			BIT(9)
-+#define CMN_PLL_REFCLK_DIV			GENMASK(8, 4)
-+#define CMN_PLL_REFCLK_INDEX			GENMASK(3, 0)
-+
-+#define CMN_PLL_POWER_ON_AND_RESET		0x780
-+#define CMN_ANA_EN_SW_RSTN			BIT(6)
-+
-+/**
-+ * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information
-+ * @id:	Clock specifier to be supplied
-+ * @name: Clock name to be registered
-+ * @rate: Clock rate
-+ */
-+struct cmn_pll_fixed_output_clk {
-+	unsigned int		id;
-+	const char		*name;
-+	const unsigned long	rate;
-+};
-+
-+#define CLK_PLL_OUTPUT(_id, _name, _rate) {		\
-+	.id = _id,					\
-+	.name = _name,					\
-+	.rate = _rate,					\
-+}
-+
-+static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = {
-+	CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),
-+	CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
-+	CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
-+	CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
-+	CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
-+};
-+
-+static int ipq_cmn_pll_config(struct device *dev, unsigned long parent_rate)
-+{
-+	void __iomem *base;
-+	u32 val;
-+
-+	base = devm_of_iomap(dev, dev->of_node, 0, NULL);
-+	if (IS_ERR(base))
-+		return PTR_ERR(base);
-+
-+	val = readl(base + CMN_PLL_REFCLK_CONFIG);
-+	val &= ~(CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_INDEX);
-+
-+	/*
-+	 * Configure the reference input clock selection as per the given rate.
-+	 * The output clock rates are always of fixed value.
-+	 */
-+	switch (parent_rate) {
-+	case 25000000:
-+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3);
-+		break;
-+	case 31250000:
-+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4);
-+		break;
-+	case 40000000:
-+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6);
-+		break;
-+	case 48000000:
-+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
-+		break;
-+	case 50000000:
-+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8);
-+		break;
-+	case 96000000:
-+		val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
-+		val &= ~CMN_PLL_REFCLK_DIV;
-+		val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	writel(val, base + CMN_PLL_REFCLK_CONFIG);
-+
-+	/* Update the source clock rate selection. Only 96 MHZ uses 0. */
-+	val = readl(base + CMN_PLL_REFCLK_SRC_SELECTION);
-+	val &= ~CMN_PLL_REFCLK_SRC_DIV;
-+	if (parent_rate != 96000000)
-+		val |= FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 1);
-+
-+	writel(val, base + CMN_PLL_REFCLK_SRC_SELECTION);
-+
-+	/*
-+	 * Reset the CMN PLL block by asserting/de-asserting for 100 ms
-+	 * each, to ensure the updated configurations take effect.
-+	 */
-+	val = readl(base + CMN_PLL_POWER_ON_AND_RESET);
-+	val &= ~CMN_ANA_EN_SW_RSTN;
-+	writel(val, base);
-+	msleep(100);
-+
-+	val |= CMN_ANA_EN_SW_RSTN;
-+	writel(val, base + CMN_PLL_POWER_ON_AND_RESET);
-+	msleep(100);
-+
-+	return 0;
-+}
-+
-+static int ipq_cmn_pll_clk_register(struct device *dev, const char *parent)
-+{
-+	const struct cmn_pll_fixed_output_clk *fixed_clk;
-+	struct clk_hw_onecell_data *data;
-+	unsigned int num_clks;
-+	struct clk_hw *hw;
-+	int i;
-+
-+	num_clks = ARRAY_SIZE(ipq9574_output_clks);
-+	fixed_clk = ipq9574_output_clks;
-+
-+	data = devm_kzalloc(dev, struct_size(data, hws, num_clks), GFP_KERNEL);
-+	if (!data)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < num_clks; i++) {
-+		hw = devm_clk_hw_register_fixed_rate(dev, fixed_clk[i].name,
-+						     parent, 0,
-+						     fixed_clk[i].rate);
-+		if (IS_ERR(hw))
-+			return PTR_ERR(hw);
-+
-+		data->hws[fixed_clk[i].id] = hw;
-+	}
-+	data->num = num_clks;
-+
-+	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
-+}
-+
-+static int ipq_cmn_pll_clk_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct clk *clk;
-+	int ret;
-+
-+	/*
-+	 * To access the CMN PLL registers, the GCC AHB & SYSY clocks
-+	 * for CMN PLL block need to be enabled.
-+	 */
-+	clk = devm_clk_get_enabled(dev, "ahb");
-+	if (IS_ERR(clk))
-+		return dev_err_probe(dev, PTR_ERR(clk),
-+				     "Enable AHB clock failed\n");
-+
-+	clk = devm_clk_get_enabled(dev, "sys");
-+	if (IS_ERR(clk))
-+		return dev_err_probe(dev, PTR_ERR(clk),
-+				     "Enable SYS clock failed\n");
-+
-+	clk = devm_clk_get(dev, "ref");
-+	if (IS_ERR(clk))
-+		return dev_err_probe(dev, PTR_ERR(clk),
-+				     "Get reference clock failed\n");
-+
-+	/* Configure CMN PLL to apply the reference clock. */
-+	ret = ipq_cmn_pll_config(dev, clk_get_rate(clk));
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Configure CMN PLL failed\n");
-+
-+	return ipq_cmn_pll_clk_register(dev, __clk_get_name(clk));
-+}
-+
-+static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
-+	{ .compatible = "qcom,ipq9574-cmn-pll", },
-+	{ }
-+};
-+
-+static struct platform_driver ipq_cmn_pll_clk_driver = {
-+	.probe = ipq_cmn_pll_clk_probe,
-+	.driver = {
-+		.name = "ipq_cmn_pll",
-+		.of_match_table = ipq_cmn_pll_clk_ids,
-+	},
-+};
-+
-+module_platform_driver(ipq_cmn_pll_clk_driver);
-+
-+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver");
-+MODULE_LICENSE("GPL");

target/linux/qualcommax/patches-6.6/0703-clk-qcom-cmn-pll-add-IPQ5018-support.patch

@@ -1,78 +0,0 @@
-From a28797563b8c97c9abced82e0cf89302fcd2bf37 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:11 +0800
-Subject: [PATCH 1/2] clk: qcom: cmn-pll: add IPQ5018 support
-
-Add support for IPQ5018 (and removing dependency on the IPQ9574 platform).
-The common network block in IPQ5018 must be enabled first through a 
-specific register at a fixed offset in the TCSR area, set in the DTS.
-
-Signed-off-by: Ziyang Huang <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- drivers/clk/qcom/Kconfig           |  1 -
- drivers/clk/qcom/clk-ipq-cmn-pll.c | 29 +++++++++++++++++++++++++++++
- 2 files changed, 29 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/Kconfig
-+++ b/drivers/clk/qcom/Kconfig
-@@ -141,7 +141,6 @@ config IPQ_APSS_6018
- 
- config IPQ_CMN_PLL
- 	tristate "IPQ CMN PLL Clock Controller"
--	depends on IPQ_GCC_9574
- 	help
- 	  Support for CMN PLL clock controller on IPQ platform. The
- 	  CMN PLL feeds the reference clocks to the Ethernet devices
---- a/drivers/clk/qcom/clk-ipq-cmn-pll.c
-+++ b/drivers/clk/qcom/clk-ipq-cmn-pll.c
-@@ -42,6 +42,9 @@
- #include <linux/platform_device.h>
- #include <linux/slab.h>
- 
-+#define TCSR_ETH_CMN				0x0
-+#define  TCSR_ETH_CMN_ENABLE			BIT(0)
-+
- #define CMN_PLL_REFCLK_SRC_SELECTION		0x28
- #define CMN_PLL_REFCLK_SRC_DIV			GENMASK(9, 8)
- 
-@@ -79,6 +82,28 @@ static const struct cmn_pll_fixed_output
- 	CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
- };
- 
-+static int ipq_cmn_pll_tcsr_enable(struct platform_device *pdev)
-+{
-+	struct resource *res;
-+	void __iomem *tcsr_base;
-+	u32 val;
-+
-+	/* For IPQ50xx, tcsr is necessary to enable cmn block */
-+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tcsr");
-+	if (!res)
-+		return 0;
-+
-+	tcsr_base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR_OR_NULL(tcsr_base))
-+		return PTR_ERR(tcsr_base);
-+
-+	val = readl(tcsr_base + TCSR_ETH_CMN);
-+	val |= TCSR_ETH_CMN_ENABLE;
-+	writel(val, (tcsr_base + TCSR_ETH_CMN));
-+
-+	return 0;
-+}
-+
- static int ipq_cmn_pll_config(struct device *dev, unsigned long parent_rate)
- {
- 	void __iomem *base;
-@@ -181,6 +206,10 @@ static int ipq_cmn_pll_clk_probe(struct
- 	struct clk *clk;
- 	int ret;
- 
-+	ret = ipq_cmn_pll_tcsr_enable(pdev);
-+	if (ret)
-+		return dev_err_probe(dev, ret, "Enable CMN PLL failed\n");
-+
- 	/*
- 	 * To access the CMN PLL registers, the GCC AHB & SYSY clocks
- 	 * for CMN PLL block need to be enabled.

target/linux/qualcommax/patches-6.6/0704-arm64-dts-qcom-ipq5018-Add-ethernet-cmn-node.patch

@@ -1,45 +0,0 @@
-From 1b625a37b96b0448aac126d7720eec38de8e5956 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:11 +0800
-Subject: [PATCH 2/2] arm64: dts: qcom: ipq5018: Add ethernet cmn node
-
-Signed-off-by: Ziyang Huang <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -16,6 +16,12 @@
- 	#size-cells = <2>;
- 
- 	clocks {
-+		cmn_pll_ref_clk: cmn-pll-ref-clk {
-+			compatible = "fixed-clock";
-+			clock-frequency = <96000000>;
-+			#clock-cells = <0>;
-+		};
-+
- 		sleep_clk: sleep-clk {
- 			compatible = "fixed-clock";
- 			#clock-cells = <0>;
-@@ -150,6 +156,19 @@
- 			status = "disabled";
- 		};
- 
-+		cmn_pll: clock-controller@9b000 {
-+			compatible = "qcom,ipq9574-cmn-pll";
-+			reg = <0x0009b000 0x800>,
-+			      <0x19475c4 0x4>;
-+			reg-names = "cmn",
-+				    "tcsr";
-+			clocks = <&cmn_pll_ref_clk>,
-+				 <&gcc GCC_CMN_BLK_AHB_CLK>,
-+				 <&gcc GCC_CMN_BLK_SYS_CLK>;
-+			clock-names = "ref", "ahb", "sys";
-+			#clock-cells = <1>;
-+		};
-+
- 		qfprom: qfprom@a0000 {
- 			compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
- 			reg = <0xa0000 0x1000>;

target/linux/qualcommax/patches-6.6/0711-net-phy-qcom-Introduce-IPQ5018-internal-PHY-driver.patch

@@ -1,184 +0,0 @@
-From 77ad12b3a5e21cae859247c0b82cf9a5b661e531 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:11 +0800
-Subject: [PATCH 1/3] net: phy: qcom: Introduce IPQ5018 internal PHY driver
-
-Introduce the internal GE PHY driver, part of the Qualcomm IPQ50xx SoC.
-The driver registers two clock providers needed and referenced by the GCC 
-using DT properties and phandles.
-
-Signed-off-by: Ziyang Huang <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- drivers/net/phy/qcom/Kconfig   |   6 ++
- drivers/net/phy/qcom/Makefile  |   1 +
- drivers/net/phy/qcom/ipq5018.c | 138 +++++++++++++++++++++++++++++++++
- 3 files changed, 145 insertions(+)
- create mode 100644 drivers/net/phy/qcom/ipq5018.c
-
---- a/drivers/net/phy/qcom/Kconfig
-+++ b/drivers/net/phy/qcom/Kconfig
-@@ -9,6 +9,12 @@ config AT803X_PHY
- 	help
- 	  Currently supports the AR8030, AR8031, AR8033, AR8035 model
- 
-+config IPQ5018_PHY
-+	tristate "Qualcomm IPQ5018 internal PHYs"
-+	select QCOM_NET_PHYLIB
-+	help
-+	  Currently supports the Qualcomm IPQ5018 internal PHY
-+
- config QCA83XX_PHY
- 	tristate "Qualcomm Atheros QCA833x PHYs"
- 	select QCOM_NET_PHYLIB
---- a/drivers/net/phy/qcom/Makefile
-+++ b/drivers/net/phy/qcom/Makefile
-@@ -1,6 +1,7 @@
- # SPDX-License-Identifier: GPL-2.0
- obj-$(CONFIG_QCOM_NET_PHYLIB)	+= qcom-phy-lib.o
- obj-$(CONFIG_AT803X_PHY)	+= at803x.o
-+obj-$(CONFIG_IPQ5018_PHY)	+= ipq5018.o
- obj-$(CONFIG_QCA83XX_PHY)	+= qca83xx.o
- obj-$(CONFIG_QCA808X_PHY)	+= qca808x.o
- obj-$(CONFIG_QCA807X_PHY)	+= qca807x.o
---- /dev/null
-+++ b/drivers/net/phy/qcom/ipq5018.c
-@@ -0,0 +1,138 @@
-+#include <linux/bitfield.h>
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/phy.h>
-+#include <linux/reset.h>
-+
-+#include "qcom.h"
-+
-+#define IPQ5018_PHY_ID			0x004dd0c0
-+
-+#define TX_RX_CLK_RATE			125000000 /* 125M */
-+
-+#define IPQ5018_PHY_FIFO_CONTROL	0x19
-+#define  IPQ5018_PHY_FIFO_RESET		GENMASK(1, 0)
-+
-+struct ipq5018_phy {
-+	int num_clks;
-+	struct clk_bulk_data *clks;
-+	struct reset_control *rst;
-+
-+	struct clk_hw *clk_rx, *clk_tx;
-+	struct clk_hw_onecell_data *clk_data;
-+};
-+
-+static int ipq5018_probe(struct phy_device *phydev)
-+{
-+	struct ipq5018_phy *priv;
-+	struct device *dev = &phydev->mdio.dev;
-+	char name[64];
-+	int ret;
-+
-+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return dev_err_probe(dev, -ENOMEM,
-+				     "failed to allocate priv\n");
-+
-+	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
-+	if (priv->num_clks < 0)
-+		return dev_err_probe(dev, priv->num_clks,
-+				     "failed to acquire clocks\n");
-+
-+	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
-+	if (ret)
-+		return dev_err_probe(dev, ret,
-+				     "failed to enable clocks\n");
-+
-+	priv->rst = devm_reset_control_array_get_exclusive(dev);
-+	if (IS_ERR_OR_NULL(priv->rst))
-+		return dev_err_probe(dev, PTR_ERR(priv->rst),
-+				     "failed to acquire reset\n");
-+
-+	ret = reset_control_reset(priv->rst);
-+	if (ret)
-+		return dev_err_probe(dev, ret,
-+				     "failed to reset\n");
-+
-+	snprintf(name, sizeof(name), "%s#rx", dev_name(dev));
-+	priv->clk_rx = clk_hw_register_fixed_rate(dev, name, NULL, 0,
-+						  TX_RX_CLK_RATE);
-+	if (IS_ERR_OR_NULL(priv->clk_rx))
-+		return dev_err_probe(dev, PTR_ERR(priv->clk_rx),
-+				     "failed to register rx clock\n");
-+
-+	snprintf(name, sizeof(name), "%s#tx", dev_name(dev));
-+	priv->clk_tx = clk_hw_register_fixed_rate(dev, name, NULL, 0,
-+						  TX_RX_CLK_RATE);
-+	if (IS_ERR_OR_NULL(priv->clk_tx))
-+		return dev_err_probe(dev, PTR_ERR(priv->clk_tx),
-+				     "failed to register tx clock\n");
-+
-+	priv->clk_data = devm_kzalloc(dev,
-+				      struct_size(priv->clk_data, hws, 2),
-+				      GFP_KERNEL);
-+	if (!priv->clk_data)
-+		return dev_err_probe(dev, -ENOMEM,
-+				     "failed to allocate clk_data\n");
-+
-+	priv->clk_data->num = 2;
-+	priv->clk_data->hws[0] = priv->clk_rx;
-+	priv->clk_data->hws[1] = priv->clk_tx;
-+	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
-+				     priv->clk_data);
-+	if (ret)
-+		return dev_err_probe(dev, ret,
-+				     "fail to register clock provider\n");
-+
-+	return 0;
-+}
-+
-+static int ipq5018_soft_reset(struct phy_device *phydev)
-+{
-+	int ret;
-+
-+	ret = phy_modify(phydev, IPQ5018_PHY_FIFO_CONTROL,
-+			 IPQ5018_PHY_FIFO_RESET, 0);
-+	if (ret < 0)
-+		return ret;
-+
-+	msleep(50);
-+
-+	ret = phy_modify(phydev, IPQ5018_PHY_FIFO_CONTROL,
-+			 IPQ5018_PHY_FIFO_RESET, IPQ5018_PHY_FIFO_RESET);
-+	if (ret < 0)
-+		return ret;
-+
-+	return 0;
-+}
-+
-+static int ipq5018_cable_test_start(struct phy_device *phydev)
-+{
-+	/* we do all the (time consuming) work later */
-+	return 0;
-+}
-+
-+static struct phy_driver ipq5018_internal_phy_driver[] = {
-+	{
-+		PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID),
-+		.name		= "Qualcomm IPQ5018 internal PHY",
-+		.flags		= PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST,
-+		.probe		= ipq5018_probe,
-+		.soft_reset	= ipq5018_soft_reset,
-+		.read_status	= at803x_read_status,
-+		.config_intr	= at803x_config_intr,
-+		.handle_interrupt = at803x_handle_interrupt,
-+		.cable_test_start	= ipq5018_cable_test_start,
-+		.cable_test_get_status	= qca808x_cable_test_get_status,
-+	},
-+};
-+module_phy_driver(ipq5018_internal_phy_driver);
-+
-+static struct mdio_device_id __maybe_unused ipq5018_internal_phy_ids[] = {
-+	{ PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(mdio, ipq5018_internal_phy_ids);
-+
-+MODULE_DESCRIPTION("Qualcomm IPQ5018 internal PHY driver");
-+MODULE_AUTHOR("Ziyang Huang <[email protected]>");

target/linux/qualcommax/patches-6.6/0712-arm64-dts-qcom-ipq5018-add-mdio-node.patch

@@ -1,47 +0,0 @@
-From d2cdc83fb2c7360856e598810b88211d815fc851 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <[email protected]>
-Date: Sun, 8 Sep 2024 16:40:12 +0800
-Subject: [PATCH 2/3] arm64: dts: qcom: ipq5018: add mdio node
-
-The IPQ5018 SoC contains two MDIO controllers. MDIO0 is used to control 
-its internal GE Phy, while MDIO1 is wired to external PHYs/switch.
-
-Signed-off-by: Ziyang Huang <[email protected]>
-Signed-off-by: George Moussalem <[email protected]>
----
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -156,6 +156,30 @@
- 			status = "disabled";
- 		};
- 
-+		mdio0: mdio@88000 {
-+			compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio";
-+			reg = <0x00088000 0x64>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			clocks = <&gcc GCC_MDIO0_AHB_CLK>;
-+			clock-names = "gcc_mdio_ahb_clk";
-+
-+			status = "disabled";
-+		};
-+
-+		mdio1: mdio@90000 {
-+			compatible = "qcom,ipq5018-mdio";
-+			reg = <0x00090000 0x64>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			clocks = <&gcc GCC_MDIO1_AHB_CLK>;
-+			clock-names = "gcc_mdio_ahb_clk";
-+
-+			status = "disabled";
-+		};
-+
- 		cmn_pll: clock-controller@9b000 {
- 			compatible = "qcom,ipq9574-cmn-pll";
- 			reg = <0x0009b000 0x800>,