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@@ -0,0 +1,196 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+
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+#include <linux/clockchips.h>
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+#include <linux/init.h>
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+#include <asm/time.h>
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+#include <linux/interrupt.h>
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+#include <linux/of_address.h>
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+#include <linux/of_irq.h>
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+#include <linux/sched_clock.h>
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+#include "timer-of.h"
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+
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+#include <mach-rtl83xx.h>
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+
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+/*
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+ * Timer registers
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+ * the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart
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+ */
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+#define RTL9300_TC_DATA 0x0
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+#define RTL9300_TC_CNT 0x4
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+#define RTL9300_TC_CTRL 0x8
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+#define RTL9300_TC_CTRL_MODE BIT(24)
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+#define RTL9300_TC_CTRL_EN BIT(28)
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+#define RTL9300_TC_INT 0xc
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+#define RTL9300_TC_INT_IP BIT(16)
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+#define RTL9300_TC_INT_IE BIT(20)
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+
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+// Clocksource is using timer 0, clock event uses timer 1
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+#define TIMER_CLK_SRC 0
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+#define TIMER_CLK_EVT 1
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+#define TIMER_BLK_EVT (TIMER_CLK_EVT << 4)
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+
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+// Timer modes
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+#define TIMER_MODE_REPEAT 1
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+#define TIMER_MODE_ONCE 0
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+
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+// Minimum divider is 2
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+#define DIVISOR_RTL9300 2
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+
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+#define N_BITS 28
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+
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+static void __iomem *rtl9300_sched_reg __read_mostly;
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+
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+static u64 notrace rtl9300_sched_clock_read(void)
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+{
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+/* pr_info("In %s: %x\n", __func__, readl_relaxed(rtl9300_sched_reg));
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+ dump_stack();*/
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+ return readl_relaxed(rtl9300_sched_reg);
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+}
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+
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+static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id)
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+{
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+ struct clock_event_device *clk = dev_id;
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+ struct timer_of *to = to_timer_of(clk);
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+ u32 v = readl(timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
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+
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+ // Acknowledge the IRQ
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+ v |= RTL9300_TC_INT_IP;
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+ writel(v, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
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+
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+ clk->event_handler(clk);
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+ return IRQ_HANDLED;
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+}
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+
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+static void rtl9300_timer_stop(struct timer_of *to)
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+{
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+ u32 v;
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+
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+ writel(0, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_CTRL);
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+
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+ // Acknowledge possibly pending IRQ
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+ v = readl(timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
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+ if (v & RTL9300_TC_INT_IP)
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+ writel(v, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
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+}
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+
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+static void rtl9300_timer_start(struct timer_of *to, int timer, bool periodic)
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+{
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+ u32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300;
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+ writel(v, timer_of_base(to) + timer * 0x10 + RTL9300_TC_CTRL);
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+}
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+
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+static int rtl9300_set_next_event(unsigned long delta, struct clock_event_device *clk)
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+{
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+ struct timer_of *to = to_timer_of(clk);
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+
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+ rtl9300_timer_stop(to);
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+ writel(delta, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
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+ rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_ONCE);
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+ return 0;
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+}
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+
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+static int rtl9300_set_state_periodic(struct clock_event_device *clk)
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+{
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+ struct timer_of *to = to_timer_of(clk);
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+
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+ rtl9300_timer_stop(to);
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+ writel(to->of_clk.period, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
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+ rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_REPEAT);
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+ return 0;
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+}
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+
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+static int rtl9300_set_state_oneshot(struct clock_event_device *clk)
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+{
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+ struct timer_of *to = to_timer_of(clk);
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+
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+ rtl9300_timer_stop(to);
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+ writel(to->of_clk.period, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
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+ rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_ONCE);
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+ return 0;
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+}
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+
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+static int rtl9300_set_state_shutdown(struct clock_event_device *clk)
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+{
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+ struct timer_of *to = to_timer_of(clk);
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+
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+ rtl9300_timer_stop(to);
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+ return 0;
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+}
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+
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+static struct timer_of t_of = {
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+ .flags = TIMER_OF_BASE | TIMER_OF_IRQ | TIMER_OF_CLOCK,
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+
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+ .clkevt = {
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+ .name = "rtl9300_timer",
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+ .rating = 350,
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+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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+ .set_next_event = rtl9300_set_next_event,
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+ .set_state_oneshot = rtl9300_set_state_oneshot,
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+ .set_state_periodic = rtl9300_set_state_periodic,
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+ .set_state_shutdown = rtl9300_set_state_shutdown,
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+ },
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+
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+ .of_irq = {
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+ .name = "ostimer",
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+ .handler = rtl9300_timer_interrupt,
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+ .flags = IRQF_TIMER,
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+ },
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+};
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+
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+static void __init rtl9300_timer_setup(u8 timer)
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+{
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+ u32 v;
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+
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+ // Disable timer
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+ writel(0, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_CTRL);
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+
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+ // Acknowledge possibly pending IRQ
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+ v = readl(timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_INT);
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+ if (v & RTL9300_TC_INT_IP)
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+ writel(v, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_INT);
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+
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+ // Setup maximum period (for use as clock-source)
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+ writel(0x0fffffff, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_DATA);
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+}
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+
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+
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+static int __init rtl9300_timer_init(struct device_node *node)
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+{
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+ int err = 0;
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+ unsigned long rate;
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+
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+ pr_info("%s: setting up timer\n", __func__);
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+
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+ err = timer_of_init(node, &t_of);
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+ if (err)
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+ return err;
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+
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+ rate = timer_of_rate(&t_of) / DIVISOR_RTL9300;
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+ pr_info("Frequency in dts: %ld, my rate is %ld, period %ld\n",
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+ timer_of_rate(&t_of), rate, timer_of_period(&t_of));
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+ pr_info("With base %08x IRQ: %d\n", (u32)timer_of_base(&t_of), timer_of_irq(&t_of));
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+
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+ // Configure clock source and register it for scheduling
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+ rtl9300_timer_setup(TIMER_CLK_SRC);
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+ rtl9300_timer_start(&t_of, TIMER_CLK_SRC, TIMER_MODE_REPEAT);
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+
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+ rtl9300_sched_reg = timer_of_base(&t_of) + TIMER_CLK_SRC * 0x10 + RTL9300_TC_CNT;
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+
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+ err = clocksource_mmio_init(rtl9300_sched_reg, node->name, rate , 100, N_BITS,
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+ clocksource_mmio_readl_up);
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+ if (err)
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+ return err;
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+
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+ sched_clock_register(rtl9300_sched_clock_read, N_BITS, rate);
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+
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+ // Configure clock event source
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+ rtl9300_timer_setup(TIMER_CLK_EVT);
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+ clockevents_config_and_register(&t_of.clkevt, rate, 100, 0x0fffffff);
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+
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+ // Enable interrupt
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+ writel(RTL9300_TC_INT_IE, timer_of_base(&t_of) + TIMER_BLK_EVT + RTL9300_TC_INT);
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+
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+ return err;
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+}
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+
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+TIMER_OF_DECLARE(rtl9300_timer, "realtek,rtl9300-timer", rtl9300_timer_init);
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Birger Koblitz