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@@ -0,0 +1,832 @@
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+From fa236a7ef24048bafaeed13f68df35a819794758 Mon Sep 17 00:00:00 2001
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+From: Kamal Dasu <[email protected]>
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+Date: Wed, 24 Aug 2016 18:04:23 -0400
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+Subject: [PATCH] spi: bcm-qspi: Add Broadcom MSPI driver
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+
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+Master SPI driver for Broadcom settop, iProc SoCs. The driver
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+is used for devices that use SPI protocol on BRCMSTB, NSP, NS2
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+SoCs. SoC platform driver call exported porbe(), remove()
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+and suspend/resume pm_ops implemented in this common driver.
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+
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+Signed-off-by: Kamal Dasu <[email protected]>
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+Signed-off-by: Yendapally Reddy Dhananjaya Reddy
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+Signed-off-by: Mark Brown <[email protected]>
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+---
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+ drivers/spi/Kconfig | 10 +
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+ drivers/spi/Makefile | 1 +
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+ drivers/spi/spi-bcm-qspi.c | 712 +++++++++++++++++++++++++++++++++++++++++++++
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+ drivers/spi/spi-bcm-qspi.h | 63 ++++
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+ 4 files changed, 786 insertions(+)
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+ create mode 100644 drivers/spi/spi-bcm-qspi.c
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+ create mode 100644 drivers/spi/spi-bcm-qspi.h
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+
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+--- a/drivers/spi/Kconfig
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++++ b/drivers/spi/Kconfig
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+@@ -147,6 +147,16 @@ config SPI_BCM63XX_HSSPI
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+ This enables support for the High Speed SPI controller present on
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+ newer Broadcom BCM63XX SoCs.
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+
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++config SPI_BCM_QSPI
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++ tristate "Broadcom BSPI and MSPI controller support"
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++ depends on ARCH_BRCMSTB || ARCH_BCM || ARCH_BCM_IPROC || COMPILE_TEST
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++ default ARCH_BCM_IPROC
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++ help
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++ Enables support for the Broadcom SPI flash and MSPI controller.
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++ Select this option for any one of BRCMSTB, iProc NSP and NS2 SoCs
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++ based platforms. This driver works for both SPI master for spi-nor
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++ flash device as well as MSPI device.
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++
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+ config SPI_BITBANG
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+ tristate "Utilities for Bitbanging SPI masters"
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+ help
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+--- a/drivers/spi/Makefile
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++++ b/drivers/spi/Makefile
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+@@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_BCM2835AUX) += spi-bcm
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+ obj-$(CONFIG_SPI_BCM53XX) += spi-bcm53xx.o
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+ obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
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+ obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
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++obj-$(CONFIG_SPI_BCM_QSPI) += spi-bcm-qspi.o
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+ obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
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+ obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o
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+ obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
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+--- /dev/null
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++++ b/drivers/spi/spi-bcm-qspi.c
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+@@ -0,0 +1,712 @@
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++/*
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++ * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
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++ *
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++ * Copyright 2016 Broadcom
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++ *
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++ * This program is free software; you can redistribute it and/or modify
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++ * it under the terms of the GNU General Public License, version 2, as
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++ * published by the Free Software Foundation (the "GPL").
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++ *
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++ * This program is distributed in the hope that it will be useful, but
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++ * WITHOUT ANY WARRANTY; without even the implied warranty of
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++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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++ * General Public License version 2 (GPLv2) for more details.
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++ *
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++ * You should have received a copy of the GNU General Public License
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++ * version 2 (GPLv2) along with this source code.
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++ */
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++
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++#include <linux/clk.h>
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++#include <linux/delay.h>
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++#include <linux/device.h>
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++#include <linux/init.h>
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++#include <linux/interrupt.h>
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++#include <linux/io.h>
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++#include <linux/ioport.h>
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++#include <linux/kernel.h>
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++#include <linux/module.h>
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++#include <linux/mtd/cfi.h>
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++#include <linux/mtd/spi-nor.h>
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++#include <linux/of.h>
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++#include <linux/of_irq.h>
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++#include <linux/platform_device.h>
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++#include <linux/slab.h>
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++#include <linux/spi/spi.h>
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++#include <linux/sysfs.h>
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++#include <linux/types.h>
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++#include "spi-bcm-qspi.h"
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++
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++#define DRIVER_NAME "bcm_qspi"
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++
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++/* MSPI register offsets */
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++#define MSPI_SPCR0_LSB 0x000
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++#define MSPI_SPCR0_MSB 0x004
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++#define MSPI_SPCR1_LSB 0x008
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++#define MSPI_SPCR1_MSB 0x00c
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++#define MSPI_NEWQP 0x010
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++#define MSPI_ENDQP 0x014
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++#define MSPI_SPCR2 0x018
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++#define MSPI_MSPI_STATUS 0x020
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++#define MSPI_CPTQP 0x024
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++#define MSPI_SPCR3 0x028
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++#define MSPI_TXRAM 0x040
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++#define MSPI_RXRAM 0x0c0
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++#define MSPI_CDRAM 0x140
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++#define MSPI_WRITE_LOCK 0x180
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++
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++#define MSPI_MASTER_BIT BIT(7)
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++
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++#define MSPI_NUM_CDRAM 16
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++#define MSPI_CDRAM_CONT_BIT BIT(7)
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++#define MSPI_CDRAM_BITSE_BIT BIT(6)
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++#define MSPI_CDRAM_PCS 0xf
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++
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++#define MSPI_SPCR2_SPE BIT(6)
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++#define MSPI_SPCR2_CONT_AFTER_CMD BIT(7)
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++
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++#define MSPI_MSPI_STATUS_SPIF BIT(0)
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++
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++#define INTR_BASE_BIT_SHIFT 0x02
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++#define INTR_COUNT 0x07
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++
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++#define NUM_CHIPSELECT 4
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++#define QSPI_SPBR_MIN 8U
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++#define QSPI_SPBR_MAX 255U
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++
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++#define OPCODE_DIOR 0xBB
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++#define OPCODE_QIOR 0xEB
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++#define OPCODE_DIOR_4B 0xBC
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++#define OPCODE_QIOR_4B 0xEC
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++
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++#define MAX_CMD_SIZE 6
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++
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++#define ADDR_4MB_MASK GENMASK(22, 0)
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++
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++/* stop at end of transfer, no other reason */
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++#define TRANS_STATUS_BREAK_NONE 0
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++/* stop at end of spi_message */
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++#define TRANS_STATUS_BREAK_EOM 1
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++/* stop at end of spi_transfer if delay */
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++#define TRANS_STATUS_BREAK_DELAY 2
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++/* stop at end of spi_transfer if cs_change */
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++#define TRANS_STATUS_BREAK_CS_CHANGE 4
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++/* stop if we run out of bytes */
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++#define TRANS_STATUS_BREAK_NO_BYTES 8
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++
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++/* events that make us stop filling TX slots */
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++#define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \
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++ TRANS_STATUS_BREAK_DELAY | \
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++ TRANS_STATUS_BREAK_CS_CHANGE)
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++
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++/* events that make us deassert CS */
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++#define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \
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++ TRANS_STATUS_BREAK_CS_CHANGE)
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++
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++struct bcm_qspi_parms {
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++ u32 speed_hz;
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++ u8 mode;
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++ u8 bits_per_word;
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++};
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++
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++enum base_type {
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++ MSPI,
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++ CHIP_SELECT,
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++ BASEMAX,
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++};
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++
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++struct bcm_qspi_irq {
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++ const char *irq_name;
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++ const irq_handler_t irq_handler;
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++ u32 mask;
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++};
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++
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++struct bcm_qspi_dev_id {
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++ const struct bcm_qspi_irq *irqp;
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++ void *dev;
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++};
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++
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++struct qspi_trans {
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++ struct spi_transfer *trans;
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++ int byte;
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++};
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++
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++struct bcm_qspi {
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++ struct platform_device *pdev;
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++ struct spi_master *master;
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++ struct clk *clk;
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++ u32 base_clk;
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++ u32 max_speed_hz;
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++ void __iomem *base[BASEMAX];
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++ struct bcm_qspi_parms last_parms;
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++ struct qspi_trans trans_pos;
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++ int curr_cs;
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++ u32 s3_strap_override_ctrl;
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++ bool big_endian;
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++ int num_irqs;
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++ struct bcm_qspi_dev_id *dev_ids;
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++ struct completion mspi_done;
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++};
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++
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++/* Read qspi controller register*/
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++static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
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++ unsigned int offset)
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++{
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++ return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
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++}
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++
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++/* Write qspi controller register*/
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++static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
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++ unsigned int offset, unsigned int data)
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++{
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++ bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
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++}
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++
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++static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
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++{
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++ u32 data = 0;
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++
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++ if (qspi->curr_cs == cs)
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++ return;
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++ if (qspi->base[CHIP_SELECT]) {
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++ data = bcm_qspi_read(qspi, CHIP_SELECT, 0);
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++ data = (data & ~0xff) | (1 << cs);
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++ bcm_qspi_write(qspi, CHIP_SELECT, 0, data);
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++ usleep_range(10, 20);
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++ }
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++ qspi->curr_cs = cs;
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++}
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++
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++/* MSPI helpers */
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++static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
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++ const struct bcm_qspi_parms *xp)
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++{
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++ u32 spcr, spbr = 0;
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++
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++ if (xp->speed_hz)
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++ spbr = qspi->base_clk / (2 * xp->speed_hz);
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++
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++ spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
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++ bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
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++
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++ spcr = MSPI_MASTER_BIT;
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++ /* for 16 bit the data should be zero */
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++ if (xp->bits_per_word != 16)
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++ spcr |= xp->bits_per_word << 2;
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++ spcr |= xp->mode & 3;
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++ bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
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++
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++ qspi->last_parms = *xp;
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++}
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++
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++static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
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++ struct spi_device *spi,
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++ struct spi_transfer *trans)
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++{
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++ struct bcm_qspi_parms xp;
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++
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++ xp.speed_hz = trans->speed_hz;
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++ xp.bits_per_word = trans->bits_per_word;
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++ xp.mode = spi->mode;
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++
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++ bcm_qspi_hw_set_parms(qspi, &xp);
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++}
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++
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++static int bcm_qspi_setup(struct spi_device *spi)
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++{
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++ struct bcm_qspi_parms *xp;
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++
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++ if (spi->bits_per_word > 16)
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++ return -EINVAL;
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++
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++ xp = spi_get_ctldata(spi);
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++ if (!xp) {
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++ xp = kzalloc(sizeof(*xp), GFP_KERNEL);
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++ if (!xp)
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++ return -ENOMEM;
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++ spi_set_ctldata(spi, xp);
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++ }
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++ xp->speed_hz = spi->max_speed_hz;
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++ xp->mode = spi->mode;
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++
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++ if (spi->bits_per_word)
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++ xp->bits_per_word = spi->bits_per_word;
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++ else
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++ xp->bits_per_word = 8;
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++
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++ return 0;
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++}
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++
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++static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
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++ struct qspi_trans *qt, int flags)
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++{
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++ int ret = TRANS_STATUS_BREAK_NONE;
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++
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++ /* count the last transferred bytes */
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++ if (qt->trans->bits_per_word <= 8)
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++ qt->byte++;
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++ else
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++ qt->byte += 2;
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++
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++ if (qt->byte >= qt->trans->len) {
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++ /* we're at the end of the spi_transfer */
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++
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++ /* in TX mode, need to pause for a delay or CS change */
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++ if (qt->trans->delay_usecs &&
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++ (flags & TRANS_STATUS_BREAK_DELAY))
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++ ret |= TRANS_STATUS_BREAK_DELAY;
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++ if (qt->trans->cs_change &&
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++ (flags & TRANS_STATUS_BREAK_CS_CHANGE))
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++ ret |= TRANS_STATUS_BREAK_CS_CHANGE;
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++ if (ret)
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++ goto done;
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++
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++ dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
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++ if (spi_transfer_is_last(qspi->master, qt->trans))
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++ ret = TRANS_STATUS_BREAK_EOM;
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++ else
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++ ret = TRANS_STATUS_BREAK_NO_BYTES;
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++
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++ qt->trans = NULL;
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++ }
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++
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++done:
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++ dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
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++ qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
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++ return ret;
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++}
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++
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++static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
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++{
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++ u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
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++
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++ /* mask out reserved bits */
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++ return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
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++}
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++
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++static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
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++{
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++ u32 reg_offset = MSPI_RXRAM;
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++ u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
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++ u32 msb_offset = reg_offset + (slot << 3);
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++
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++ return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
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++ ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
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++}
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++
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++static void read_from_hw(struct bcm_qspi *qspi, int slots)
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++{
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++ struct qspi_trans tp;
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++ int slot;
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++
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++ if (slots > MSPI_NUM_CDRAM) {
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++ /* should never happen */
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++ dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
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++ return;
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++ }
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++
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++ tp = qspi->trans_pos;
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++
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++ for (slot = 0; slot < slots; slot++) {
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++ if (tp.trans->bits_per_word <= 8) {
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++ u8 *buf = tp.trans->rx_buf;
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++
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++ if (buf)
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++ buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
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++ dev_dbg(&qspi->pdev->dev, "RD %02x\n",
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++ buf ? buf[tp.byte] : 0xff);
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++ } else {
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++ u16 *buf = tp.trans->rx_buf;
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++
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++ if (buf)
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++ buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
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++ slot);
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++ dev_dbg(&qspi->pdev->dev, "RD %04x\n",
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++ buf ? buf[tp.byte] : 0xffff);
|
|
|
++ }
|
|
|
++
|
|
|
++ update_qspi_trans_byte_count(qspi, &tp,
|
|
|
++ TRANS_STATUS_BREAK_NONE);
|
|
|
++ }
|
|
|
++
|
|
|
++ qspi->trans_pos = tp;
|
|
|
++}
|
|
|
++
|
|
|
++static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
|
|
|
++ u8 val)
|
|
|
++{
|
|
|
++ u32 reg_offset = MSPI_TXRAM + (slot << 3);
|
|
|
++
|
|
|
++ /* mask out reserved bits */
|
|
|
++ bcm_qspi_write(qspi, MSPI, reg_offset, val);
|
|
|
++}
|
|
|
++
|
|
|
++static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
|
|
|
++ u16 val)
|
|
|
++{
|
|
|
++ u32 reg_offset = MSPI_TXRAM;
|
|
|
++ u32 msb_offset = reg_offset + (slot << 3);
|
|
|
++ u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
|
|
|
++
|
|
|
++ bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
|
|
|
++ bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
|
|
|
++}
|
|
|
++
|
|
|
++static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
|
|
|
++{
|
|
|
++ return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
|
|
|
++}
|
|
|
++
|
|
|
++static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
|
|
|
++{
|
|
|
++ bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
|
|
|
++}
|
|
|
++
|
|
|
++/* Return number of slots written */
|
|
|
++static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
|
|
|
++{
|
|
|
++ struct qspi_trans tp;
|
|
|
++ int slot = 0, tstatus = 0;
|
|
|
++ u32 mspi_cdram = 0;
|
|
|
++
|
|
|
++ tp = qspi->trans_pos;
|
|
|
++ bcm_qspi_update_parms(qspi, spi, tp.trans);
|
|
|
++
|
|
|
++ /* Run until end of transfer or reached the max data */
|
|
|
++ while (!tstatus && slot < MSPI_NUM_CDRAM) {
|
|
|
++ if (tp.trans->bits_per_word <= 8) {
|
|
|
++ const u8 *buf = tp.trans->tx_buf;
|
|
|
++ u8 val = buf ? buf[tp.byte] : 0xff;
|
|
|
++
|
|
|
++ write_txram_slot_u8(qspi, slot, val);
|
|
|
++ dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
|
|
|
++ } else {
|
|
|
++ const u16 *buf = tp.trans->tx_buf;
|
|
|
++ u16 val = buf ? buf[tp.byte / 2] : 0xffff;
|
|
|
++
|
|
|
++ write_txram_slot_u16(qspi, slot, val);
|
|
|
++ dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
|
|
|
++ }
|
|
|
++ mspi_cdram = MSPI_CDRAM_CONT_BIT;
|
|
|
++ mspi_cdram |= (~(1 << spi->chip_select) &
|
|
|
++ MSPI_CDRAM_PCS);
|
|
|
++ mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
|
|
|
++ MSPI_CDRAM_BITSE_BIT);
|
|
|
++
|
|
|
++ write_cdram_slot(qspi, slot, mspi_cdram);
|
|
|
++
|
|
|
++ tstatus = update_qspi_trans_byte_count(qspi, &tp,
|
|
|
++ TRANS_STATUS_BREAK_TX);
|
|
|
++ slot++;
|
|
|
++ }
|
|
|
++
|
|
|
++ if (!slot) {
|
|
|
++ dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
|
|
|
++ goto done;
|
|
|
++ }
|
|
|
++
|
|
|
++ dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
|
|
|
++ bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
|
|
|
++ bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
|
|
|
++
|
|
|
++ if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
|
|
|
++ mspi_cdram = read_cdram_slot(qspi, slot - 1) &
|
|
|
++ ~MSPI_CDRAM_CONT_BIT;
|
|
|
++ write_cdram_slot(qspi, slot - 1, mspi_cdram);
|
|
|
++ }
|
|
|
++
|
|
|
++ /* Must flush previous writes before starting MSPI operation */
|
|
|
++ mb();
|
|
|
++ /* Set cont | spe | spifie */
|
|
|
++ bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
|
|
|
++
|
|
|
++done:
|
|
|
++ return slot;
|
|
|
++}
|
|
|
++
|
|
|
++static int bcm_qspi_transfer_one(struct spi_master *master,
|
|
|
++ struct spi_device *spi,
|
|
|
++ struct spi_transfer *trans)
|
|
|
++{
|
|
|
++ struct bcm_qspi *qspi = spi_master_get_devdata(master);
|
|
|
++ int slots;
|
|
|
++ unsigned long timeo = msecs_to_jiffies(100);
|
|
|
++
|
|
|
++ bcm_qspi_chip_select(qspi, spi->chip_select);
|
|
|
++ qspi->trans_pos.trans = trans;
|
|
|
++ qspi->trans_pos.byte = 0;
|
|
|
++
|
|
|
++ while (qspi->trans_pos.byte < trans->len) {
|
|
|
++ reinit_completion(&qspi->mspi_done);
|
|
|
++
|
|
|
++ slots = write_to_hw(qspi, spi);
|
|
|
++ if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
|
|
|
++ dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
|
|
|
++ return -ETIMEDOUT;
|
|
|
++ }
|
|
|
++
|
|
|
++ read_from_hw(qspi, slots);
|
|
|
++ }
|
|
|
++
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static void bcm_qspi_cleanup(struct spi_device *spi)
|
|
|
++{
|
|
|
++ struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
|
|
|
++
|
|
|
++ kfree(xp);
|
|
|
++}
|
|
|
++
|
|
|
++static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
|
|
|
++{
|
|
|
++ struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
|
|
|
++ struct bcm_qspi *qspi = qspi_dev_id->dev;
|
|
|
++ u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
|
|
|
++
|
|
|
++ if (status & MSPI_MSPI_STATUS_SPIF) {
|
|
|
++ /* clear interrupt */
|
|
|
++ status &= ~MSPI_MSPI_STATUS_SPIF;
|
|
|
++ bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
|
|
|
++ complete(&qspi->mspi_done);
|
|
|
++ return IRQ_HANDLED;
|
|
|
++ } else {
|
|
|
++ return IRQ_NONE;
|
|
|
++ }
|
|
|
++}
|
|
|
++
|
|
|
++static const struct bcm_qspi_irq qspi_irq_tab[] = {
|
|
|
++ {
|
|
|
++ .irq_name = "mspi_done",
|
|
|
++ .irq_handler = bcm_qspi_mspi_l2_isr,
|
|
|
++ .mask = INTR_MSPI_DONE_MASK,
|
|
|
++ },
|
|
|
++ {
|
|
|
++ .irq_name = "mspi_halted",
|
|
|
++ .irq_handler = bcm_qspi_mspi_l2_isr,
|
|
|
++ .mask = INTR_MSPI_HALTED_MASK,
|
|
|
++ },
|
|
|
++};
|
|
|
++
|
|
|
++static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
|
|
|
++{
|
|
|
++ struct bcm_qspi_parms parms;
|
|
|
++
|
|
|
++ bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
|
|
|
++ bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
|
|
|
++ bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
|
|
|
++ bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
|
|
|
++ bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
|
|
|
++
|
|
|
++ parms.mode = SPI_MODE_3;
|
|
|
++ parms.bits_per_word = 8;
|
|
|
++ parms.speed_hz = qspi->max_speed_hz;
|
|
|
++ bcm_qspi_hw_set_parms(qspi, &parms);
|
|
|
++}
|
|
|
++
|
|
|
++static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
|
|
|
++{
|
|
|
++ bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
|
|
|
++}
|
|
|
++
|
|
|
++static const struct of_device_id bcm_qspi_of_match[] = {
|
|
|
++ { .compatible = "brcm,spi-bcm-qspi" },
|
|
|
++ {},
|
|
|
++};
|
|
|
++MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
|
|
|
++
|
|
|
++int bcm_qspi_probe(struct platform_device *pdev,
|
|
|
++ struct bcm_qspi_soc_intc *soc)
|
|
|
++{
|
|
|
++ struct device *dev = &pdev->dev;
|
|
|
++ struct bcm_qspi *qspi;
|
|
|
++ struct spi_master *master;
|
|
|
++ struct resource *res;
|
|
|
++ int irq, ret = 0, num_ints = 0;
|
|
|
++ u32 val;
|
|
|
++ const char *name = NULL;
|
|
|
++ int num_irqs = ARRAY_SIZE(qspi_irq_tab);
|
|
|
++
|
|
|
++ /* We only support device-tree instantiation */
|
|
|
++ if (!dev->of_node)
|
|
|
++ return -ENODEV;
|
|
|
++
|
|
|
++ if (!of_match_node(bcm_qspi_of_match, dev->of_node))
|
|
|
++ return -ENODEV;
|
|
|
++
|
|
|
++ master = spi_alloc_master(dev, sizeof(struct bcm_qspi));
|
|
|
++ if (!master) {
|
|
|
++ dev_err(dev, "error allocating spi_master\n");
|
|
|
++ return -ENOMEM;
|
|
|
++ }
|
|
|
++
|
|
|
++ qspi = spi_master_get_devdata(master);
|
|
|
++ qspi->pdev = pdev;
|
|
|
++ qspi->trans_pos.trans = NULL;
|
|
|
++ qspi->trans_pos.byte = 0;
|
|
|
++ qspi->master = master;
|
|
|
++
|
|
|
++ master->bus_num = -1;
|
|
|
++ master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
|
|
|
++ master->setup = bcm_qspi_setup;
|
|
|
++ master->transfer_one = bcm_qspi_transfer_one;
|
|
|
++ master->cleanup = bcm_qspi_cleanup;
|
|
|
++ master->dev.of_node = dev->of_node;
|
|
|
++ master->num_chipselect = NUM_CHIPSELECT;
|
|
|
++
|
|
|
++ qspi->big_endian = of_device_is_big_endian(dev->of_node);
|
|
|
++
|
|
|
++ if (!of_property_read_u32(dev->of_node, "num-cs", &val))
|
|
|
++ master->num_chipselect = val;
|
|
|
++
|
|
|
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
|
|
|
++ if (!res)
|
|
|
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
|
|
++ "mspi");
|
|
|
++
|
|
|
++ if (res) {
|
|
|
++ qspi->base[MSPI] = devm_ioremap_resource(dev, res);
|
|
|
++ if (IS_ERR(qspi->base[MSPI])) {
|
|
|
++ ret = PTR_ERR(qspi->base[MSPI]);
|
|
|
++ goto qspi_probe_err;
|
|
|
++ }
|
|
|
++ } else {
|
|
|
++ goto qspi_probe_err;
|
|
|
++ }
|
|
|
++
|
|
|
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
|
|
|
++ if (res) {
|
|
|
++ qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
|
|
|
++ if (IS_ERR(qspi->base[CHIP_SELECT])) {
|
|
|
++ ret = PTR_ERR(qspi->base[CHIP_SELECT]);
|
|
|
++ goto qspi_probe_err;
|
|
|
++ }
|
|
|
++ }
|
|
|
++
|
|
|
++ qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
|
|
|
++ GFP_KERNEL);
|
|
|
++ if (IS_ERR(qspi->dev_ids)) {
|
|
|
++ ret = PTR_ERR(qspi->dev_ids);
|
|
|
++ goto qspi_probe_err;
|
|
|
++ }
|
|
|
++
|
|
|
++ for (val = 0; val < num_irqs; val++) {
|
|
|
++ irq = -1;
|
|
|
++ name = qspi_irq_tab[val].irq_name;
|
|
|
++ irq = platform_get_irq_byname(pdev, name);
|
|
|
++
|
|
|
++ if (irq >= 0) {
|
|
|
++ ret = devm_request_irq(&pdev->dev, irq,
|
|
|
++ qspi_irq_tab[val].irq_handler, 0,
|
|
|
++ name,
|
|
|
++ &qspi->dev_ids[val]);
|
|
|
++ if (ret < 0) {
|
|
|
++ dev_err(&pdev->dev, "IRQ %s not found\n", name);
|
|
|
++ goto qspi_probe_err;
|
|
|
++ }
|
|
|
++
|
|
|
++ qspi->dev_ids[val].dev = qspi;
|
|
|
++ qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
|
|
|
++ num_ints++;
|
|
|
++ dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
|
|
|
++ qspi_irq_tab[val].irq_name,
|
|
|
++ irq);
|
|
|
++ }
|
|
|
++ }
|
|
|
++
|
|
|
++ if (!num_ints) {
|
|
|
++ dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
|
|
|
++ goto qspi_probe_err;
|
|
|
++ }
|
|
|
++
|
|
|
++ qspi->clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
++ if (IS_ERR(qspi->clk)) {
|
|
|
++ dev_warn(dev, "unable to get clock\n");
|
|
|
++ goto qspi_probe_err;
|
|
|
++ }
|
|
|
++
|
|
|
++ ret = clk_prepare_enable(qspi->clk);
|
|
|
++ if (ret) {
|
|
|
++ dev_err(dev, "failed to prepare clock\n");
|
|
|
++ goto qspi_probe_err;
|
|
|
++ }
|
|
|
++
|
|
|
++ qspi->base_clk = clk_get_rate(qspi->clk);
|
|
|
++ qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
|
|
|
++
|
|
|
++ bcm_qspi_hw_init(qspi);
|
|
|
++ init_completion(&qspi->mspi_done);
|
|
|
++ qspi->curr_cs = -1;
|
|
|
++
|
|
|
++ platform_set_drvdata(pdev, qspi);
|
|
|
++ ret = devm_spi_register_master(&pdev->dev, master);
|
|
|
++ if (ret < 0) {
|
|
|
++ dev_err(dev, "can't register master\n");
|
|
|
++ goto qspi_reg_err;
|
|
|
++ }
|
|
|
++
|
|
|
++ return 0;
|
|
|
++
|
|
|
++qspi_reg_err:
|
|
|
++ bcm_qspi_hw_uninit(qspi);
|
|
|
++ clk_disable_unprepare(qspi->clk);
|
|
|
++qspi_probe_err:
|
|
|
++ spi_master_put(master);
|
|
|
++ kfree(qspi->dev_ids);
|
|
|
++ return ret;
|
|
|
++}
|
|
|
++/* probe function to be called by SoC specific platform driver probe */
|
|
|
++EXPORT_SYMBOL_GPL(bcm_qspi_probe);
|
|
|
++
|
|
|
++int bcm_qspi_remove(struct platform_device *pdev)
|
|
|
++{
|
|
|
++ struct bcm_qspi *qspi = platform_get_drvdata(pdev);
|
|
|
++
|
|
|
++ platform_set_drvdata(pdev, NULL);
|
|
|
++ bcm_qspi_hw_uninit(qspi);
|
|
|
++ clk_disable_unprepare(qspi->clk);
|
|
|
++ kfree(qspi->dev_ids);
|
|
|
++ spi_unregister_master(qspi->master);
|
|
|
++
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++/* function to be called by SoC specific platform driver remove() */
|
|
|
++EXPORT_SYMBOL_GPL(bcm_qspi_remove);
|
|
|
++
|
|
|
++#ifdef CONFIG_PM_SLEEP
|
|
|
++static int bcm_qspi_suspend(struct device *dev)
|
|
|
++{
|
|
|
++ struct bcm_qspi *qspi = dev_get_drvdata(dev);
|
|
|
++
|
|
|
++ spi_master_suspend(qspi->master);
|
|
|
++ clk_disable(qspi->clk);
|
|
|
++ bcm_qspi_hw_uninit(qspi);
|
|
|
++
|
|
|
++ return 0;
|
|
|
++};
|
|
|
++
|
|
|
++static int bcm_qspi_resume(struct device *dev)
|
|
|
++{
|
|
|
++ struct bcm_qspi *qspi = dev_get_drvdata(dev);
|
|
|
++ int ret = 0;
|
|
|
++
|
|
|
++ bcm_qspi_hw_init(qspi);
|
|
|
++ bcm_qspi_chip_select(qspi, qspi->curr_cs);
|
|
|
++ ret = clk_enable(qspi->clk);
|
|
|
++ if (!ret)
|
|
|
++ spi_master_resume(qspi->master);
|
|
|
++
|
|
|
++ return ret;
|
|
|
++}
|
|
|
++#endif /* CONFIG_PM_SLEEP */
|
|
|
++
|
|
|
++const struct dev_pm_ops bcm_qspi_pm_ops = {
|
|
|
++ .suspend = bcm_qspi_suspend,
|
|
|
++ .resume = bcm_qspi_resume,
|
|
|
++};
|
|
|
++/* pm_ops to be called by SoC specific platform driver */
|
|
|
++EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
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++
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++MODULE_AUTHOR("Kamal Dasu");
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++MODULE_DESCRIPTION("Broadcom QSPI driver");
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++MODULE_LICENSE("GPL v2");
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++MODULE_ALIAS("platform:" DRIVER_NAME);
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+--- /dev/null
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++++ b/drivers/spi/spi-bcm-qspi.h
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+@@ -0,0 +1,63 @@
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++/*
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++ * Copyright 2016 Broadcom
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++ *
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++ * This program is free software; you can redistribute it and/or modify
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++ * it under the terms of the GNU General Public License, version 2, as
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++ * published by the Free Software Foundation (the "GPL").
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++ *
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++ * This program is distributed in the hope that it will be useful, but
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++ * WITHOUT ANY WARRANTY; without even the implied warranty of
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++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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++ * General Public License version 2 (GPLv2) for more details.
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++ *
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++ * You should have received a copy of the GNU General Public License
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++ * version 2 (GPLv2) along with this source code.
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++ */
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++
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++#ifndef __SPI_BCM_QSPI_H__
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++#define __SPI_BCM_QSPI_H__
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++
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++#include <linux/types.h>
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++#include <linux/io.h>
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++
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++/* MSPI Interrupt masks */
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++#define INTR_MSPI_HALTED_MASK BIT(6)
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++#define INTR_MSPI_DONE_MASK BIT(5)
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++
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++#define MSPI_INTERRUPTS_ALL \
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++ (INTR_MSPI_DONE_MASK | \
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|
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++ INTR_MSPI_HALTED_MASK)
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|
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++
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|
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++struct platform_device;
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|
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++struct dev_pm_ops;
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++
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++struct bcm_qspi_soc_intc;
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|
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++
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|
|
++/* Read controller register*/
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|
|
++static inline u32 bcm_qspi_readl(bool be, void __iomem *addr)
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|
|
++{
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|
|
++ if (be)
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|
|
++ return ioread32be(addr);
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|
|
++ else
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|
|
++ return readl_relaxed(addr);
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|
|
++}
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++
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|
|
++/* Write controller register*/
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|
|
++static inline void bcm_qspi_writel(bool be,
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|
|
++ unsigned int data, void __iomem *addr)
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|
|
++{
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|
|
++ if (be)
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|
|
++ iowrite32be(data, addr);
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|
|
++ else
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|
|
++ writel_relaxed(data, addr);
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|
|
++}
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++
|
|
|
++/* The common driver functions to be called by the SoC platform driver */
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|
|
++int bcm_qspi_probe(struct platform_device *pdev,
|
|
|
++ struct bcm_qspi_soc_intc *soc_intc);
|
|
|
++int bcm_qspi_remove(struct platform_device *pdev);
|
|
|
++
|
|
|
++/* pm_ops used by the SoC platform driver called on PM suspend/resume */
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|
|
++extern const struct dev_pm_ops bcm_qspi_pm_ops;
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|
|
++
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|
|
++#endif /* __SPI_BCM_QSPI_H__ */
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Rafał Miłecki