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+From 34167f1a024d2c5abae0b0325a6d0b8257160f86 Mon Sep 17 00:00:00 2001
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+From: Markus Stockhausen <[email protected]>
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+Date: Wed, 13 Aug 2025 01:44:07 -0400
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+Subject: net: phy: realtek: convert RTL8226-CG to c45 only
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+
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+Short: Convert the RTL8226-CG to c45 so it can be used in its
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+Realtek based ecosystems.
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+
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+Long: The RTL8226-CG can be mainly found on devices of the
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+Realtek Otto switch platform. Devices like the Zyxel XGS1210-12
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+are based on it. These implement a hardware based phy polling
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+in the background to update SoC status registers.
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+
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+The hardware provides 4 smi busses where phys are attached to.
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+For each bus one can decide if it is polled in c45 or c22 mode.
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+See https://svanheule.net/realtek/longan/register/smi_glb_ctrl
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+With this setting the register access will be limited by the
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+hardware. This is very complex (including caching and special
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+c45-over-c22 handling). But basically it boils down to "enable
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+protocol x and SoC will disable register access via protocol y".
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+
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+Mainline already gained support for the rtl9300 mdio driver
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+in commit 24e31e474769 ("net: mdio: Add RTL9300 MDIO driver").
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+
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+It covers the basic features, but a lot effort is still needed
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+to understand hardware properly. So it runs a simple setup by
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+selecting the proper bus mode during startup.
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+
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+ /* Put the interfaces into C45 mode if required */
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+ glb_ctrl_mask = GENMASK(19, 16);
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+ for (i = 0; i < MAX_SMI_BUSSES; i++)
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+ if (priv->smi_bus_is_c45[i])
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+ glb_ctrl_val |= GLB_CTRL_INTF_SEL(i);
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+ ...
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+ err = regmap_update_bits(regmap, SMI_GLB_CTRL,
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+ glb_ctrl_mask, glb_ctrl_val);
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+
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+To avoid complex coding later on, it limits access by only
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+providing either c22 or c45:
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+
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+ bus->name = "Realtek Switch MDIO Bus";
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+ if (priv->smi_bus_is_c45[mdio_bus]) {
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+ bus->read_c45 = rtl9300_mdio_read_c45;
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+ bus->write_c45 = rtl9300_mdio_write_c45;
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+ } else {
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+ bus->read = rtl9300_mdio_read_c22;
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+ bus->write = rtl9300_mdio_write_c22;
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+ }
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+
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+Because of these limitations the existing RTL8226 phy driver
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+is not working at all on Realtek switches. Convert the driver
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+to c45-only.
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+
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+Luckily the RTL8226 seems to support proper MDIO_PMA_EXTABLE
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+flags. So standard function genphy_c45_pma_read_abilities() can
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+call genphy_c45_pma_read_ext_abilities() and 10/100/1000 is
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+populated right. Thus conversion is straight forward.
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+
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+Outputs before - REMARK: For this a "hacked" bus was used that
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+toggles the mode for each c22/c45 access. But that is slow and
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+produces unstable data in the SoC status registers).
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+
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+Settings for lan9:
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+ Supported ports: [ TP MII ]
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+ Supported link modes: 10baseT/Half 10baseT/Full
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+ 100baseT/Half 100baseT/Full
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+ 1000baseT/Full
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+ 2500baseT/Full
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+ Supported pause frame use: Symmetric Receive-only
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+ Supports auto-negotiation: Yes
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+ Supported FEC modes: Not reported
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+ Advertised link modes: 10baseT/Half 10baseT/Full
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+ 100baseT/Half 100baseT/Full
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+ 1000baseT/Full
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+ 2500baseT/Full
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+ Advertised pause frame use: Symmetric Receive-only
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+ Advertised auto-negotiation: Yes
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+ Advertised FEC modes: Not reported
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+ Speed: Unknown!
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+ Duplex: Unknown! (255)
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+ Port: Twisted Pair
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+ PHYAD: 24
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+ Transceiver: external
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+ Auto-negotiation: on
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+ MDI-X: Unknown
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+ Supports Wake-on: d
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+ Wake-on: d
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+ Link detected: no
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+
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+Outputs with this commit:
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+
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+Settings for lan9:
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+ Supported ports: [ TP ]
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+ Supported link modes: 10baseT/Half 10baseT/Full
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+ 100baseT/Half 100baseT/Full
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+ 1000baseT/Full
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+ 2500baseT/Full
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+ Supported pause frame use: Symmetric Receive-only
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+ Supports auto-negotiation: Yes
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+ Supported FEC modes: Not reported
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+ Advertised link modes: 10baseT/Half 10baseT/Full
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+ 100baseT/Half 100baseT/Full
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+ 1000baseT/Full
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+ 2500baseT/Full
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+ Advertised pause frame use: Symmetric Receive-only
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+ Advertised auto-negotiation: Yes
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+ Advertised FEC modes: Not reported
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+ Speed: Unknown!
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+ Duplex: Unknown! (255)
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+ Port: Twisted Pair
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+ PHYAD: 24
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+ Transceiver: external
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+ Auto-negotiation: on
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+ MDI-X: Unknown
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+ Supports Wake-on: d
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+ Wake-on: d
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+ Link detected: no
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+
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+Signed-off-by: Markus Stockhausen <[email protected]>
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+Link: https://patch.msgid.link/[email protected]
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+Signed-off-by: Jakub Kicinski <[email protected]>
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+---
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+ drivers/net/phy/realtek/realtek_main.c | 28 +++++++++++++++++++++-------
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+ 1 file changed, 21 insertions(+), 7 deletions(-)
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+
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+--- a/drivers/net/phy/realtek/realtek_main.c
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++++ b/drivers/net/phy/realtek/realtek_main.c
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+@@ -1274,6 +1274,21 @@ static int rtl822x_c45_read_status(struc
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+ return 0;
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+ }
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+
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++static int rtl822x_c45_soft_reset(struct phy_device *phydev)
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++{
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++ int ret, val;
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++
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++ ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
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++ MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
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++ if (ret < 0)
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++ return ret;
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++
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++ return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD,
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++ MDIO_CTRL1, val,
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++ !(val & MDIO_CTRL1_RESET),
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++ 5000, 100000, true);
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++}
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++
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+ static int rtl822xb_c45_read_status(struct phy_device *phydev)
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+ {
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+ int ret;
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+@@ -1660,13 +1675,12 @@ static struct phy_driver realtek_drvs[]
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+ }, {
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+ PHY_ID_MATCH_EXACT(0x001cc838),
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+ .name = "RTL8226-CG 2.5Gbps PHY",
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+- .get_features = rtl822x_get_features,
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+- .config_aneg = rtl822x_config_aneg,
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+- .read_status = rtl822x_read_status,
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+- .suspend = genphy_suspend,
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+- .resume = rtlgen_resume,
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+- .read_page = rtl821x_read_page,
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+- .write_page = rtl821x_write_page,
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++ .soft_reset = rtl822x_c45_soft_reset,
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++ .get_features = rtl822x_c45_get_features,
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++ .config_aneg = rtl822x_c45_config_aneg,
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++ .read_status = rtl822x_c45_read_status,
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++ .suspend = genphy_c45_pma_suspend,
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++ .resume = rtlgen_c45_resume,
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+ }, {
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+ PHY_ID_MATCH_EXACT(0x001cc848),
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+ .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
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Markus Stockhausen