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@@ -1,3 +1,11 @@
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+Sent to mainline on 2009 Feb 03.
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+
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+For further modifications, please use separate patch files. This simpifies
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+keeping track of what is upstream and what is not. Thanks.
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+
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+--mb
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+
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+
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Index: linux-2.6.28.2/drivers/ssb/Makefile
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===================================================================
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--- linux-2.6.28.2.orig/drivers/ssb/Makefile 2009-02-01 13:09:04.000000000 +0100
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@@ -13,8 +21,8 @@ Index: linux-2.6.28.2/drivers/ssb/Makefile
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Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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-+++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-02 20:59:48.000000000 +0100
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-@@ -0,0 +1,481 @@
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++++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-03 19:07:23.000000000 +0100
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+@@ -0,0 +1,508 @@
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+/*
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+ * Sonics Silicon Backplane
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+ * Broadcom ChipCommon Power Management Unit driver
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@@ -254,17 +262,15 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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+ ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
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+ (crystalfreq / 1000), (crystalfreq % 1000));
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+
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-+WARN_ON(1); //TODO not fully implemented, yet.
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-+return;
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+ /* First turn the PLL off. */
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+ switch (bus->chip_id) {
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+ case 0x4325:
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+ chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
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+ ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
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-+ (1 << SSB_PMURES_4325_HT_AVAIL)));
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++ (1 << SSB_PMURES_4325_HT_AVAIL)));
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+ chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
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+ ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
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-+ (1 << SSB_PMURES_4325_HT_AVAIL)));
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++ (1 << SSB_PMURES_4325_HT_AVAIL)));
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+ /* Adjust the BBPLL to 2 on all channels later. */
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+ buffer_strength = 0x222222;
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+ break;
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@@ -283,10 +289,39 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
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+
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+ /* Set p1div and p2div. */
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+ pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
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-+ //TODO
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++ pllctl &= ~(SSB_PMU1_PLLCTL0_P1DIV | SSB_PMU1_PLLCTL0_P2DIV);
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++ pllctl |= ((u32)e->p1div << SSB_PMU1_PLLCTL0_P1DIV_SHIFT) & SSB_PMU1_PLLCTL0_P1DIV;
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++ pllctl |= ((u32)e->p2div << SSB_PMU1_PLLCTL0_P2DIV_SHIFT) & SSB_PMU1_PLLCTL0_P2DIV;
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+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
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+
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-+ //TODO
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++ /* Set ndiv int and ndiv mode */
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++ pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL2);
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++ pllctl &= ~(SSB_PMU1_PLLCTL2_NDIVINT | SSB_PMU1_PLLCTL2_NDIVMODE);
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++ pllctl |= ((u32)e->ndiv_int << SSB_PMU1_PLLCTL2_NDIVINT_SHIFT) & SSB_PMU1_PLLCTL2_NDIVINT;
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++ pllctl |= (1 << SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT) & SSB_PMU1_PLLCTL2_NDIVMODE;
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++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl);
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++
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++ /* Set ndiv frac */
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++ pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL3);
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++ pllctl &= ~SSB_PMU1_PLLCTL3_NDIVFRAC;
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++ pllctl |= ((u32)e->ndiv_frac << SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT) & SSB_PMU1_PLLCTL3_NDIVFRAC;
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++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl);
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++
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++ /* Change the drive strength, if required. */
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++ if (buffer_strength) {
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++ pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL5);
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++ pllctl &= ~SSB_PMU1_PLLCTL5_CLKDRV;
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++ pllctl |= (buffer_strength << SSB_PMU1_PLLCTL5_CLKDRV_SHIFT) & SSB_PMU1_PLLCTL5_CLKDRV;
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++ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl);
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++ }
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++
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++ /* Tune the crystalfreq and the divisor. */
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++ pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
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++ pmuctl &= ~(SSB_CHIPCO_PMU_CTL_ILP_DIV | SSB_CHIPCO_PMU_CTL_XTALFREQ);
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++ pmuctl |= ((((u32)e->freq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
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++ & SSB_CHIPCO_PMU_CTL_ILP_DIV;
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++ pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
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++ chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
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+}
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+
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+static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
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@@ -531,7 +566,7 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon.c
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Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
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===================================================================
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--- linux-2.6.28.2.orig/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-01 13:22:59.000000000 +0100
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-+++ linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-02 21:00:08.000000000 +0100
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++++ linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h 2009-02-03 18:43:33.000000000 +0100
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@@ -181,6 +181,16 @@
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#define SSB_CHIPCO_PROG_WAITCNT 0x0124
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#define SSB_CHIPCO_FLASH_CFG 0x0128
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@@ -549,7 +584,7 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
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#define SSB_CHIPCO_UART0_DATA 0x0300
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#define SSB_CHIPCO_UART0_IMR 0x0304
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#define SSB_CHIPCO_UART0_FCR 0x0308
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-@@ -197,6 +207,172 @@
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+@@ -197,6 +207,196 @@
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#define SSB_CHIPCO_UART1_LSR 0x0414
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#define SSB_CHIPCO_UART1_MSR 0x0418
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#define SSB_CHIPCO_UART1_SCRATCH 0x041C
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@@ -613,11 +648,35 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
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+
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+/* PMU rev 1 PLL registers */
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+#define SSB_PMU1_PLLCTL0 0
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++#define SSB_PMU1_PLLCTL0_P1DIV 0x00F00000 /* P1 div */
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++#define SSB_PMU1_PLLCTL0_P1DIV_SHIFT 20
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++#define SSB_PMU1_PLLCTL0_P2DIV 0x0F000000 /* P2 div */
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++#define SSB_PMU1_PLLCTL0_P2DIV_SHIFT 24
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+#define SSB_PMU1_PLLCTL1 1
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++#define SSB_PMU1_PLLCTL1_M1DIV 0x000000FF /* M1 div */
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++#define SSB_PMU1_PLLCTL1_M1DIV_SHIFT 0
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++#define SSB_PMU1_PLLCTL1_M2DIV 0x0000FF00 /* M2 div */
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++#define SSB_PMU1_PLLCTL1_M2DIV_SHIFT 8
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++#define SSB_PMU1_PLLCTL1_M3DIV 0x00FF0000 /* M3 div */
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++#define SSB_PMU1_PLLCTL1_M3DIV_SHIFT 16
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++#define SSB_PMU1_PLLCTL1_M4DIV 0xFF000000 /* M4 div */
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++#define SSB_PMU1_PLLCTL1_M4DIV_SHIFT 24
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+#define SSB_PMU1_PLLCTL2 2
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++#define SSB_PMU1_PLLCTL2_M5DIV 0x000000FF /* M5 div */
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++#define SSB_PMU1_PLLCTL2_M5DIV_SHIFT 0
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++#define SSB_PMU1_PLLCTL2_M6DIV 0x0000FF00 /* M6 div */
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++#define SSB_PMU1_PLLCTL2_M6DIV_SHIFT 8
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++#define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */
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++#define SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT 17
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++#define SSB_PMU1_PLLCTL2_NDIVINT 0x1FF00000 /* NDIV int */
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++#define SSB_PMU1_PLLCTL2_NDIVINT_SHIFT 20
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+#define SSB_PMU1_PLLCTL3 3
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++#define SSB_PMU1_PLLCTL3_NDIVFRAC 0x00FFFFFF /* NDIV frac */
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++#define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT 0
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+#define SSB_PMU1_PLLCTL4 4
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+#define SSB_PMU1_PLLCTL5 5
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++#define SSB_PMU1_PLLCTL5_CLKDRV 0xFFFFFF00 /* clk drv */
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++#define SSB_PMU1_PLLCTL5_CLKDRV_SHIFT 8
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+
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+/* BCM4312 PLL resource numbers. */
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+#define SSB_PMURES_4312_SWITCHER_BURST 0
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@@ -722,7 +781,7 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
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-@@ -353,11 +529,20 @@
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+@@ -353,11 +553,20 @@
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struct ssb_device;
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struct ssb_serial_port;
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@@ -743,7 +802,7 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
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};
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static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
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-@@ -365,6 +550,17 @@ static inline bool ssb_chipco_available(
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+@@ -365,6 +574,17 @@ static inline bool ssb_chipco_available(
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return (cc->dev != NULL);
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}
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@@ -761,7 +820,7 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
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extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
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extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
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-@@ -406,4 +602,8 @@ extern int ssb_chipco_serial_init(struct
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+@@ -406,4 +626,8 @@ extern int ssb_chipco_serial_init(struct
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struct ssb_serial_port *ports);
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#endif /* CONFIG_SSB_SERIAL */
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Michael Büsch