mediatek: copy patches-6.1 to patches-6.6

Copy patches from patches-6.1 to patches-6.6. No changes.

Signed-off-by: Daniel Golle <[email protected]>

target/linux/mediatek/patches-6.6/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch

@@ -0,0 +1,44 @@
+From 363547d2191cbc32ca954ba75d72908712398ff2 Mon Sep 17 00:00:00 2001
+From: Andrew Davis <[email protected]>
+Date: Mon, 24 Oct 2022 12:34:28 -0500
+Subject: [PATCH] kbuild: Allow DTB overlays to built from .dtso named source
+ files
+
+Currently DTB Overlays (.dtbo) are build from source files with the same
+extension (.dts) as the base DTs (.dtb). This may become confusing and
+even lead to wrong results. For example, a composite DTB (created from a
+base DTB and a set of overlays) might have the same name as one of the
+overlays that create it.
+
+Different files should be generated from differently named sources.
+ .dtb  <-> .dts
+ .dtbo <-> .dtso
+
+We do not remove the ability to compile DTBO files from .dts files here,
+only add a new rule allowing the .dtso file name. The current .dts named
+overlays can be renamed with time. After all have been renamed we can
+remove the other rule.
+
+Signed-off-by: Andrew Davis <[email protected]>
+Reviewed-by: Geert Uytterhoeven <[email protected]>
+Tested-by: Geert Uytterhoeven <[email protected]>
+Reviewed-by: Frank Rowand <[email protected]>
+Tested-by: Frank Rowand <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Rob Herring <[email protected]>
+---
+ scripts/Makefile.lib | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T
+ $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE
+ 	$(call if_changed_dep,dtc)
+ 
++$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
++	$(call if_changed_dep,dtc)
++
+ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+ 
+ # Bzip2

target/linux/mediatek/patches-6.6/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch

@@ -0,0 +1,106 @@
+From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <[email protected]>
+Date: Sat, 5 Nov 2022 23:36:16 +0100
+Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX
+ Wireless Ethernet Dispatch
+
+Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
+Dispatch to offload traffic received by the wlan interface to lan/wan
+one.
+
+Co-developed-by: Sujuan Chen <[email protected]>
+Signed-off-by: Sujuan Chen <[email protected]>
+Signed-off-by: Lorenzo Bianconi <[email protected]>
+Signed-off-by: David S. Miller <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++
+ 1 file changed, 65 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -76,6 +76,47 @@
+ 			no-map;
+ 			reg = <0 0x4fc00000 0 0x00100000>;
+ 		};
++
++		wo_emi0: wo-emi@4fd00000 {
++			reg = <0 0x4fd00000 0 0x40000>;
++			no-map;
++		};
++
++		wo_emi1: wo-emi@4fd40000 {
++			reg = <0 0x4fd40000 0 0x40000>;
++			no-map;
++		};
++
++		wo_ilm0: wo-ilm@151e0000 {
++			reg = <0 0x151e0000 0 0x8000>;
++			no-map;
++		};
++
++		wo_ilm1: wo-ilm@151f0000 {
++			reg = <0 0x151f0000 0 0x8000>;
++			no-map;
++		};
++
++		wo_data: wo-data@4fd80000 {
++			reg = <0 0x4fd80000 0 0x240000>;
++			no-map;
++		};
++
++		wo_dlm0: wo-dlm@151e8000 {
++			reg = <0 0x151e8000 0 0x2000>;
++			no-map;
++		};
++
++		wo_dlm1: wo-dlm@151f8000 {
++			reg = <0 0x151f8000 0 0x2000>;
++			no-map;
++		};
++
++		wo_boot: wo-boot@15194000 {
++			reg = <0 0x15194000 0 0x1000>;
++			no-map;
++		};
++
+ 	};
+ 
+ 	timer {
+@@ -239,6 +280,11 @@
+ 			reg = <0 0x15010000 0 0x1000>;
+ 			interrupt-parent = <&gic>;
+ 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
++			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
++					<&wo_data>, <&wo_boot>;
++			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
++					      "wo-data", "wo-boot";
++			mediatek,wo-ccif = <&wo_ccif0>;
+ 		};
+ 
+ 		wed1: wed@15011000 {
+@@ -247,6 +293,25 @@
+ 			reg = <0 0x15011000 0 0x1000>;
+ 			interrupt-parent = <&gic>;
+ 			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
++			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
++					<&wo_data>, <&wo_boot>;
++			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
++					      "wo-data", "wo-boot";
++			mediatek,wo-ccif = <&wo_ccif1>;
++		};
++
++		wo_ccif0: syscon@151a5000 {
++			compatible = "mediatek,mt7986-wo-ccif", "syscon";
++			reg = <0 0x151a5000 0 0x1000>;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		wo_ccif1: syscon@151ad000 {
++			compatible = "mediatek,mt7986-wo-ccif", "syscon";
++			reg = <0 0x151ad000 0 0x1000>;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ 		};
+ 
+ 		eth: ethernet@15100000 {

target/linux/mediatek/patches-6.6/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch

@@ -0,0 +1,166 @@
+From 438e53828c08cf0e8a65b61cf6ce1e4b6620551a Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sun, 6 Nov 2022 09:50:24 +0100
+Subject: [PATCH 02/19] arm64: dts: mt7986: harmonize device node order
+
+This arrange device tree nodes in alphabetical order.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++----------
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++---
+ 2 files changed, 58 insertions(+), 58 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -54,6 +54,53 @@
+ 	};
+ };
+ 
++&pio {
++	uart1_pins: uart1-pins {
++		mux {
++			function = "uart";
++			groups = "uart1";
++		};
++	};
++
++	uart2_pins: uart2-pins {
++		mux {
++			function = "uart";
++			groups = "uart2";
++		};
++	};
++
++	wf_2g_5g_pins: wf-2g-5g-pins {
++		mux {
++			function = "wifi";
++			groups = "wf_2g", "wf_5g";
++		};
++		conf {
++			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
++			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
++			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
++			       "WF1_TOP_CLK", "WF1_TOP_DATA";
++			drive-strength = <4>;
++		};
++	};
++
++	wf_dbdc_pins: wf-dbdc-pins {
++		mux {
++			function = "wifi";
++			groups = "wf_dbdc";
++		};
++		conf {
++			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++			       "WF0_TOP_CLK", "WF0_TOP_DATA";
++			drive-strength = <4>;
++		};
++	};
++};
++
+ &switch {
+ 	ports {
+ 		#address-cells = <1>;
+@@ -121,50 +168,3 @@
+ 	pinctrl-0 = <&wf_2g_5g_pins>;
+ 	pinctrl-1 = <&wf_dbdc_pins>;
+ };
+-
+-&pio {
+-	uart1_pins: uart1-pins {
+-		mux {
+-			function = "uart";
+-			groups = "uart1";
+-		};
+-	};
+-
+-	uart2_pins: uart2-pins {
+-		mux {
+-			function = "uart";
+-			groups = "uart2";
+-		};
+-	};
+-
+-	wf_2g_5g_pins: wf-2g-5g-pins {
+-		mux {
+-			function = "wifi";
+-			groups = "wf_2g", "wf_5g";
+-		};
+-		conf {
+-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+-			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+-			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+-			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+-			       "WF1_TOP_CLK", "WF1_TOP_DATA";
+-			drive-strength = <4>;
+-		};
+-	};
+-
+-	wf_dbdc_pins: wf-dbdc-pins {
+-		mux {
+-			function = "wifi";
+-			groups = "wf_dbdc";
+-		};
+-		conf {
+-			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+-			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+-			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+-			       "WF0_TOP_CLK", "WF0_TOP_DATA";
+-			drive-strength = <4>;
+-		};
+-	};
+-};
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -25,10 +25,6 @@
+ 	};
+ };
+ 
+-&uart0 {
+-	status = "okay";
+-};
+-
+ &eth {
+ 	status = "okay";
+ 
+@@ -99,13 +95,6 @@
+ 	};
+ };
+ 
+-&wifi {
+-	status = "okay";
+-	pinctrl-names = "default", "dbdc";
+-	pinctrl-0 = <&wf_2g_5g_pins>;
+-	pinctrl-1 = <&wf_dbdc_pins>;
+-};
+-
+ &pio {
+ 	wf_2g_5g_pins: wf-2g-5g-pins {
+ 		mux {
+@@ -138,3 +127,14 @@
+ 		};
+ 	};
+ };
++
++&uart0 {
++	status = "okay";
++};
++
++&wifi {
++	status = "okay";
++	pinctrl-names = "default", "dbdc";
++	pinctrl-0 = <&wf_2g_5g_pins>;
++	pinctrl-1 = <&wf_dbdc_pins>;
++};

target/linux/mediatek/patches-6.6/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch

@@ -0,0 +1,68 @@
+From ffb05357b47f06b2b4d1e14ba89169e28feb727b Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sun, 6 Nov 2022 09:50:27 +0100
+Subject: [PATCH 03/19] arm64: dts: mt7986: add crypto related device nodes
+
+This patch adds crypto engine support for MT7986.
+
+Signed-off-by: Vic Wu <[email protected]>
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts |  4 ++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 15 +++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts |  4 ++++
+ 3 files changed, 23 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -25,6 +25,10 @@
+ 	};
+ };
+ 
++&crypto {
++	status = "okay";
++};
++
+ &eth {
+ 	status = "okay";
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -223,6 +223,21 @@
+ 			status = "disabled";
+ 		};
+ 
++		crypto: crypto@10320000 {
++			compatible = "inside-secure,safexcel-eip97";
++			reg = <0 0x10320000 0 0x40000>;
++			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "ring0", "ring1", "ring2", "ring3";
++			clocks = <&infracfg CLK_INFRA_EIP97_CK>;
++			clock-names = "infra_eip97_ck";
++			assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
++			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
++			status = "disabled";
++		};
++
+ 		uart0: serial@11002000 {
+ 			compatible = "mediatek,mt7986-uart",
+ 				     "mediatek,mt6577-uart";
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -25,6 +25,10 @@
+ 	};
+ };
+ 
++&crypto {
++	status = "okay";
++};
++
+ &eth {
+ 	status = "okay";
+ 

target/linux/mediatek/patches-6.6/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch

@@ -0,0 +1,37 @@
+From b49b7dc404ded1d89cbc568d875009a5c1ed4ef6 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Sun, 6 Nov 2022 09:50:29 +0100
+Subject: [PATCH 04/19] arm64: dts: mt7986: add i2c node
+
+Add i2c Node to mt7986 devicetree.
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -279,6 +279,20 @@
+ 			status = "disabled";
+ 		};
+ 
++		i2c0: i2c@11008000 {
++			compatible = "mediatek,mt7986-i2c";
++			reg = <0 0x11008000 0 0x90>,
++			      <0 0x10217080 0 0x80>;
++			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
++			clock-div = <5>;
++			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
++				 <&infracfg CLK_INFRA_AP_DMA_CK>;
++			clock-names = "main", "dma";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
+ 		ethsys: syscon@15000000 {
+ 			 #address-cells = <1>;
+ 			 #size-cells = <1>;

target/linux/mediatek/patches-6.6/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch

@@ -0,0 +1,61 @@
+From 2cd6022800d6da7822e169f3e6f7f790c1431445 Mon Sep 17 00:00:00 2001
+From: Matthias Brugger <[email protected]>
+Date: Mon, 14 Nov 2022 13:16:53 +0100
+Subject: [PATCH 05/19] arm64: dts: mediatek: mt7986: Add SoC compatible
+
+Missing SoC compatible in the board file causes dt bindings check.
+
+Signed-off-by: Matthias Brugger <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +-
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +-
+ arch/arm64/boot/dts/mediatek/mt7986b.dtsi    | 3 +++
+ 4 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -9,7 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT7986a RFB";
+-	compatible = "mediatek,mt7986a-rfb";
++	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
+ 
+ 	aliases {
+ 		serial0 = &uart0;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -10,6 +10,7 @@
+ #include <dt-bindings/reset/mt7986-resets.h>
+ 
+ / {
++	compatible = "mediatek,mt7986a";
+ 	interrupt-parent = <&gic>;
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -9,7 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT7986b RFB";
+-	compatible = "mediatek,mt7986b-rfb";
++	compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
+ 
+ 	aliases {
+ 		serial0 = &uart0;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+@@ -5,6 +5,9 @@
+  */
+ 
+ #include "mt7986a.dtsi"
++/ {
++	compatible = "mediatek,mt7986b";
++};
+ 
+ &pio {
+ 	compatible = "mediatek,mt7986b-pinctrl";

target/linux/mediatek/patches-6.6/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch

@@ -0,0 +1,157 @@
+From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Fri, 18 Nov 2022 20:01:21 +0100
+Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes
+
+This patch adds spi support for MT7986.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 28 ++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++
+ 3 files changed, 98 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -59,6 +59,20 @@
+ };
+ 
+ &pio {
++	spi_flash_pins: spi-flash-pins {
++		mux {
++			function = "spi";
++			groups = "spi0", "spi0_wp_hold";
++		};
++	};
++
++	spic_pins: spic-pins {
++		mux {
++			function = "spi";
++			groups = "spi1_2";
++		};
++	};
++
+ 	uart1_pins: uart1-pins {
+ 		mux {
+ 			function = "uart";
+@@ -105,6 +119,27 @@
+ 	};
+ };
+ 
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi_flash_pins>;
++	cs-gpios = <0>, <0>;
++	status = "okay";
++	spi_nand: spi_nand@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++		spi-tx-bus-width = <4>;
++		spi-rx-bus-width = <4>;
++	};
++};
++
++&spi1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spic_pins>;
++	cs-gpios = <0>, <0>;
++	status = "okay";
++};
++
+ &switch {
+ 	ports {
+ 		#address-cells = <1>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -294,6 +294,34 @@
+ 			status = "disabled";
+ 		};
+ 
++		spi0: spi@1100a000 {
++			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0 0x1100a000 0 0x100>;
++			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&topckgen CLK_TOP_MPLL_D2>,
++				 <&topckgen CLK_TOP_SPI_SEL>,
++				 <&infracfg CLK_INFRA_SPI0_CK>,
++				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
++			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
++			status = "disabled";
++		};
++
++		spi1: spi@1100b000 {
++			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0 0x1100b000 0 0x100>;
++			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&topckgen CLK_TOP_MPLL_D2>,
++				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
++				 <&infracfg CLK_INFRA_SPI1_CK>,
++				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
++			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
++			status = "disabled";
++		};
++
+ 		ethsys: syscon@15000000 {
+ 			 #address-cells = <1>;
+ 			 #size-cells = <1>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -100,6 +100,20 @@
+ };
+ 
+ &pio {
++	spi_flash_pins: spi-flash-pins {
++		mux {
++			function = "spi";
++			groups = "spi0", "spi0_wp_hold";
++		};
++	};
++
++	spic_pins: spic-pins {
++		mux {
++			function = "spi";
++			groups = "spi1_2";
++		};
++	};
++
+ 	wf_2g_5g_pins: wf-2g-5g-pins {
+ 		mux {
+ 			function = "wifi";
+@@ -132,6 +146,27 @@
+ 	};
+ };
+ 
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi_flash_pins>;
++	cs-gpios = <0>, <0>;
++	status = "okay";
++	spi_nand: spi_nand@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++		spi-tx-bus-width = <4>;
++		spi-rx-bus-width = <4>;
++	};
++};
++
++&spi1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spic_pins>;
++	cs-gpios = <0>, <0>;
++	status = "okay";
++};
++
+ &uart0 {
+ 	status = "okay";
+ };

target/linux/mediatek/patches-6.6/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch

@@ -0,0 +1,127 @@
+From 9e8e24ab716098e617195ce29b88e84608bf2108 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Fri, 6 Jan 2023 16:28:42 +0100
+Subject: [PATCH 07/19] arm64: dts: mt7986: add usb related device nodes
+
+This patch adds USB support for MT7986.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: Chunfeng Yun <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts |  8 +++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 55 ++++++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts |  8 +++
+ 3 files changed, 71 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -140,6 +140,10 @@
+ 	status = "okay";
+ };
+ 
++&ssusb {
++	status = "okay";
++};
++
+ &switch {
+ 	ports {
+ 		#address-cells = <1>;
+@@ -201,6 +205,10 @@
+ 	status = "okay";
+ };
+ 
++&usb_phy {
++	status = "okay";
++};
++
+ &wifi {
+ 	status = "okay";
+ 	pinctrl-names = "default", "dbdc";
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -322,6 +322,61 @@
+ 			status = "disabled";
+ 		};
+ 
++		ssusb: usb@11200000 {
++			compatible = "mediatek,mt7986-xhci",
++				     "mediatek,mtk-xhci";
++			reg = <0 0x11200000 0 0x2e00>,
++			      <0 0x11203e00 0 0x0100>;
++			reg-names = "mac", "ippc";
++			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
++				 <&infracfg CLK_INFRA_IUSB_CK>,
++				 <&infracfg CLK_INFRA_IUSB_133_CK>,
++				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
++				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
++			clock-names = "sys_ck",
++				      "ref_ck",
++				      "mcu_ck",
++				      "dma_ck",
++				      "xhci_ck";
++			phys = <&u2port0 PHY_TYPE_USB2>,
++			       <&u3port0 PHY_TYPE_USB3>,
++			       <&u2port1 PHY_TYPE_USB2>;
++			status = "disabled";
++		};
++
++		usb_phy: t-phy@11e10000 {
++			compatible = "mediatek,mt7986-tphy",
++				     "mediatek,generic-tphy-v2";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0 0x11e10000 0x1700>;
++			status = "disabled";
++
++			u2port0: usb-phy@0 {
++				reg = <0x0 0x700>;
++				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
++					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
++				clock-names = "ref", "da_ref";
++				#phy-cells = <1>;
++			};
++
++			u3port0: usb-phy@700 {
++				reg = <0x700 0x900>;
++				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
++				clock-names = "ref";
++				#phy-cells = <1>;
++			};
++
++			u2port1: usb-phy@1000 {
++				reg = <0x1000 0x700>;
++				clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
++					 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
++				clock-names = "ref", "da_ref";
++				#phy-cells = <1>;
++			};
++		};
++
+ 		ethsys: syscon@15000000 {
+ 			 #address-cells = <1>;
+ 			 #size-cells = <1>;
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -167,10 +167,18 @@
+ 	status = "okay";
+ };
+ 
++&ssusb {
++	status = "okay";
++};
++
+ &uart0 {
+ 	status = "okay";
+ };
+ 
++&usb_phy {
++	status = "okay";
++};
++
+ &wifi {
+ 	status = "okay";
+ 	pinctrl-names = "default", "dbdc";

target/linux/mediatek/patches-6.6/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch

@@ -0,0 +1,160 @@
+From c1744e9e75a6a8abc7c893f349bcbf725b9c0d74 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Fri, 6 Jan 2023 16:28:43 +0100
+Subject: [PATCH 08/19] arm64: dts: mt7986: add mmc related device nodes
+
+This patch adds mmc support for MT7986.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 96 ++++++++++++++++++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 15 +++
+ 2 files changed, 111 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -5,6 +5,8 @@
+  */
+ 
+ /dts-v1/;
++#include <dt-bindings/pinctrl/mt65xx.h>
++
+ #include "mt7986a.dtsi"
+ 
+ / {
+@@ -23,6 +25,24 @@
+ 		device_type = "memory";
+ 		reg = <0 0x40000000 0 0x40000000>;
+ 	};
++
++	reg_1p8v: regulator-1p8v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-1.8V";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	reg_3p3v: regulator-3p3v {
++		compatible = "regulator-fixed";
++		regulator-name = "fixed-3.3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
+ };
+ 
+ &crypto {
+@@ -58,7 +78,83 @@
+ 	};
+ };
+ 
++&mmc0 {
++	pinctrl-names = "default", "state_uhs";
++	pinctrl-0 = <&mmc0_pins_default>;
++	pinctrl-1 = <&mmc0_pins_uhs>;
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	cap-mmc-highspeed;
++	mmc-hs200-1_8v;
++	mmc-hs400-1_8v;
++	hs400-ds-delay = <0x14014>;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_1p8v>;
++	non-removable;
++	no-sd;
++	no-sdio;
++	status = "okay";
++};
++
+ &pio {
++	mmc0_pins_default: mmc0-pins {
++		mux {
++			function = "emmc";
++			groups = "emmc_51";
++		};
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++		conf-clk {
++			pins = "EMMC_CK";
++			drive-strength = <6>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-ds {
++			pins = "EMMC_DSL";
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-rst {
++			pins = "EMMC_RSTB";
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++	};
++
++	mmc0_pins_uhs: mmc0-uhs-pins {
++		mux {
++			function = "emmc";
++			groups = "emmc_51";
++		};
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++		conf-clk {
++			pins = "EMMC_CK";
++			drive-strength = <6>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-ds {
++			pins = "EMMC_DSL";
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-rst {
++			pins = "EMMC_RSTB";
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++	};
++
+ 	spi_flash_pins: spi-flash-pins {
+ 		mux {
+ 			function = "spi";
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -345,6 +345,21 @@
+ 			status = "disabled";
+ 		};
+ 
++		mmc0: mmc@11230000 {
++			compatible = "mediatek,mt7986-mmc";
++			reg = <0 0x11230000 0 0x1000>,
++			      <0 0x11c20000 0 0x1000>;
++			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
++				 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
++				 <&infracfg CLK_INFRA_MSDC_CK>,
++				 <&infracfg CLK_INFRA_MSDC_133M_CK>,
++				 <&infracfg CLK_INFRA_MSDC_66M_CK>;
++			clock-names = "source", "hclk", "source_cg", "bus_clk",
++				      "sys_cg";
++			status = "disabled";
++		};
++
+ 		usb_phy: t-phy@11e10000 {
+ 			compatible = "mediatek,mt7986-tphy",
+ 				     "mediatek,generic-tphy-v2";

target/linux/mediatek/patches-6.6/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch

@@ -0,0 +1,118 @@
+From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Fri, 6 Jan 2023 16:28:44 +0100
+Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes
+
+This patch adds PCIe support for MT7986.
+
+Signed-off-by: Jieyy Yang <[email protected]>
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi    | 52 ++++++++++++++++++++
+ 2 files changed, 68 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -93,6 +93,15 @@
+ 	non-removable;
+ 	no-sd;
+ 	no-sdio;
++};
++
++&pcie {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_pins>;
++	status = "okay";
++};
++
++&pcie_phy {
+ 	status = "okay";
+ };
+ 
+@@ -155,6 +164,13 @@
+ 		};
+ 	};
+ 
++	pcie_pins: pcie-pins {
++		mux {
++			function = "pcie";
++			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
++		};
++	};
++
+ 	spi_flash_pins: spi-flash-pins {
+ 		mux {
+ 			function = "spi";
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt7986-clk.h>
+ #include <dt-bindings/reset/mt7986-resets.h>
++#include <dt-bindings/phy/phy.h>
+ 
+ / {
+ 	compatible = "mediatek,mt7986a";
+@@ -360,6 +361,57 @@
+ 			status = "disabled";
+ 		};
+ 
++		pcie: pcie@11280000 {
++			compatible = "mediatek,mt7986-pcie",
++				     "mediatek,mt8192-pcie";
++			device_type = "pci";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			reg = <0x00 0x11280000 0x00 0x4000>;
++			reg-names = "pcie-mac";
++			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++			bus-range = <0x00 0xff>;
++			ranges = <0x82000000 0x00 0x20000000 0x00
++				  0x20000000 0x00 0x10000000>;
++			clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
++				 <&infracfg CLK_INFRA_IPCIE_CK>,
++				 <&infracfg CLK_INFRA_IPCIER_CK>,
++				 <&infracfg CLK_INFRA_IPCIEB_CK>;
++			clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
++			status = "disabled";
++
++			phys = <&pcie_port PHY_TYPE_PCIE>;
++			phy-names = "pcie-phy";
++
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 0x7>;
++			interrupt-map = <0 0 0 1 &pcie_intc 0>,
++					<0 0 0 2 &pcie_intc 1>,
++					<0 0 0 3 &pcie_intc 2>,
++					<0 0 0 4 &pcie_intc 3>;
++			pcie_intc: interrupt-controller {
++				#address-cells = <0>;
++				#interrupt-cells = <1>;
++				interrupt-controller;
++			};
++		};
++
++		pcie_phy: t-phy@11c00000 {
++			compatible = "mediatek,mt7986-tphy",
++				     "mediatek,generic-tphy-v2";
++			#address-cells = <2>;
++			#size-cells = <2>;
++			ranges;
++			status = "disabled";
++
++			pcie_port: pcie-phy@11c00000 {
++				reg = <0 0x11c00000 0 0x20000>;
++				clocks = <&clk40m>;
++				clock-names = "ref";
++				#phy-cells = <1>;
++			};
++		};
++
+ 		usb_phy: t-phy@11e10000 {
+ 			compatible = "mediatek,mt7986-tphy",
+ 				     "mediatek,generic-tphy-v2";

target/linux/mediatek/patches-6.6/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch

@@ -0,0 +1,689 @@
+From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Fri, 6 Jan 2023 16:28:45 +0100
+Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3
+
+Add support for Bananapi R3 SBC.
+
+- SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
+- SPI-NAND/NOR support (switched CS by sw5/C)
+- all rj45 ports and both SFP working (eth1/lan4)
+- all USB-Ports + SIM-Slot tested
+- i2c and all uarts tested
+- wifi tested (with eeprom calibration data)
+
+The device can boot from all 4 storage options. Both, SPI and MMC, can
+be switched using hardware switches on the board, see
+https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/Makefile         |   5 +
+ .../mt7986a-bananapi-bpi-r3-emmc.dtso         |  29 ++
+ .../mt7986a-bananapi-bpi-r3-nand.dtso         |  55 +++
+ .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso |  68 +++
+ .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso  |  23 +
+ .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts  | 450 ++++++++++++++++++
+ 6 files changed, 630 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+ create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+
+--- a/arch/arm64/boot/dts/mediatek/Makefile
++++ b/arch/arm64/boot/dts/mediatek/Makefile
+@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
++dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
+ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Copyright (C) 2021 MediaTek Inc.
++ * Author: Sam.Shih <[email protected]>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++	fragment@0 {
++		target-path = "/soc/mmc@11230000";
++		__overlay__ {
++			bus-width = <8>;
++			max-frequency = <200000000>;
++			cap-mmc-highspeed;
++			mmc-hs200-1_8v;
++			mmc-hs400-1_8v;
++			hs400-ds-delay = <0x14014>;
++			non-removable;
++			no-sd;
++			no-sdio;
++			status = "okay";
++		};
++	};
++};
++
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+@@ -0,0 +1,55 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
++/*
++ * Authors: Daniel Golle <[email protected]>
++ *          Frank Wunderlich <[email protected]>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++	fragment@0 {
++		target-path = "/soc/spi@1100a000";
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spi_nand: spi_nand@0 {
++				compatible = "spi-nand";
++				reg = <0>;
++				spi-max-frequency = <10000000>;
++				spi-tx-bus-width = <4>;
++				spi-rx-bus-width = <4>;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <1>;
++					#size-cells = <1>;
++
++					partition@0 {
++						label = "bl2";
++						reg = <0x0 0x80000>;
++						read-only;
++					};
++
++					partition@80000 {
++						label = "reserved";
++						reg = <0x80000 0x300000>;
++					};
++
++					partition@380000 {
++						label = "fip";
++						reg = <0x380000 0x200000>;
++						read-only;
++					};
++
++					partition@580000 {
++						label = "ubi";
++						reg = <0x580000 0x7a80000>;
++					};
++				};
++			};
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -0,0 +1,68 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
++/*
++ * Authors: Daniel Golle <[email protected]>
++ *          Frank Wunderlich <[email protected]>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++	fragment@0 {
++		target-path = "/soc/spi@1100a000";
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			flash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <10000000>;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <1>;
++					#size-cells = <1>;
++
++					partition@0 {
++						label = "bl2";
++						reg = <0x0 0x20000>;
++						read-only;
++					};
++
++					partition@20000 {
++						label = "reserved";
++						reg = <0x20000 0x20000>;
++					};
++
++					partition@40000 {
++						label = "u-boot-env";
++						reg = <0x40000 0x40000>;
++					};
++
++					partition@80000 {
++						label = "reserved2";
++						reg = <0x80000 0x80000>;
++					};
++
++					partition@100000 {
++						label = "fip";
++						reg = <0x100000 0x80000>;
++						read-only;
++					};
++
++					partition@180000 {
++						label = "recovery";
++						reg = <0x180000 0xa80000>;
++					};
++
++					partition@c00000 {
++						label = "fit";
++						reg = <0xc00000 0x1400000>;
++					};
++				};
++			};
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+@@ -0,0 +1,23 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Copyright (C) 2021 MediaTek Inc.
++ * Author: Sam.Shih <[email protected]>
++ */
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++	fragment@0 {
++		target-path = "/soc/mmc@11230000";
++		__overlay__ {
++			bus-width = <4>;
++			max-frequency = <52000000>;
++			cap-sd-highspeed;
++			status = "okay";
++		};
++	};
++};
++
+--- /dev/null
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -0,0 +1,450 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++/*
++ * Copyright (C) 2021 MediaTek Inc.
++ * Authors: Sam.Shih <[email protected]>
++ *          Frank Wunderlich <[email protected]>
++ *          Daniel Golle <[email protected]>
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/mt65xx.h>
++
++#include "mt7986a.dtsi"
++
++/ {
++	model = "Bananapi BPI-R3";
++	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
++
++	aliases {
++		serial0 = &uart0;
++		ethernet0 = &gmac0;
++		ethernet1 = &gmac1;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	dcin: regulator-12vd {
++		compatible = "regulator-fixed";
++		regulator-name = "12vd";
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		reset-key {
++			label = "reset";
++			linux,code = <KEY_RESTART>;
++			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
++		};
++
++		wps-key {
++			label = "wps";
++			linux,code = <KEY_WPS_BUTTON>;
++			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	/* i2c of the left SFP cage (wan) */
++	i2c_sfp1: i2c-gpio-0 {
++		compatible = "i2c-gpio";
++		sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <2>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
++	/* i2c of the right SFP cage (lan) */
++	i2c_sfp2: i2c-gpio-1 {
++		compatible = "i2c-gpio";
++		sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <2>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		green_led: led-0 {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_POWER;
++			gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		blue_led: led-1 {
++			color = <LED_COLOR_ID_BLUE>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
++			default-state = "off";
++		};
++	};
++
++	reg_1p8v: regulator-1p8v {
++		compatible = "regulator-fixed";
++		regulator-name = "1.8vd";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-boot-on;
++		regulator-always-on;
++		vin-supply = <&dcin>;
++	};
++
++	reg_3p3v: regulator-3p3v {
++		compatible = "regulator-fixed";
++		regulator-name = "3.3vd";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++		vin-supply = <&dcin>;
++	};
++
++	/* left SFP cage (wan) */
++	sfp1: sfp-1 {
++		compatible = "sff,sfp";
++		i2c-bus = <&i2c_sfp1>;
++		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
++		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
++		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
++		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
++	};
++
++	/* right SFP cage (lan) */
++	sfp2: sfp-2 {
++		compatible = "sff,sfp";
++		i2c-bus = <&i2c_sfp2>;
++		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
++		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
++		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
++		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
++	};
++};
++
++&crypto {
++	status = "okay";
++};
++
++&eth {
++	status = "okay";
++
++	gmac0: mac@0 {
++		compatible = "mediatek,eth-mac";
++		reg = <0>;
++		phy-mode = "2500base-x";
++
++		fixed-link {
++			speed = <2500>;
++			full-duplex;
++			pause;
++		};
++	};
++
++	gmac1: mac@1 {
++		compatible = "mediatek,eth-mac";
++		reg = <1>;
++		phy-mode = "2500base-x";
++		sfp = <&sfp1>;
++		managed = "in-band-status";
++	};
++
++	mdio: mdio-bus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++};
++
++&mdio {
++	switch: switch@1f {
++		compatible = "mediatek,mt7531";
++		reg = <31>;
++		interrupt-controller;
++		#interrupt-cells = <1>;
++		interrupt-parent = <&pio>;
++		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
++		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
++	};
++};
++
++&mmc0 {
++	pinctrl-names = "default", "state_uhs";
++	pinctrl-0 = <&mmc0_pins_default>;
++	pinctrl-1 = <&mmc0_pins_uhs>;
++	vmmc-supply = <&reg_3p3v>;
++	vqmmc-supply = <&reg_1p8v>;
++};
++
++&i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c_pins>;
++	status = "okay";
++};
++
++&pcie {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_pins>;
++	status = "okay";
++};
++
++&pcie_phy {
++	status = "okay";
++};
++
++&pio {
++	i2c_pins: i2c-pins {
++		mux {
++			function = "i2c";
++			groups = "i2c";
++		};
++	};
++
++	mmc0_pins_default: mmc0-pins {
++		mux {
++			function = "emmc";
++			groups = "emmc_51";
++		};
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++		conf-clk {
++			pins = "EMMC_CK";
++			drive-strength = <6>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-ds {
++			pins = "EMMC_DSL";
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-rst {
++			pins = "EMMC_RSTB";
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++	};
++
++	mmc0_pins_uhs: mmc0-uhs-pins {
++		mux {
++			function = "emmc";
++			groups = "emmc_51";
++		};
++		conf-cmd-dat {
++			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
++			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
++			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
++			input-enable;
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++		conf-clk {
++			pins = "EMMC_CK";
++			drive-strength = <6>;
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-ds {
++			pins = "EMMC_DSL";
++			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
++		};
++		conf-rst {
++			pins = "EMMC_RSTB";
++			drive-strength = <4>;
++			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
++		};
++	};
++
++	pcie_pins: pcie-pins {
++		mux {
++			function = "pcie";
++			groups = "pcie_clk", "pcie_pereset";
++		};
++	};
++
++	spi_flash_pins: spi-flash-pins {
++		mux {
++			function = "spi";
++			groups = "spi0", "spi0_wp_hold";
++		};
++	};
++
++	spic_pins: spic-pins {
++		mux {
++			function = "spi";
++			groups = "spi1_0";
++		};
++	};
++
++	uart1_pins: uart1-pins {
++		mux {
++			function = "uart";
++			groups = "uart1_rx_tx";
++		};
++	};
++
++	uart2_pins: uart2-pins {
++		mux {
++			function = "uart";
++			groups = "uart2_0_rx_tx";
++		};
++	};
++
++	wf_2g_5g_pins: wf-2g-5g-pins {
++		mux {
++			function = "wifi";
++			groups = "wf_2g", "wf_5g";
++		};
++		conf {
++			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
++			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
++			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
++			       "WF1_TOP_CLK", "WF1_TOP_DATA";
++			drive-strength = <4>;
++		};
++	};
++
++	wf_dbdc_pins: wf-dbdc-pins {
++		mux {
++			function = "wifi";
++			groups = "wf_dbdc";
++		};
++		conf {
++			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
++			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
++			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
++			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
++			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
++			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
++			       "WF1_TOP_CLK", "WF1_TOP_DATA";
++			drive-strength = <4>;
++		};
++	};
++
++	wf_led_pins: wf-led-pins {
++		mux {
++			function = "led";
++			groups = "wifi_led";
++		};
++	};
++};
++
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi_flash_pins>;
++	status = "okay";
++};
++
++&spi1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spic_pins>;
++	status = "okay";
++};
++
++&ssusb {
++	status = "okay";
++};
++
++&switch {
++	ports {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		port@0 {
++			reg = <0>;
++			label = "wan";
++		};
++
++		port@1 {
++			reg = <1>;
++			label = "lan0";
++		};
++
++		port@2 {
++			reg = <2>;
++			label = "lan1";
++		};
++
++		port@3 {
++			reg = <3>;
++			label = "lan2";
++		};
++
++		port@4 {
++			reg = <4>;
++			label = "lan3";
++		};
++
++		port5: port@5 {
++			reg = <5>;
++			label = "lan4";
++			phy-mode = "2500base-x";
++			sfp = <&sfp2>;
++			managed = "in-band-status";
++		};
++
++		port@6 {
++			reg = <6>;
++			label = "cpu";
++			ethernet = <&gmac0>;
++			phy-mode = "2500base-x";
++
++			fixed-link {
++				speed = <2500>;
++				full-duplex;
++				pause;
++			};
++		};
++	};
++};
++
++&trng {
++	status = "okay";
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pins>;
++	status = "okay";
++};
++
++&usb_phy {
++	status = "okay";
++};
++
++&watchdog {
++	status = "okay";
++};
++
++&wifi {
++	status = "okay";
++	pinctrl-names = "default", "dbdc";
++	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
++	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
++};
++

target/linux/mediatek/patches-6.6/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch

@@ -0,0 +1,323 @@
+From 4c2d5411f4b101f7aa0fd74f80109e3afd6dc967 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Wed, 17 May 2023 12:11:08 +0200
+Subject: [PATCH 11/19] arm64: mediatek: Propagate chassis-type where possible
+
+The chassis-type string identifies the form-factor of the system:
+add this property to all device trees of devices for which the form
+factor is known.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt2712-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt6755-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt6779-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt6795-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt6797-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts                  | 1 +
+ arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts         | 1 +
+ arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts                     | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts         | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts                     | 1 +
+ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts                     | 1 +
+ arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts                  | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts            | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts                 | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-elm.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt8173-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-evb.dts                      | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts     | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts       | 1 +
+ .../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts     | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts       | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts             | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts       | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts      | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts      | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts         | 1 +
+ arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts       | 1 +
+ arch/arm64/boot/dts/mediatek/mt8186-evb.dts                      | 1 +
+ 28 files changed, 28 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+@@ -11,6 +11,7 @@
+ 
+ / {
+ 	model = "MediaTek MT2712 evaluation board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT6755 EVB";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
+@@ -10,6 +10,7 @@
+ 
+ / {
+ 	model = "MediaTek MT6779 EVB";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT6795 Evaluation Board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT6797 Evaluation Board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
++++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
+@@ -12,6 +12,7 @@
+ 
+ / {
+ 	model = "Mediatek X20 Development Board";
++	chassis-type = "embedded";
+ 	compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -15,6 +15,7 @@
+ 
+ / {
+ 	model = "Bananapi BPI-R64";
++	chassis-type = "embedded";
+ 	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -15,6 +15,7 @@
+ 
+ / {
+ 	model = "MediaTek MT7622 RFB1 board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -16,6 +16,7 @@
+ 
+ / {
+ 	model = "Bananapi BPI-R3";
++	chassis-type = "embedded";
+ 	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
+@@ -11,6 +11,7 @@
+ 
+ / {
+ 	model = "MediaTek MT7986a RFB";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek MT7986b RFB";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
+@@ -11,6 +11,7 @@
+ 
+ / {
+ 	model = "Pumpkin MT8167";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";
+ 
+ 	memory@40000000 {
+--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
+@@ -8,6 +8,7 @@
+ 
+ / {
+ 	model = "Google Hanawl";
++	chassis-type = "laptop";
+ 	compatible = "google,hana-rev7", "mediatek,mt8173";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
+@@ -8,6 +8,7 @@
+ 
+ / {
+ 	model = "Google Hana";
++	chassis-type = "laptop";
+ 	compatible = "google,hana-rev6", "google,hana-rev5",
+ 		     "google,hana-rev4", "google,hana-rev3",
+ 		     "google,hana", "mediatek,mt8173";
+--- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
+@@ -8,6 +8,7 @@
+ 
+ / {
+ 	model = "Google Elm";
++	chassis-type = "laptop";
+ 	compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",
+ 		     "google,elm-rev5", "google,elm-rev4", "google,elm-rev3",
+ 		     "google,elm", "mediatek,mt8173";
+--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+@@ -10,6 +10,7 @@
+ 
+ / {
+ 	model = "MediaTek MT8173 evaluation board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+@@ -11,6 +11,7 @@
+ 
+ / {
+ 	model = "MediaTek MT8183 evaluation board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
+ 
+ 	aliases {
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "Google burnet board";
++	chassis-type = "convertible";
+ 	compatible = "google,burnet", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "Google damu board";
++	chassis-type = "convertible";
+ 	compatible = "google,damu", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "Google juniper sku16 board";
++	chassis-type = "convertible";
+ 	compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek kakadu board sku22";
++	chassis-type = "tablet";
+ 	compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",
+ 		     "google,kakadu", "mediatek,mt8183";
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
+@@ -9,6 +9,7 @@
+ 
+ / {
+ 	model = "MediaTek kakadu board";
++	chassis-type = "tablet";
+ 	compatible = "google,kakadu-rev3", "google,kakadu-rev2",
+ 			"google,kakadu", "mediatek,mt8183";
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
+@@ -12,6 +12,7 @@
+ 
+ / {
+ 	model = "MediaTek kodama sku16 board";
++	chassis-type = "tablet";
+ 	compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
+@@ -12,6 +12,7 @@
+ 
+ / {
+ 	model = "MediaTek kodama sku272 board";
++	chassis-type = "tablet";
+ 	compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
+@@ -12,6 +12,7 @@
+ 
+ / {
+ 	model = "MediaTek kodama sku288 board";
++	chassis-type = "tablet";
+ 	compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
+@@ -14,6 +14,7 @@
+ 
+ / {
+ 	model = "MediaTek krane sku0 board";
++	chassis-type = "tablet";
+ 	compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
+@@ -14,6 +14,7 @@
+ 
+ / {
+ 	model = "MediaTek krane sku176 board";
++	chassis-type = "tablet";
+ 	compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
+ };
+ 
+--- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
++++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
+@@ -7,6 +7,7 @@
+ 
+ / {
+ 	model = "MediaTek MT8186 evaluation board";
++	chassis-type = "embedded";
+ 	compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
+ 
+ 	aliases {

target/linux/mediatek/patches-6.6/012-v6.5-arm64-dts-mt7986-add-PWM.patch

@@ -0,0 +1,38 @@
+From 3b92c547e3d4a35c6214b3e7fa1103d0749d83b1 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Fri, 21 Apr 2023 15:20:44 +0200
+Subject: [PATCH 12/19] arm64: dts: mt7986: add PWM
+
+This adds pwm node to mt7986.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -240,6 +240,20 @@
+ 			status = "disabled";
+ 		};
+ 
++		pwm: pwm@10048000 {
++			compatible = "mediatek,mt7986-pwm";
++			reg = <0 0x10048000 0 0x1000>;
++			#clock-cells = <1>;
++			#pwm-cells = <2>;
++			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&topckgen CLK_TOP_PWM_SEL>,
++				 <&infracfg CLK_INFRA_PWM_STA>,
++				 <&infracfg CLK_INFRA_PWM1_CK>,
++				 <&infracfg CLK_INFRA_PWM2_CK>;
++			clock-names = "top", "main", "pwm1", "pwm2";
++			status = "disabled";
++		};
++
+ 		uart0: serial@11002000 {
+ 			compatible = "mediatek,mt7986-uart",
+ 				     "mediatek,mt6577-uart";

target/linux/mediatek/patches-6.6/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch

@@ -0,0 +1,43 @@
+From 35e482bb599df010b4869017ff576dbb7a4d4c2e Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Fri, 21 Apr 2023 15:20:45 +0200
+Subject: [PATCH 13/19] arm64: dts: mt7986: add PWM to BPI-R3
+
+Add pwm node and pinctrl to BananaPi R3 devicetree.
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts   | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -275,6 +275,13 @@
+ 		};
+ 	};
+ 
++	pwm_pins: pwm-pins {
++		mux {
++			function = "pwm";
++			groups = "pwm0", "pwm1_0";
++		};
++	};
++
+ 	spi_flash_pins: spi-flash-pins {
+ 		mux {
+ 			function = "spi";
+@@ -345,6 +352,12 @@
+ 	};
+ };
+ 
++&pwm {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm_pins>;
++	status = "okay";
++};
++
+ &spi0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spi_flash_pins>;

target/linux/mediatek/patches-6.6/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch

@@ -0,0 +1,27 @@
+From ccdda5714446db8690505371442f7807f5d7c6fc Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Sun, 5 Feb 2023 18:48:33 +0100
+Subject: [PATCH 14/19] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3
+
+Leds for Wifi are low-active, so add property to devicetree.
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -460,5 +460,9 @@
+ 	pinctrl-names = "default", "dbdc";
+ 	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
+ 	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
++
++	led {
++		led-active-low;
++	};
+ };
+ 

target/linux/mediatek/patches-6.6/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch

@@ -0,0 +1,46 @@
+From 1423b4b780adcf3994e63a5988a62d5d1d509bb1 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Sun, 28 May 2023 13:33:42 +0200
+Subject: [PATCH 15/19] arm64: dts: mt7986: use size of reserved partition for
+ bl2
+
+To store uncompressed bl2 more space is required than partition is
+actually defined.
+
+There is currently no known usage of this reserved partition.
+Openwrt uses same partition layout.
+
+We added same change to u-boot with commit d7bb1099 [1].
+
+[1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e
+
+Cc: [email protected]
+Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso     | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -27,15 +27,10 @@
+ 
+ 					partition@0 {
+ 						label = "bl2";
+-						reg = <0x0 0x20000>;
++						reg = <0x0 0x40000>;
+ 						read-only;
+ 					};
+ 
+-					partition@20000 {
+-						label = "reserved";
+-						reg = <0x20000 0x20000>;
+-					};
+-
+ 					partition@40000 {
+ 						label = "u-boot-env";
+ 						reg = <0x40000 0x40000>;

target/linux/mediatek/patches-6.6/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch

@@ -0,0 +1,80 @@
+From 40a5a767d698ef7a71f8be851ea18b0a7a8b47bd Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Tue, 30 May 2023 22:12:33 +0200
+Subject: [PATCH 16/19] arm64: dts: mt7986: add thermal and efuse
+
+Add thermal related nodes to mt7986 devicetree.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++-
+ 1 file changed, 35 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -337,6 +337,15 @@
+ 			status = "disabled";
+ 		};
+ 
++		auxadc: adc@1100d000 {
++			compatible = "mediatek,mt7986-auxadc";
++			reg = <0 0x1100d000 0 0x1000>;
++			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
++			clock-names = "main";
++			#io-channel-cells = <1>;
++			status = "disabled";
++		};
++
+ 		ssusb: usb@11200000 {
+ 			compatible = "mediatek,mt7986-xhci",
+ 				     "mediatek,mtk-xhci";
+@@ -375,6 +384,21 @@
+ 			status = "disabled";
+ 		};
+ 
++		thermal: thermal@1100c800 {
++			#thermal-sensor-cells = <1>;
++			compatible = "mediatek,mt7986-thermal";
++			reg = <0 0x1100c800 0 0x800>;
++			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&infracfg CLK_INFRA_THERM_CK>,
++				 <&infracfg CLK_INFRA_ADC_26M_CK>,
++				 <&infracfg CLK_INFRA_ADC_FRC_CK>;
++			clock-names = "therm", "auxadc", "adc_32k";
++			mediatek,auxadc = <&auxadc>;
++			mediatek,apmixedsys = <&apmixedsys>;
++			nvmem-cells = <&thermal_calibration>;
++			nvmem-cell-names = "calibration-data";
++		};
++
+ 		pcie: pcie@11280000 {
+ 			compatible = "mediatek,mt7986-pcie",
+ 				     "mediatek,mt8192-pcie";
+@@ -426,6 +450,17 @@
+ 			};
+ 		};
+ 
++		efuse: efuse@11d00000 {
++			compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
++			reg = <0 0x11d00000 0 0x1000>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			thermal_calibration: calib@274 {
++				reg = <0x274 0xc>;
++			};
++		};
++
+ 		usb_phy: t-phy@11e10000 {
+ 			compatible = "mediatek,mt7986-tphy",
+ 				     "mediatek,generic-tphy-v2";
+@@ -567,5 +602,4 @@
+ 			memory-region = <&wmcpu_emi>;
+ 		};
+ 	};
+-
+ };

target/linux/mediatek/patches-6.6/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch

@@ -0,0 +1,51 @@
+From bb78d0cf5117517f1ed296ae71048945d9107675 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Tue, 30 May 2023 22:12:34 +0200
+Subject: [PATCH 17/19] arm64: dts: mt7986: add thermal-zones
+
+Add thermal-zones to mt7986 devicetree.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -602,4 +602,32 @@
+ 			memory-region = <&wmcpu_emi>;
+ 		};
+ 	};
++
++	thermal-zones {
++		cpu_thermal: cpu-thermal {
++			polling-delay-passive = <1000>;
++			polling-delay = <1000>;
++			thermal-sensors = <&thermal 0>;
++
++			trips {
++				cpu_trip_active_high: active-high {
++					temperature = <115000>;
++					hysteresis = <2000>;
++					type = "active";
++				};
++
++				cpu_trip_active_low: active-low {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "active";
++				};
++
++				cpu_trip_passive: passive {
++					temperature = <40000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++			};
++		};
++	};
+ };

target/linux/mediatek/patches-6.6/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch

@@ -0,0 +1,64 @@
+From 5d90603b09e5814ffc38c47e79ccf9bc564f9296 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Tue, 30 May 2023 22:12:35 +0200
+Subject: [PATCH 18/19] arm64: dts: mt7986: add pwm-fan and cooling-maps to
+ BPI-R3 dts
+
+Add pwm-fan and cooling-maps to BananaPi-R3 devicetree.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts  | 31 +++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -38,6 +38,15 @@
+ 		regulator-always-on;
+ 	};
+ 
++	fan: pwm-fan {
++		compatible = "pwm-fan";
++		#cooling-cells = <2>;
++		/* cooling level (0, 1, 2) - pwm inverted */
++		cooling-levels = <255 96 0>;
++		pwms = <&pwm 0 10000 0>;
++		status = "okay";
++	};
++
+ 	gpio-keys {
+ 		compatible = "gpio-keys";
+ 
+@@ -133,6 +142,28 @@
+ 	};
+ };
+ 
++&cpu_thermal {
++	cooling-maps {
++		cpu-active-high {
++			/* active: set fan to cooling level 2 */
++			cooling-device = <&fan 2 2>;
++			trip = <&cpu_trip_active_high>;
++		};
++
++		cpu-active-low {
++			/* active: set fan to cooling level 1 */
++			cooling-device = <&fan 1 1>;
++			trip = <&cpu_trip_active_low>;
++		};
++
++		cpu-passive {
++			/* passive: set fan to cooling level 0 */
++			cooling-device = <&fan 0 0>;
++			trip = <&cpu_trip_passive>;
++		};
++	};
++};
++
+ &crypto {
+ 	status = "okay";
+ };

target/linux/mediatek/patches-6.6/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch

@@ -0,0 +1,41 @@
+From 6dd3b939370094eb79529683be84500f3c757404 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Tue, 6 Jun 2023 16:43:20 +0100
+Subject: [PATCH 19/19] arm64: dts: mt7986: increase bl2 partition on NAND of
+ Bananapi R3
+
+The bootrom burned into the MT7986 SoC will try multiple locations on
+the SPI-NAND flash to load bl2 in case the bl2 image located at the the
+previously attempted offset is corrupt.
+
+Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND,
+allowing for up to four redundant copies of bl2 (typically sized a
+bit less than 0x40000).
+
+Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3")
+Signed-off-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso     | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+@@ -29,13 +29,13 @@
+ 
+ 					partition@0 {
+ 						label = "bl2";
+-						reg = <0x0 0x80000>;
++						reg = <0x0 0x100000>;
+ 						read-only;
+ 					};
+ 
+-					partition@80000 {
++					partition@100000 {
+ 						label = "reserved";
+-						reg = <0x80000 0x300000>;
++						reg = <0x100000 0x280000>;
+ 					};
+ 
+ 					partition@380000 {

target/linux/mediatek/patches-6.6/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch

@@ -0,0 +1,34 @@
+From f8ed4088ed9c61ae92193da6130d04c37e7b19f2 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Sun, 20 Aug 2023 17:31:33 +0200
+Subject: [PATCH 20/22] arm64: dts: mt7986: define 3W max power to both SFP on
+ BPI-R3
+
+All SFP power supplies are connected to the system VDD33 which is 3v3/8A.
+Set 3A per SFP slot to allow SFPs work which need more power than the
+default 1W.
+
+Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
+Signed-off-by: Frank Wunderlich <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -126,6 +126,7 @@
+ 		compatible = "sff,sfp";
+ 		i2c-bus = <&i2c_sfp1>;
+ 		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
++		maximum-power-milliwatt = <3000>;
+ 		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
+ 		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+ 		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+@@ -137,6 +138,7 @@
+ 		i2c-bus = <&i2c_sfp2>;
+ 		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
+ 		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
++		maximum-power-milliwatt = <3000>;
+ 		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
+ 		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
+ 	};

target/linux/mediatek/patches-6.6/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch

@@ -0,0 +1,59 @@
+From aa3d6df9803c267725dc72286bb91602b7579882 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Sun, 20 Aug 2023 17:31:34 +0200
+Subject: [PATCH 21/22] arm64: dts: mt7986: change cooling trips
+
+Add Critical and hot trips for emergency system shutdown and limiting
+system load.
+
+Change passive trip to active to make sure fan is activated on the
+lowest trip.
+
+Fixes: 1f5be05132f3 ("arm64: dts: mt7986: add thermal-zones")
+Suggested-by: Daniel Golle <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -610,22 +610,34 @@
+ 			thermal-sensors = <&thermal 0>;
+ 
+ 			trips {
++				cpu_trip_crit: crit {
++					temperature = <125000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++
++				cpu_trip_hot: hot {
++					temperature = <120000>;
++					hysteresis = <2000>;
++					type = "hot";
++				};
++
+ 				cpu_trip_active_high: active-high {
+ 					temperature = <115000>;
+ 					hysteresis = <2000>;
+ 					type = "active";
+ 				};
+ 
+-				cpu_trip_active_low: active-low {
++				cpu_trip_active_med: active-med {
+ 					temperature = <85000>;
+ 					hysteresis = <2000>;
+ 					type = "active";
+ 				};
+ 
+-				cpu_trip_passive: passive {
+-					temperature = <40000>;
++				cpu_trip_active_low: active-low {
++					temperature = <60000>;
+ 					hysteresis = <2000>;
+-					type = "passive";
++					type = "active";
+ 				};
+ 			};
+ 		};

target/linux/mediatek/patches-6.6/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch

@@ -0,0 +1,38 @@
+From 6ddf23526955b8dbedfeaa57e691261fd73f9d4e Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Sun, 20 Aug 2023 17:31:35 +0200
+Subject: [PATCH 22/22] arm64: dts: mt7986: change thermal trips on BPI-R3
+
+Apply new naming after mt7986 thermal trips were changed.
+
+Fixes: c26f779a2295 ("arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts")
+Suggested-by: Daniel Golle <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+---
+ .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts      | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -152,16 +152,16 @@
+ 			trip = <&cpu_trip_active_high>;
+ 		};
+ 
+-		cpu-active-low {
++		cpu-active-med {
+ 			/* active: set fan to cooling level 1 */
+ 			cooling-device = <&fan 1 1>;
+-			trip = <&cpu_trip_active_low>;
++			trip = <&cpu_trip_active_med>;
+ 		};
+ 
+-		cpu-passive {
+-			/* passive: set fan to cooling level 0 */
++		cpu-active-low {
++			/* active: set fan to cooling level 0 */
+ 			cooling-device = <&fan 0 0>;
+-			trip = <&cpu_trip_passive>;
++			trip = <&cpu_trip_active_low>;
+ 		};
+ 	};
+ };

target/linux/mediatek/patches-6.6/041-block-fit-partition-parser.patch

@@ -0,0 +1,216 @@
+From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
+From: OpenWrt community <[email protected]>
+Date: Wed, 13 Jul 2022 13:37:33 +0200
+Subject: [PATCH] kernel: add block fit partition parser
+
+---
+ block/blk.h                     |  2 ++
+ block/partitions/Kconfig        |  7 +++++++
+ block/partitions/Makefile       |  1 +
+ block/partitions/check.h        |  3 +++
+ block/partitions/core.c         | 17 +++++++++++++++++
+ block/partitions/efi.c          |  8 ++++++++
+ block/partitions/efi.h          |  3 +++
+ block/partitions/msdos.c        | 10 ++++++++++
+ drivers/mtd/mtd_blkdevs.c       |  2 ++
+ drivers/mtd/ubi/block.c         |  3 +++
+ include/linux/msdos_partition.h |  1 +
+ 11 files changed, 57 insertions(+)
+
+--- a/block/blk.h
++++ b/block/blk.h
+@@ -414,6 +414,8 @@ void blk_free_ext_minor(unsigned int min
+ #define ADDPART_FLAG_NONE	0
+ #define ADDPART_FLAG_RAID	1
+ #define ADDPART_FLAG_WHOLEDISK	2
++#define ADDPART_FLAG_READONLY	4
++#define ADDPART_FLAG_ROOTDEV	8
+ int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
+ 		sector_t length);
+ int bdev_del_partition(struct gendisk *disk, int partno);
+--- a/block/partitions/Kconfig
++++ b/block/partitions/Kconfig
+@@ -103,6 +103,13 @@ config ATARI_PARTITION
+ 	  Say Y here if you would like to use hard disks under Linux which
+ 	  were partitioned under the Atari OS.
+ 
++config FIT_PARTITION
++	bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
++	default n
++	help
++	  Say Y here if your system needs to mount the filesystem part of
++	  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
++
+ config IBM_PARTITION
+ 	bool "IBM disk label and partition support"
+ 	depends on PARTITION_ADVANCED && S390
+--- a/block/partitions/Makefile
++++ b/block/partitions/Makefile
+@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
+ obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
+ obj-$(CONFIG_ATARI_PARTITION) += atari.o
+ obj-$(CONFIG_AIX_PARTITION) += aix.o
++obj-$(CONFIG_FIT_PARTITION) += fit.o
+ obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
+ obj-$(CONFIG_MAC_PARTITION) += mac.o
+ obj-$(CONFIG_LDM_PARTITION) += ldm.o
+--- a/block/partitions/check.h
++++ b/block/partitions/check.h
+@@ -57,6 +57,7 @@ int amiga_partition(struct parsed_partit
+ int atari_partition(struct parsed_partitions *state);
+ int cmdline_partition(struct parsed_partitions *state);
+ int efi_partition(struct parsed_partitions *state);
++int fit_partition(struct parsed_partitions *state);
+ int ibm_partition(struct parsed_partitions *);
+ int karma_partition(struct parsed_partitions *state);
+ int ldm_partition(struct parsed_partitions *state);
+@@ -67,3 +68,5 @@ int sgi_partition(struct parsed_partitio
+ int sun_partition(struct parsed_partitions *state);
+ int sysv68_partition(struct parsed_partitions *state);
+ int ultrix_partition(struct parsed_partitions *state);
++
++int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
+--- a/block/partitions/core.c
++++ b/block/partitions/core.c
+@@ -11,6 +11,9 @@
+ #include <linux/vmalloc.h>
+ #include <linux/raid/detect.h>
+ #include <linux/property.h>
++#ifdef CONFIG_FIT_PARTITION
++#include <linux/root_dev.h>
++#endif
+ 
+ #include "check.h"
+ 
+@@ -48,6 +51,9 @@ static int (*check_part[])(struct parsed
+ #ifdef CONFIG_EFI_PARTITION
+ 	efi_partition,		/* this must come before msdos */
+ #endif
++#ifdef CONFIG_FIT_PARTITION
++	fit_partition,
++#endif
+ #ifdef CONFIG_SGI_PARTITION
+ 	sgi_partition,
+ #endif
+@@ -439,6 +445,11 @@ static struct block_device *add_partitio
+ 			goto out_del;
+ 	}
+ 
++#ifdef CONFIG_FIT_PARTITION
++	if (flags & ADDPART_FLAG_READONLY)
++		bdev->bd_read_only = true;
++#endif
++
+ 	/* everything is up and running, commence */
+ 	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
+ 	if (err)
+@@ -631,6 +642,11 @@ static bool blk_add_partition(struct gen
+ 	    (state->parts[p].flags & ADDPART_FLAG_RAID))
+ 		md_autodetect_dev(part->bd_dev);
+ 
++#ifdef CONFIG_FIT_PARTITION
++	if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
++		ROOT_DEV = part->bd_dev;
++#endif
++
+ 	return true;
+ }
+ 
+--- a/block/partitions/efi.c
++++ b/block/partitions/efi.c
+@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
+ 	gpt_entry *ptes = NULL;
+ 	u32 i;
+ 	unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
++#ifdef CONFIG_FIT_PARTITION
++	u32 extra_slot = 64;
++#endif
+ 
+ 	if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
+ 		kfree(gpt);
+@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
+ 				ARRAY_SIZE(ptes[i].partition_name));
+ 		utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
+ 		state->parts[i + 1].has_info = true;
++#ifdef CONFIG_FIT_PARTITION
++		/* If this is a U-Boot FIT volume it may have subpartitions */
++		if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
++			(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
++#endif
+ 	}
+ 	kfree(ptes);
+ 	kfree(gpt);
+--- a/block/partitions/efi.h
++++ b/block/partitions/efi.h
+@@ -51,6 +51,9 @@
+ #define PARTITION_LINUX_LVM_GUID \
+     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
+               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
++#define PARTITION_LINUX_FIT_GUID \
++    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
++              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
+ 
+ typedef struct _gpt_header {
+ 	__le64 signature;
+--- a/block/partitions/msdos.c
++++ b/block/partitions/msdos.c
+@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
+ #endif /* CONFIG_MINIX_SUBPARTITION */
+ }
+ 
++static void parse_fit_mbr(struct parsed_partitions *state,
++			  sector_t offset, sector_t size, int origin)
++{
++#ifdef CONFIG_FIT_PARTITION
++	u32 extra_slot = 64;
++	(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
++#endif /* CONFIG_FIT_PARTITION */
++}
++
+ static struct {
+ 	unsigned char id;
+ 	void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
+@@ -575,6 +584,7 @@ static struct {
+ 	{UNIXWARE_PARTITION, parse_unixware},
+ 	{SOLARIS_X86_PARTITION, parse_solaris_x86},
+ 	{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
++	{FIT_PARTITION, parse_fit_mbr},
+ 	{0, NULL},
+ };
+ 
+--- a/drivers/mtd/mtd_blkdevs.c
++++ b/drivers/mtd/mtd_blkdevs.c
+@@ -359,7 +359,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt
+ 	} else {
+ 		snprintf(gd->disk_name, sizeof(gd->disk_name),
+ 			 "%s%d", tr->name, new->devnum);
+-		gd->flags |= GENHD_FL_NO_PART;
++
++		if (!IS_ENABLED(CONFIG_FIT_PARTITION) || mtd_type_is_nand(new->mtd))
++			gd->flags |= GENHD_FL_NO_PART;
+ 	}
+ 
+ 	set_capacity(gd, ((u64)new->size * tr->blksize) >> 9);
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -432,7 +432,9 @@ int ubiblock_create(struct ubi_volume_in
+ 		ret = -ENODEV;
+ 		goto out_cleanup_disk;
+ 	}
+-	gd->flags |= GENHD_FL_NO_PART;
++	if (!IS_ENABLED(CONFIG_FIT_PARTITION))
++		gd->flags |= GENHD_FL_NO_PART;
++
+ 	gd->private_data = dev;
+ 	sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
+ 	set_capacity(gd, disk_capacity);
+--- a/include/linux/msdos_partition.h
++++ b/include/linux/msdos_partition.h
+@@ -31,6 +31,7 @@ enum msdos_sys_ind {
+ 	LINUX_LVM_PARTITION = 0x8e,
+ 	LINUX_RAID_PARTITION = 0xfd,	/* autodetect RAID partition */
+ 
++	FIT_PARTITION = 0x2e,		/* U-Boot uImage.FIT */
+ 	SOLARIS_X86_PARTITION =	0x82,	/* also Linux swap partitions */
+ 	NEW_SOLARIS_X86_PARTITION = 0xbf,
+ 

target/linux/mediatek/patches-6.6/100-dts-update-mt7622-rfb1.patch

@@ -0,0 +1,107 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -1,7 +1,6 @@
+ /*
+- * Copyright (c) 2017 MediaTek Inc.
+- * Author: Ming Huang <[email protected]>
+- *	   Sean Wang <[email protected]>
++ * Copyright (c) 2018 MediaTek Inc.
++ * Author: Ryder Lee <[email protected]>
+  *
+  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+  */
+@@ -24,7 +23,7 @@
+ 
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+-		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
++		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
+ 	};
+ 
+ 	cpus {
+@@ -45,18 +44,18 @@
+ 		key-factory {
+ 			label = "factory";
+ 			linux,code = <BTN_0>;
+-			gpios = <&pio 0 0>;
++			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ 		};
+ 
+ 		key-wps {
+ 			label = "wps";
+ 			linux,code = <KEY_WPS_BUTTON>;
+-			gpios = <&pio 102 0>;
++			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
+ 		};
+ 	};
+ 
+ 	memory@40000000 {
+-		reg = <0 0x40000000 0 0x20000000>;
++		reg = <0 0x40000000 0 0x40000000>;
+ 	};
+ 
+ 	reg_1p8v: regulator-1p8v {
+@@ -132,22 +131,22 @@
+ 
+ 				port@0 {
+ 					reg = <0>;
+-					label = "lan0";
++					label = "lan1";
+ 				};
+ 
+ 				port@1 {
+ 					reg = <1>;
+-					label = "lan1";
++					label = "lan2";
+ 				};
+ 
+ 				port@2 {
+ 					reg = <2>;
+-					label = "lan2";
++					label = "lan3";
+ 				};
+ 
+ 				port@3 {
+ 					reg = <3>;
+-					label = "lan3";
++					label = "lan4";
+ 				};
+ 
+ 				port@4 {
+@@ -240,7 +239,22 @@
+ 	status = "okay";
+ };
+ 
++&pcie1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie1_pins>;
++	status = "okay";
++};
++
+ &pio {
++	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
++	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
++	 */
++	asm_sel {
++		gpio-hog;
++		gpios = <90 GPIO_ACTIVE_HIGH>;
++		output-high;
++	};
++
+ 	/* eMMC is shared pin with parallel NAND */
+ 	emmc_pins_default: emmc-pins-default {
+ 		mux {
+@@ -517,11 +531,11 @@
+ };
+ 
+ &sata {
+-	status = "okay";
++	status = "disabled";
+ };
+ 
+ &sata_phy {
+-	status = "okay";
++	status = "disabled";
+ };
+ 
+ &spi0 {

target/linux/mediatek/patches-6.6/101-dts-update-mt7629-rfb.patch

@@ -0,0 +1,60 @@
+--- a/arch/arm/boot/dts/mt7629-rfb.dts
++++ b/arch/arm/boot/dts/mt7629-rfb.dts
+@@ -18,6 +18,7 @@
+ 
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
++		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
+ 	};
+ 
+ 	gpio-keys {
+@@ -70,6 +71,10 @@
+ 		compatible = "mediatek,eth-mac";
+ 		reg = <0>;
+ 		phy-mode = "2500base-x";
++
++		nvmem-cells = <&macaddr_factory_2a>;
++		nvmem-cell-names = "mac-address";
++
+ 		fixed-link {
+ 			speed = <2500>;
+ 			full-duplex;
+@@ -82,6 +87,9 @@
+ 		reg = <1>;
+ 		phy-mode = "gmii";
+ 		phy-handle = <&phy0>;
++
++		nvmem-cells = <&macaddr_factory_24>;
++		nvmem-cell-names = "mac-address";
+ 	};
+ 
+ 	mdio: mdio-bus {
+@@ -133,8 +141,9 @@
+ 			};
+ 
+ 			partition@b0000 {
+-				label = "kernel";
++				label = "firmware";
+ 				reg = <0xb0000 0xb50000>;
++				compatible = "denx,fit";
+ 			};
+ 		};
+ 	};
+@@ -273,3 +282,17 @@
+ 	pinctrl-0 = <&watchdog_pins>;
+ 	status = "okay";
+ };
++
++&factory {
++	compatible = "nvmem-cells";
++	#address-cells = <1>;
++	#size-cells = <1>;
++
++	macaddr_factory_24: macaddr@24 {
++		reg = <0x24 0x6>;
++	};
++
++	macaddr_factory_2a: macaddr@2a {
++		reg = <0x2a 0x6>;
++	};
++};

target/linux/mediatek/patches-6.6/103-mt7623-enable-arch-timer.patch

@@ -0,0 +1,20 @@
+From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001
+From: Chuanhong Guo <[email protected]>
+Date: Fri, 29 Apr 2022 10:40:56 +0800
+Subject: [PATCH] arm: mediatek: select arch timer for mt7623
+
+Signed-off-by: Chuanhong Guo <[email protected]>
+---
+ arch/arm/mach-mediatek/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/mach-mediatek/Kconfig
++++ b/arch/arm/mach-mediatek/Kconfig
+@@ -26,6 +26,7 @@ config MACH_MT6592
+ config MACH_MT7623
+ 	bool "MediaTek MT7623 SoCs support"
+ 	default ARCH_MEDIATEK
++	select HAVE_ARM_ARCH_TIMER
+ 
+ config MACH_MT7629
+ 	bool "MediaTek MT7629 SoCs support"

target/linux/mediatek/patches-6.6/104-mt7622-add-snor-irq.patch

@@ -0,0 +1,10 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -578,6 +578,7 @@
+ 		compatible = "mediatek,mt7622-nor",
+ 			     "mediatek,mt8173-nor";
+ 		reg = <0 0x11014000 0 0xe0>;
++		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
+ 		clocks = <&pericfg CLK_PERI_FLASH_PD>,
+ 			 <&topckgen CLK_TOP_FLASH_SEL>;
+ 		clock-names = "spi", "sf";

target/linux/mediatek/patches-6.6/105-dts-mt7622-enable-pstore.patch

@@ -0,0 +1,16 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -134,6 +134,13 @@
+ 		#size-cells = <2>;
+ 		ranges;
+ 
++		/* 64 KiB reserved for ramoops/pstore */
++		ramoops@42ff0000 {
++			compatible = "ramoops";
++			reg = <0 0x42ff0000 0 0x10000>;
++			record-size = <0x1000>;
++		};
++
+ 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ 		secmon_reserved: secmon@43000000 {
+ 			reg = <0 0x43000000 0 0x30000>;

target/linux/mediatek/patches-6.6/106-dts-mt7622-disable_btif.patch

@@ -0,0 +1,26 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -108,10 +108,6 @@
+ 	status = "disabled";
+ };
+ 
+-&btif {
+-	status = "okay";
+-};
+-
+ &cir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&irrx_pins>;
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -89,10 +89,6 @@
+ 	status = "disabled";
+ };
+ 
+-&btif {
+-	status = "okay";
+-};
+-
+ &cir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&irrx_pins>;

target/linux/mediatek/patches-6.6/110-dts-fix-bpi2-console.patch

@@ -0,0 +1,10 @@
+--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+@@ -19,6 +19,7 @@
+ 
+ 	chosen {
+ 		stdout-path = "serial2:115200n8";
++		bootargs = "console=ttyS2,115200n8 console=tty1";
+ 	};
+ 
+ 	connector {

target/linux/mediatek/patches-6.6/111-dts-fix-bpi64-console.patch

@@ -0,0 +1,11 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -24,7 +24,7 @@
+ 
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+-		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
++		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
+ 	};
+ 
+ 	cpus {

target/linux/mediatek/patches-6.6/112-dts-fix-bpi64-lan-names.patch

@@ -0,0 +1,37 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -20,6 +20,7 @@
+ 
+ 	aliases {
+ 		serial0 = &uart0;
++		ethernet0 = &gmac0;
+ 	};
+ 
+ 	chosen {
+@@ -160,22 +161,22 @@
+ 
+ 				port@1 {
+ 					reg = <1>;
+-					label = "lan0";
++					label = "lan1";
+ 				};
+ 
+ 				port@2 {
+ 					reg = <2>;
+-					label = "lan1";
++					label = "lan2";
+ 				};
+ 
+ 				port@3 {
+ 					reg = <3>;
+-					label = "lan2";
++					label = "lan3";
+ 				};
+ 
+ 				port@4 {
+ 					reg = <4>;
+-					label = "lan3";
++					label = "lan4";
+ 				};
+ 
+ 				port@6 {

target/linux/mediatek/patches-6.6/113-dts-fix-bpi64-leds-and-buttons.patch

@@ -0,0 +1,49 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -21,6 +21,12 @@
+ 	aliases {
+ 		serial0 = &uart0;
+ 		ethernet0 = &gmac0;
++		led-boot = &led_system_green;
++		led-failsafe = &led_system_blue;
++		led-running = &led_system_green;
++		led-upgrade = &led_system_blue;
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
+ 	};
+ 
+ 	chosen {
+@@ -44,8 +50,8 @@
+ 		compatible = "gpio-keys";
+ 
+ 		factory-key {
+-			label = "factory";
+-			linux,code = <BTN_0>;
++			label = "reset";
++			linux,code = <KEY_RESTART>;
+ 			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+ 		};
+ 
+@@ -59,17 +65,17 @@
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+-		led-0 {
++		led_system_green: led-0 {
+ 			label = "bpi-r64:pio:green";
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
+ 			default-state = "off";
+ 		};
+ 
+-		led-1 {
+-			label = "bpi-r64:pio:red";
+-			color = <LED_COLOR_ID_RED>;
+-			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
++		led_system_blue: led-1 {
++			label = "bpi-r64:pio:blue";
++			color = <LED_COLOR_ID_BLUE>;
++			gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
+ 			default-state = "off";
+ 		};
+ 	};

target/linux/mediatek/patches-6.6/114-dts-bpi64-disable-rtc.patch

@@ -0,0 +1,21 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -556,12 +556,16 @@
+ 	status = "okay";
+ };
+ 
++&rtc {
++	status = "disabled";
++};
++
+ &sata {
+-	status = "disable";
++	status = "disabled";
+ };
+ 
+ &sata_phy {
+-	status = "disable";
++	status = "disabled";
+ };
+ 
+ &spi0 {

target/linux/mediatek/patches-6.6/115-v6.5-arm64-dts-mt7622-declare-SPI-NAND-present-on-BPI-R64.patch

@@ -0,0 +1,70 @@
+From d278f43f25beedfd0cb784d1dd0a9e7e8c8f123f Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Wed, 19 Apr 2023 20:15:53 +0100
+Subject: [PATCH] arm64: dts: mt7622: declare SPI-NAND present on BPI-R64
+
+The SPI-NOR node in the device tree of the BananaPi R64 has most likely
+been copied from the reference board's device tree even though the R64
+comes with an SPI-NAND chip rather than SPI-NOR.
+
+Setup the Serial NAND Flash Interface (SNFI) controller, enable
+hardware BCH error detection and correction engine and add the SPI-NAND
+chip including basic partitions,
+
+Signed-off-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ .../dts/mediatek/mt7622-bananapi-bpi-r64.dts  | 38 ++++++++++++++++---
+ 1 file changed, 33 insertions(+), 5 deletions(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -253,14 +253,42 @@
+ 	status = "disabled";
+ };
+ 
+-&nor_flash {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&spi_nor_pins>;
+-	status = "disabled";
++&bch {
++	status = "okay";
++};
+ 
++&snfi {
++	pinctrl-names = "default";
++	pinctrl-0 = <&serial_nand_pins>;
++	status = "okay";
+ 	flash@0 {
+-		compatible = "jedec,spi-nor";
++		compatible = "spi-nand";
+ 		reg = <0>;
++		spi-tx-bus-width = <4>;
++		spi-rx-bus-width = <4>;
++		nand-ecc-engine = <&snfi>;
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "bl2";
++				reg = <0x0 0x80000>;
++				read-only;
++			};
++
++			partition@80000 {
++				label = "fip";
++				reg = <0x80000 0x200000>;
++				read-only;
++			};
++
++			ubi: partition@280000 {
++				label = "ubi";
++				reg = <0x280000 0x7d80000>;
++			};
++		};
+ 	};
+ };
+ 

target/linux/mediatek/patches-6.6/121-hack-spi-nand-1b-bbm.patch

@@ -0,0 +1,20 @@
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_
+ static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
+ {
+ 	struct spinand_device *spinand = nand_to_spinand(nand);
+-	u8 marker[2] = { };
++	u8 marker[1] = { };
+ 	struct nand_page_io_req req = {
+ 		.pos = *pos,
+ 		.ooblen = sizeof(marker),
+@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de
+ 
+ 	spinand_select_target(spinand, pos->target);
+ 	spinand_read_page(spinand, &req);
+-	if (marker[0] != 0xff || marker[1] != 0xff)
++	if (marker[0] != 0xff)
+ 		return true;
+ 
+ 	return false;

target/linux/mediatek/patches-6.6/130-dts-mt7629-add-snand-support.patch

@@ -0,0 +1,94 @@
+From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
+From: Xiangsheng Hou <[email protected]>
+Date: Thu, 6 Jun 2019 16:29:04 +0800
+Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
+
+Signed-off-by: Xiangsheng Hou <[email protected]>
+---
+ arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/mt7629.dtsi    | 22 ++++++++++++++++
+ 3 files changed, 79 insertions(+)
+
+--- a/arch/arm/boot/dts/mt7629.dtsi
++++ b/arch/arm/boot/dts/mt7629.dtsi
+@@ -272,6 +272,27 @@
+ 			status = "disabled";
+ 		};
+ 
++		snfi: spi@1100d000 {
++			compatible = "mediatek,mt7629-snand";
++			reg = <0x1100d000 0x1000>;
++			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
++			clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
++			clock-names = "nfi_clk", "pad_clk";
++			nand-ecc-engine = <&bch>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++		};
++
++		bch: ecc@1100e000 {
++			compatible = "mediatek,mt7622-ecc";
++			reg = <0x1100e000 0x1000>;
++			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
++			clocks = <&pericfg CLK_PERI_NFIECC_PD>;
++			clock-names = "nfiecc_clk";
++			status = "disabled";
++		};
++
+ 		spi: spi@1100a000 {
+ 			compatible = "mediatek,mt7629-spi",
+ 				     "mediatek,mt7622-spi";
+--- a/arch/arm/boot/dts/mt7629-rfb.dts
++++ b/arch/arm/boot/dts/mt7629-rfb.dts
+@@ -255,6 +255,50 @@
+ 	};
+ };
+ 
++&bch {
++	status = "okay";
++};
++
++&snfi {
++	pinctrl-names = "default";
++	pinctrl-0 = <&serial_nand_pins>;
++	status = "okay";
++	flash@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++		spi-tx-bus-width = <4>;
++		spi-rx-bus-width = <4>;
++		nand-ecc-engine = <&snfi>;
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "Bootloader";
++				reg = <0x00000 0x0100000>;
++				read-only;
++			};
++
++			partition@100000 {
++				label = "Config";
++				reg = <0x100000 0x0040000>;
++			};
++
++			partition@140000 {
++				label = "factory";
++				reg = <0x140000 0x0080000>;
++			};
++
++			partition@1c0000 {
++				label = "firmware";
++				reg = <0x1c0000 0x1000000>;
++			};
++		};
++	};
++};
++
+ &spi {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spi_pins>;

target/linux/mediatek/patches-6.6/131-dts-mt7622-add-snand-support.patch

@@ -0,0 +1,68 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -534,6 +534,65 @@
+ 	status = "disabled";
+ };
+ 
++&bch {
++	status = "okay";
++};
++
++&snfi {
++	pinctrl-names = "default";
++	pinctrl-0 = <&serial_nand_pins>;
++	status = "okay";
++	flash@0 {
++		compatible = "spi-nand";
++		reg = <0>;
++		spi-tx-bus-width = <4>;
++		spi-rx-bus-width = <4>;
++		nand-ecc-engine = <&snfi>;
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "Preloader";
++				reg = <0x00000 0x0080000>;
++				read-only;
++			};
++
++			partition@80000 {
++				label = "ATF";
++				reg = <0x80000 0x0040000>;
++			};
++
++			partition@c0000 {
++				label = "Bootloader";
++				reg = <0xc0000 0x0080000>;
++			};
++
++			partition@140000 {
++				label = "Config";
++				reg = <0x140000 0x0080000>;
++			};
++
++			partition@1c0000 {
++				label = "Factory";
++				reg = <0x1c0000 0x0100000>;
++			};
++
++			partition@200000 {
++				label = "firmware";
++				reg = <0x2c0000 0x2000000>;
++			};
++
++			partition@2200000 {
++				label = "User_data";
++				reg = <0x22c0000 0x4000000>;
++			};
++		};
++	};
++};
++
+ &spi0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spic0_pins>;

target/linux/mediatek/patches-6.6/140-dts-fix-wmac-support-for-mt7622-rfb1.patch

@@ -0,0 +1,18 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -575,7 +575,7 @@
+ 				reg = <0x140000 0x0080000>;
+ 			};
+ 
+-			partition@1c0000 {
++			factory: partition@1c0000 {
+ 				label = "Factory";
+ 				reg = <0x1c0000 0x0100000>;
+ 			};
+@@ -636,5 +636,6 @@
+ &wmac {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&wmac_pins>;
++	mediatek,mtd-eeprom = <&factory 0x0000>;
+ 	status = "okay";
+ };

target/linux/mediatek/patches-6.6/150-dts-mt7623-eip97-inside-secure-support.patch

@@ -0,0 +1,24 @@
+--- a/arch/arm/boot/dts/mt7623.dtsi
++++ b/arch/arm/boot/dts/mt7623.dtsi
+@@ -984,17 +984,15 @@
+ 	};
+ 
+ 	crypto: crypto@1b240000 {
+-		compatible = "mediatek,eip97-crypto";
++		compatible = "inside-secure,safexcel-eip97";
+ 		reg = <0 0x1b240000 0 0x20000>;
+ 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
+ 			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
+ 			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
+-			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
+-			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
++			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-names = "ring0", "ring1", "ring2", "ring3";
+ 		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
+-		clock-names = "cryp";
+-		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+-		status = "disabled";
++		status = "okay";
+ 	};
+ 
+ 	bdpsys: syscon@1c000000 {

target/linux/mediatek/patches-6.6/160-dts-mt7623-bpi-r2-earlycon.patch

@@ -0,0 +1,11 @@
+--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+@@ -19,7 +19,7 @@
+ 
+ 	chosen {
+ 		stdout-path = "serial2:115200n8";
+-		bootargs = "console=ttyS2,115200n8 console=tty1";
++		bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
+ 	};
+ 
+ 	connector {

target/linux/mediatek/patches-6.6/161-dts-mt7623-bpi-r2-mmc-device-order.patch

@@ -0,0 +1,11 @@
+--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+@@ -15,6 +15,8 @@
+ 
+ 	aliases {
+ 		serial2 = &uart2;
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
+ 	};
+ 
+ 	chosen {

target/linux/mediatek/patches-6.6/162-dts-mt7623-bpi-r2-led-aliases.patch

@@ -0,0 +1,29 @@
+--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+@@ -17,6 +17,10 @@
+ 		serial2 = &uart2;
+ 		mmc0 = &mmc0;
+ 		mmc1 = &mmc1;
++		led-boot = &led_system_green;
++		led-failsafe = &led_system_blue;
++		led-running = &led_system_green;
++		led-upgrade = &led_system_blue;
+ 	};
+ 
+ 	chosen {
+@@ -112,13 +116,13 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&led_pins_a>;
+ 
+-		blue {
++		led_system_blue: blue {
+ 			label = "bpi-r2:pio:blue";
+ 			gpios = <&pio 240 GPIO_ACTIVE_LOW>;
+ 			default-state = "off";
+ 		};
+ 
+-		green {
++		led_system_green: green {
+ 			label = "bpi-r2:pio:green";
+ 			gpios = <&pio 241 GPIO_ACTIVE_LOW>;
+ 			default-state = "off";

target/linux/mediatek/patches-6.6/163-dts-mt7623-bpi-r2-ethernet-alias.patch

@@ -0,0 +1,10 @@
+--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+@@ -15,6 +15,7 @@
+ 
+ 	aliases {
+ 		serial2 = &uart2;
++		ethernet0 = &gmac0;
+ 		mmc0 = &mmc0;
+ 		mmc1 = &mmc1;
+ 		led-boot = &led_system_green;

target/linux/mediatek/patches-6.6/164-dts-mt7623-bpi-r2-rootdisk-for-fitblk.patch

@@ -0,0 +1,55 @@
+--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
++++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+@@ -26,7 +26,9 @@
+ 
+ 	chosen {
+ 		stdout-path = "serial2:115200n8";
+-		bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
++		bootargs = "root=/dev/fit0 earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
++		rootdisk-emmc = <&emmc_rootdisk>;
++		rootdisk-sd = <&sd_rootdisk>;
+ 	};
+ 
+ 	connector {
+@@ -315,6 +317,20 @@
+ 	vmmc-supply = <&reg_3p3v>;
+ 	vqmmc-supply = <&reg_1p8v>;
+ 	non-removable;
++
++	card@0 {
++		compatible = "mmc-card";
++		reg = <0>;
++
++		block {
++			compatible = "block-device";
++			partitions {
++				emmc_rootdisk: block-partition-fit {
++					partno = <3>;
++				};
++			};
++		};
++	};
+ };
+ 
+ &mmc1 {
+@@ -328,6 +344,20 @@
+ 	cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
+ 	vmmc-supply = <&reg_3p3v>;
+ 	vqmmc-supply = <&reg_3p3v>;
++
++	card@0 {
++		compatible = "mmc-card";
++		reg = <0>;
++
++		block {
++			compatible = "block-device";
++			partitions {
++				sd_rootdisk: block-partition-fit {
++					partno = <3>;
++				};
++			};
++		};
++	};
+ };
+ 
+ &mt6323_leds {

target/linux/mediatek/patches-6.6/180-v6.5-arm64-dts-mt7622-handle-interrupts-from-MT7531-switc.patch

@@ -0,0 +1,32 @@
+From 983f37ee08acb60435744f1b1e2afea2d2a09c48 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Wed, 19 Apr 2023 20:16:29 +0100
+Subject: [PATCH] arm64: dts: mt7622: handle interrupts from MT7531 switch on
+ BPI-R64
+
+Since commit ba751e28d442 ("net: dsa: mt7530: add interrupt support")
+the mt7530 driver can act as an interrupt controller. Wire up irq line
+of the MT7531 switch on the BananaPi BPi-R64 board, so the status of
+the PHYs of the five 1000Base-T ports doesn't need to be polled any
+more.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Matthias Brugger <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -154,6 +154,10 @@
+ 		switch@0 {
+ 			compatible = "mediatek,mt7531";
+ 			reg = <0>;
++			interrupt-controller;
++			#interrupt-cells = <1>;
++			interrupt-parent = <&pio>;
++			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ 			reset-gpios = <&pio 54 0>;
+ 
+ 			ports {

target/linux/mediatek/patches-6.6/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch

@@ -0,0 +1,106 @@
+From patchwork Tue Apr 26 19:51:36 2022
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <[email protected]>
+X-Patchwork-Id: 12827872
+Return-Path: 
+ <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>
+X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
+	aws-us-west-2-korg-lkml-1.web.codeaurora.org
+Received: from bombadil.infradead.org (bombadil.infradead.org
+ [198.137.202.133])
+	(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
+	(No client certificate requested)
+	by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF
+	for <[email protected]>;
+ Tue, 26 Apr 2022 19:53:05 +0000 (UTC)
+DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
+	d=lists.infradead.org; s=bombadil.20210309; h=Sender:
+	Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:
+	List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To:
+	From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:
+	Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:
+	List-Owner; bh=OWGSxvlKoyPWz6b629RNINucULo6oOdFssAIiJETWRg=; b=T0HEjee0FX3hlb
+	x5jl7xLK5sKM0pkE2oRgwzthbFlNg8ST1j/2GkgcgT0S2Bi0vRfFxHeu/RKzS9RmiVnKJnPGL8ctg
+	WoBLyO5i+NcmosGoy6MmoOjGTNhj/+3q3Z1jRLBSJ4ySSP22X77YeuJTmVzySPUllQhWvDhjMVCR9
+	QBRmQdc6gCAg3IYGEbWwS2TG+UHveDCeZRWxMzrwI8UPadNCRFROwugmiQ3mdU41lHCTDpnlfuRJh
+	o1igLKfMBLz+D8rFYvDh7FfkcKkY6lNoswA2HKUun1MEzgoyQKmITPnG2maX/BvJJuj/B3ZJShh4k
+	AZHmXoQxq1mrsm2FxfnQ==;
+Received: from localhost ([::1] helo=bombadil.infradead.org)
+	by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux))
+	id 1njRE5-00G05D-9z; Tue, 26 Apr 2022 19:51:57 +0000
+Received: from fudo.makrotopia.org ([2a07:2ec0:3002::71])
+ by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux))
+ id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000
+Received: from local
+ by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256)
+ (Exim 4.94.2) (envelope-from <[email protected]>)
+ id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200
+Date: Tue, 26 Apr 2022 20:51:36 +0100
+From: Daniel Golle <[email protected]>
+To: [email protected], [email protected],
+ [email protected], [email protected]
+Cc: Rob Herring <[email protected]>,
+ Krzysztof Kozlowski <[email protected]>,
+ Matthias Brugger <[email protected]>
+Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
+Message-ID: <YmhNSLgp/[email protected]>
+MIME-Version: 1.0
+Content-Disposition: inline
+X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 
+X-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C 
+X-CRM114-Status: GOOD (  12.45  )
+X-BeenThere: [email protected]
+X-Mailman-Version: 2.1.34
+Precedence: list
+List-Id: <linux-arm-kernel.lists.infradead.org>
+List-Unsubscribe: 
+ <http://lists.infradead.org/mailman/options/linux-arm-kernel>,
+ <mailto:[email protected]?subject=unsubscribe>
+List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>
+List-Post: <mailto:[email protected]>
+List-Help: <mailto:[email protected]?subject=help>
+List-Subscribe: 
+ <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,
+ <mailto:[email protected]?subject=subscribe>
+Sender: "linux-arm-kernel" <[email protected]>
+Errors-To: 
+ linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
+
+With the current range specified for the CPU interface there is an
+error message at boot:
+
+GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
+
+Setting irqchip.gicv2_force_probe=1 in bootargs results in:
+
+GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
+GIC: Adjusting CPU interface base to 0x000000001032f000
+GIC: Using split EOI/Deactivate mode
+
+Using the adjusted CPU interface base and 8K size results in only the
+final line remaining and fully working system as well as /proc/interrupts
+showing additional IPI3,4,5,6:
+
+IPI3:         0          0       CPU stop (for crash dump) interrupts
+IPI4:         0          0       Timer broadcast interrupts
+IPI5:         0          0       IRQ work interrupts
+IPI6:         0          0       CPU wake-up interrupts
+
+Signed-off-by: Daniel Golle <[email protected]>
+---
+ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -346,7 +346,7 @@
+ 		#interrupt-cells = <3>;
+ 		interrupt-parent = <&gic>;
+ 		reg = <0 0x10310000 0 0x1000>,
+-		      <0 0x10320000 0 0x1000>,
++		      <0 0x1032f000 0 0x2000>,
+ 		      <0 0x10340000 0 0x2000>,
+ 		      <0 0x10360000 0 0x2000>;
+ 	};

target/linux/mediatek/patches-6.6/193-dts-mt7623-thermal_zone_fix.patch

@@ -0,0 +1,48 @@
+From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001
+From: Bruno Umuarama <[email protected]>
+Date: Thu, 13 Oct 2022 21:18:21 +0000
+Subject: [PATCH] mediatek: mt7623: fix thermal zone
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Raising the temperatures for passive and active trips. @VA1DER
+proposed at issue 9396 to remove passive trip. This commit relates to
+his suggestion.
+
+Without this patch. the CPU will be throttled all the way down to 98MHz
+if the temperature rises even a degree above the trip point, and it was
+further discovered that if the internal temperature of the device is
+above the first trip point temperature when it boots then it will start
+in a throttled state and even
+$ echo disabled > /sys/class/thermal/thermal_zone0/mode
+will have no effect.
+
+The patch increases the passive trip point and active cooling map. The
+throttling temperature will then be at 77°C and 82°C, which is still a
+low enough temperature for ARM devices to not be in the real danger
+zone, and gives some operational headroom.
+
+Signed-off-by: Bruno Umuarama <[email protected]>
+---
+ arch/arm/boot/dts/mt7623.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/mt7623.dtsi
++++ b/arch/arm/boot/dts/mt7623.dtsi
+@@ -160,13 +160,13 @@
+ 
+ 				trips {
+ 					cpu_passive: cpu-passive {
+-						temperature = <57000>;
++						temperature = <77000>;
+ 						hysteresis = <2000>;
+ 						type = "passive";
+ 					};
+ 
+ 					cpu_active: cpu-active {
+-						temperature = <67000>;
++						temperature = <82000>;
+ 						hysteresis = <2000>;
+ 						type = "active";
+ 					};

target/linux/mediatek/patches-6.6/194-dts-mt7968a-add-ramoops.patch

@@ -0,0 +1,17 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+@@ -68,6 +68,14 @@
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+ 		ranges;
++
++		/* 64 KiB reserved for ramoops/pstore */
++		ramoops@42ff0000 {
++			compatible = "ramoops";
++			reg = <0 0x42ff0000 0 0x10000>;
++			record-size = <0x1000>;
++		};
++
+ 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ 		secmon_reserved: secmon@43000000 {
+ 			reg = <0 0x43000000 0 0x30000>;

target/linux/mediatek/patches-6.6/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch

@@ -0,0 +1,196 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
+@@ -23,6 +23,10 @@
+ 		serial0 = &uart0;
+ 		ethernet0 = &gmac0;
+ 		ethernet1 = &gmac1;
++		led-boot = &green_led;
++		led-failsafe = &green_led;
++		led-running = &green_led;
++		led-upgrade = &blue_led;
+ 	};
+ 
+ 	chosen {
+@@ -419,27 +423,27 @@
+ 
+ 		port@1 {
+ 			reg = <1>;
+-			label = "lan0";
++			label = "lan1";
+ 		};
+ 
+ 		port@2 {
+ 			reg = <2>;
+-			label = "lan1";
++			label = "lan2";
+ 		};
+ 
+ 		port@3 {
+ 			reg = <3>;
+-			label = "lan2";
++			label = "lan3";
+ 		};
+ 
+ 		port@4 {
+ 			reg = <4>;
+-			label = "lan3";
++			label = "lan4";
+ 		};
+ 
+ 		port5: port@5 {
+ 			reg = <5>;
+-			label = "lan4";
++			label = "sfp2";
+ 			phy-mode = "2500base-x";
+ 			sfp = <&sfp2>;
+ 			managed = "in-band-status";
+@@ -490,9 +494,137 @@
+ 
+ &wifi {
+ 	status = "okay";
+-	pinctrl-names = "default", "dbdc";
++	pinctrl-names = "default";
+ 	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
+-	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
++
++	mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
++				0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
++				0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
++				0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
++				0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3
++				0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
++				0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
++				0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
++				0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a
++				0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
++				0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00
++				0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
++				0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb
++				0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
++				0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
++				0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc
++				0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
++				0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
++				0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
++				0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
++				0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
++				0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
++				0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
++				0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300
++				0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00
++				0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000
++				0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011
++				0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000
++				0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800
++				0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600
++				0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000
++				0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026
++				0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000
++				0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700
++				0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
++				0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
++				0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
++				0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
++				0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
++				0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
++				0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
++				0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
++				0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
++				0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
++				0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
++				0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
++				0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
++				0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
++				0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
++				0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
+ 
+ 	led {
+ 		led-active-low;
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -55,6 +55,7 @@
+ 					partition@c00000 {
+ 						label = "fit";
+ 						reg = <0xc00000 0x1400000>;
++						compatible = "denx,fit";
+ 					};
+ 				};
+ 			};

target/linux/mediatek/patches-6.6/196-dts-mt7986a-bpi-r3-use-all-ubi-nand-layout.patch

@@ -0,0 +1,131 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
+@@ -23,7 +23,27 @@
+ 			no-sd;
+ 			no-sdio;
+ 			status = "okay";
++
++			card@0 {
++				compatible = "mmc-card";
++				reg = <0>;
++
++				block {
++					compatible = "block-device";
++					partitions {
++						emmc_rootdisk: block-partition-production {
++							partname = "production";
++						};
++					};
++				};
++			};
+ 		};
+ 	};
+-};
+ 
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-emmc = <&emmc_rootdisk>;
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
+@@ -29,27 +29,30 @@
+ 
+ 					partition@0 {
+ 						label = "bl2";
+-						reg = <0x0 0x100000>;
++						reg = <0x0 0x200000>;
+ 						read-only;
+ 					};
+ 
+-					partition@100000 {
+-						label = "reserved";
+-						reg = <0x100000 0x280000>;
+-					};
+-
+-					partition@380000 {
+-						label = "fip";
+-						reg = <0x380000 0x200000>;
+-						read-only;
+-					};
+-
+-					partition@580000 {
++					partition@200000 {
+ 						label = "ubi";
+-						reg = <0x580000 0x7a80000>;
++						reg = <0x200000 0x7e00000>;
++						compatible = "linux,ubi";
++
++						volumes {
++							nand_rootdisk: ubi-volume-fit {
++								volname = "fit";
++							};
++						};
+ 					};
+ 				};
+ 			};
+ 		};
+ 	};
++
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-spim-nand = <&nand_rootdisk>;
++		};
++	};
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
+@@ -52,7 +52,7 @@
+ 						reg = <0x180000 0xa80000>;
+ 					};
+ 
+-					partition@c00000 {
++					nor_rootdisk: partition@c00000 {
+ 						label = "fit";
+ 						reg = <0xc00000 0x1400000>;
+ 						compatible = "denx,fit";
+@@ -61,4 +61,11 @@
+ 			};
+ 		};
+ 	};
++
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-nor = <&nor_rootdisk>;
++		};
++	};
+ };
+--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
++++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
+@@ -17,6 +17,27 @@
+ 			max-frequency = <52000000>;
+ 			cap-sd-highspeed;
+ 			status = "okay";
++
++			card@0 {
++				compatible = "mmc-card";
++				reg = <0>;
++
++				block {
++					compatible = "block-device";
++					partitions {
++						sd_rootdisk: block-partition-production {
++							partname = "production";
++						};
++					};
++				};
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/chosen";
++		__overlay__ {
++			rootdisk-sd = <&sd_rootdisk>;
+ 		};
+ 	};
+ };

target/linux/mediatek/patches-6.6/200-phy-phy-mtk-tphy-Add-hifsys-support.patch

@@ -0,0 +1,66 @@
+From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
+From: Kristian Evensen <[email protected]>
+Date: Mon, 30 Apr 2018 14:38:01 +0200
+Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
+
+---
+ drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/drivers/phy/mediatek/phy-mtk-tphy.c
++++ b/drivers/phy/mediatek/phy-mtk-tphy.c
+@@ -17,6 +17,8 @@
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++#include <linux/regmap.h>
+ 
+ #include "phy-mtk-io.h"
+ 
+@@ -264,6 +266,9 @@
+ 
+ #define TPHY_CLKS_CNT	2
+ 
++#define HIF_SYSCFG1			0x14
++#define HIF_SYSCFG1_PHY2_MASK		(0x3 << 20)
++
+ enum mtk_phy_version {
+ 	MTK_PHY_V1 = 1,
+ 	MTK_PHY_V2,
+@@ -331,6 +336,7 @@ struct mtk_tphy {
+ 	void __iomem *sif_base;	/* only shared sif */
+ 	const struct mtk_phy_pdata *pdata;
+ 	struct mtk_phy_instance **phys;
++	struct regmap *hif;
+ 	int nphys;
+ 	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
+ 	int src_coef; /* coefficient for slew rate calibrate */
+@@ -596,6 +602,10 @@ static void pcie_phy_instance_init(struc
+ 	if (tphy->pdata->version != MTK_PHY_V1)
+ 		return;
+ 
++	if (tphy->hif)
++		regmap_update_bits(tphy->hif, HIF_SYSCFG1,
++				   HIF_SYSCFG1_PHY2_MASK, 0);
++
+ 	mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
+ 			    P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
+ 			    FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
+@@ -1241,6 +1251,16 @@ static int mtk_tphy_probe(struct platfor
+ 					 &tphy->src_coef);
+ 	}
+ 
++	if (of_find_property(np, "mediatek,phy-switch", NULL)) {
++		tphy->hif = syscon_regmap_lookup_by_phandle(np,
++							    "mediatek,phy-switch");
++		if (IS_ERR(tphy->hif)) {
++			dev_err(&pdev->dev,
++				"missing \"mediatek,phy-switch\" phandle\n");
++			return PTR_ERR(tphy->hif);
++		}
++	}
++
+ 	port = 0;
+ 	for_each_child_of_node(np, child_np) {
+ 		struct mtk_phy_instance *instance;

target/linux/mediatek/patches-6.6/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch

@@ -0,0 +1,88 @@
+From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sat, 8 Oct 2022 18:48:06 +0200
+Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts
+ separately
+
+Some mt7986 boards use uart rts/cts pins as gpio,
+This patch allows to change rts/cts to gpio mode, but keep
+rx/tx as UART function.
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+Signed-off-by: Sam Shih <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++-----
+ 1 file changed, 25 insertions(+), 7 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+@@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4,
+ static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
+ static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
+ 
+-static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
+-static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
++static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
++static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
+ 
+-static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
+-static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
++static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
++static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
++
++static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
++static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
++
++static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
++static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
+ 
+ static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
+ static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
+@@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = {
+ static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
+ static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
+ 
++static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
++static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
++
++static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
++static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
++
+ static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
+ static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
+ 
+@@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr
+ 	PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
+ 	PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
+ 	PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
++	PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
++	PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
+ 	PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
+ 	PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
+ 	PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
+@@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr
+ 	PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
+ 	PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
+ 	PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
+-	PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
+-	PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
++	PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
++	PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
++	PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
++	PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
+ 	PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
+ 	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
+ 	PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
+@@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] =
+ static const char *mt7986_spi_groups[] = {
+ 	"spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
+ static const char *mt7986_uart_groups[] = {
+-	"uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts",
++	"uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
++	"uart1_2_rx_tx", "uart1_2_cts_rts",
++	"uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
+ 	"uart2_0", "uart2_1", "uart0", "uart1", "uart2",
+ };
+ static const char *mt7986_wdt_groups[] = { "watchdog", };

target/linux/mediatek/patches-6.6/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch

@@ -0,0 +1,100 @@
+From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sun, 6 Nov 2022 09:01:13 +0100
+Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek
+ MT7986 SoC
+
+Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
+add SoC specify 'pull_type' attribute for bias configuration.
+
+This patch add pull_type attribute to pinctrl-mt7986.c, and make
+bias_set_combo and bias_get_combo available to mediatek MT7986 SoC.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+@@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m
+ 	PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
+ };
+ 
++static const unsigned int mt7986_pull_type[] = {
++	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
++	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
++	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
++	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
++	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
++	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
++	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
++	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
++	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
++	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
++	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
++	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
++	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
++	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
++	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
++	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
++	MTK_PULL_PU_PD_TYPE,/*100*/
++};
++
+ static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
+ 	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
+ 	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
+@@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data =
+ 	.ies_present = false,
+ 	.base_names = mt7986_pinctrl_register_base_names,
+ 	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
++	.pull_type = mt7986_pull_type,
+ 	.bias_set_combo = mtk_pinconf_bias_set_combo,
+ 	.bias_get_combo = mtk_pinconf_bias_get_combo,
+ 	.drive_set = mtk_pinconf_drive_set_rev1,
+@@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data =
+ 	.ies_present = false,
+ 	.base_names = mt7986_pinctrl_register_base_names,
+ 	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
++	.pull_type = mt7986_pull_type,
+ 	.bias_set_combo = mtk_pinconf_bias_set_combo,
+ 	.bias_get_combo = mtk_pinconf_bias_get_combo,
+ 	.drive_set = mtk_pinconf_drive_set_rev1,

target/linux/mediatek/patches-6.6/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch

@@ -0,0 +1,1094 @@
+From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Thu, 26 Jan 2023 00:34:56 +0000
+Subject: [PATCH] pinctrl: add mt7981 pinctrl driver
+
+Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver
+which can also be found the SDK.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Reviewed-by: Rob Herring <[email protected]>
+Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/mediatek/Kconfig          |    5 +
+ drivers/pinctrl/mediatek/Makefile         |    1 +
+ drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++
+ 3 files changed, 1054 insertions(+)
+ create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c
+
+--- a/drivers/pinctrl/mediatek/Kconfig
++++ b/drivers/pinctrl/mediatek/Kconfig
+@@ -127,6 +127,11 @@ config PINCTRL_MT7622
+ 	default ARM64 && ARCH_MEDIATEK
+ 	select PINCTRL_MTK_MOORE
+ 
++config PINCTRL_MT7981
++	bool "Mediatek MT7981 pin control"
++	depends on OF
++	select PINCTRL_MTK_MOORE
++
+ config PINCTRL_MT7986
+ 	bool "Mediatek MT7986 pin control"
+ 	depends on OF
+--- a/drivers/pinctrl/mediatek/Makefile
++++ b/drivers/pinctrl/mediatek/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-
+ obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
+ obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
+ obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
++obj-$(CONFIG_PINCTRL_MT7981)	+= pinctrl-mt7981.o
+ obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
+ obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
+ obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
+--- /dev/null
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+@@ -0,0 +1,1048 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * The MT7981 driver based on Linux generic pinctrl binding.
++ *
++ * Copyright (C) 2020 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ */
++
++#include "pinctrl-moore.h"
++
++#define MT7981_PIN(_number, _name)				\
++	MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
++
++#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
++	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
++		       _x_bits, 32, 0)
++
++#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)	\
++	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
++		      _x_bits, 32, 1)
++
++static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
++	PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
++	PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
++	PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
++	PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
++	PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
++	PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
++	PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
++	PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
++	PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
++	PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
++	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
++	PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
++	PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
++	PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
++	PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
++	PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
++	PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
++	PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
++	PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
++	PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
++	PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
++	PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
++	PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
++	PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
++	PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
++	PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
++	PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
++	PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
++	PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
++
++	PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
++	PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
++	PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
++	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
++	PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
++	PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
++	PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
++	PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
++	PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
++
++	PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
++	PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
++	PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
++	PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
++	PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
++	PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
++	PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
++	PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
++	PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
++	PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
++	PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
++	PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
++	PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
++	PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
++	PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
++	PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
++	PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
++	PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
++	PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
++	PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
++	PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
++	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
++	PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
++	PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
++	PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
++	PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
++	PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
++	PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
++	PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
++	PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
++	PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
++	PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
++	PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
++	PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
++	PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
++	PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
++	PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
++
++	PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
++	PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
++	PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
++	PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
++	PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
++	PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
++	PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
++	PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
++	PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
++	PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
++
++	PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
++	PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
++	PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
++	PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
++	PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
++	PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
++	PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
++	PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
++	PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
++	PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
++	PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
++	PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
++	PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
++	PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
++	PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
++	PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
++	PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
++
++	PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
++	PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
++	PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
++	PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
++	PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
++	PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
++	PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
++	PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
++	PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
++	PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
++	PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
++	PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
++	PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
++	PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
++
++	PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
++	PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
++	PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
++	PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
++	PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
++	PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
++
++	PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
++
++	PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
++	PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
++	PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
++	PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
++	PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
++	PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
++	PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
++	PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
++	PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
++	PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
++	PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
++	PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
++	PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
++	PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
++	PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
++	PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
++	PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
++
++	PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
++	PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
++	PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
++	PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
++	PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
++	PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
++	PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
++	PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
++
++	PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
++	PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
++	PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
++	PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
++	PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
++	PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
++	PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
++	PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
++	PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
++	PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
++	PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
++	PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
++	PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
++	PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
++	PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
++	PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
++	PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
++	PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
++	PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
++	PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
++	PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
++	PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
++	PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
++	PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
++	PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
++	PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
++	PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
++	PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
++	PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
++	PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
++	PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
++	PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
++	PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
++	PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
++	PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
++	PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
++	PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
++	PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
++	PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
++	PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
++	PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
++	PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
++	PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
++	PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
++	PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
++	PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
++	PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
++	PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
++	PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
++	PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
++	PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
++	PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
++	PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
++	PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
++	PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
++};
++
++static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
++	PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
++	PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
++	PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
++	PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
++	PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
++	PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
++	PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
++	PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
++
++	PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
++	PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
++	PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
++	PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
++	PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
++
++	PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
++	PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
++	PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
++	PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
++	PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
++	PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
++	PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
++	PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
++	PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
++	PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
++	PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
++
++	PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
++	PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
++	PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
++	PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
++	PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
++	PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
++
++	PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
++	PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
++
++	PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
++	PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
++
++	PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
++	PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
++	PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
++	PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
++};
++
++static const unsigned int mt7981_pull_type[] = {
++	MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
++	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
++	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
++	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
++	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
++	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
++	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
++	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
++	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
++	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
++	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
++	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
++	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
++	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
++	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
++	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
++	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
++	MTK_PULL_PU_PD_TYPE,/*100*/
++};
++
++static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
++	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
++	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
++	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
++	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
++	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
++	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
++	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
++	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
++	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
++	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
++	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
++	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
++};
++
++static const struct mtk_pin_desc mt7981_pins[] = {
++	MT7981_PIN(0, "GPIO_WPS"),
++	MT7981_PIN(1, "GPIO_RESET"),
++	MT7981_PIN(2, "SYS_WATCHDOG"),
++	MT7981_PIN(3, "PCIE_PERESET_N"),
++	MT7981_PIN(4, "JTAG_JTDO"),
++	MT7981_PIN(5, "JTAG_JTDI"),
++	MT7981_PIN(6, "JTAG_JTMS"),
++	MT7981_PIN(7, "JTAG_JTCLK"),
++	MT7981_PIN(8, "JTAG_JTRST_N"),
++	MT7981_PIN(9, "WO_JTAG_JTDO"),
++	MT7981_PIN(10, "WO_JTAG_JTDI"),
++	MT7981_PIN(11, "WO_JTAG_JTMS"),
++	MT7981_PIN(12, "WO_JTAG_JTCLK"),
++	MT7981_PIN(13, "WO_JTAG_JTRST_N"),
++	MT7981_PIN(14, "USB_VBUS"),
++	MT7981_PIN(15, "PWM0"),
++	MT7981_PIN(16, "SPI0_CLK"),
++	MT7981_PIN(17, "SPI0_MOSI"),
++	MT7981_PIN(18, "SPI0_MISO"),
++	MT7981_PIN(19, "SPI0_CS"),
++	MT7981_PIN(20, "SPI0_HOLD"),
++	MT7981_PIN(21, "SPI0_WP"),
++	MT7981_PIN(22, "SPI1_CLK"),
++	MT7981_PIN(23, "SPI1_MOSI"),
++	MT7981_PIN(24, "SPI1_MISO"),
++	MT7981_PIN(25, "SPI1_CS"),
++	MT7981_PIN(26, "SPI2_CLK"),
++	MT7981_PIN(27, "SPI2_MOSI"),
++	MT7981_PIN(28, "SPI2_MISO"),
++	MT7981_PIN(29, "SPI2_CS"),
++	MT7981_PIN(30, "SPI2_HOLD"),
++	MT7981_PIN(31, "SPI2_WP"),
++	MT7981_PIN(32, "UART0_RXD"),
++	MT7981_PIN(33, "UART0_TXD"),
++	MT7981_PIN(34, "PCIE_CLK_REQ"),
++	MT7981_PIN(35, "PCIE_WAKE_N"),
++	MT7981_PIN(36, "SMI_MDC"),
++	MT7981_PIN(37, "SMI_MDIO"),
++	MT7981_PIN(38, "GBE_INT"),
++	MT7981_PIN(39, "GBE_RESET"),
++	MT7981_PIN(40, "WF_DIG_RESETB"),
++	MT7981_PIN(41, "WF_CBA_RESETB"),
++	MT7981_PIN(42, "WF_XO_REQ"),
++	MT7981_PIN(43, "WF_TOP_CLK"),
++	MT7981_PIN(44, "WF_TOP_DATA"),
++	MT7981_PIN(45, "WF_HB1"),
++	MT7981_PIN(46, "WF_HB2"),
++	MT7981_PIN(47, "WF_HB3"),
++	MT7981_PIN(48, "WF_HB4"),
++	MT7981_PIN(49, "WF_HB0"),
++	MT7981_PIN(50, "WF_HB0_B"),
++	MT7981_PIN(51, "WF_HB5"),
++	MT7981_PIN(52, "WF_HB6"),
++	MT7981_PIN(53, "WF_HB7"),
++	MT7981_PIN(54, "WF_HB8"),
++	MT7981_PIN(55, "WF_HB9"),
++	MT7981_PIN(56, "WF_HB10"),
++};
++
++/* List all groups consisting of these pins dedicated to the enablement of
++ * certain hardware block and the corresponding mode for all of the pins.
++ * The hardware probably has multiple combinations of these pinouts.
++ */
++
++/* WA_AICE */
++static int mt7981_wa_aice1_pins[] = { 0, 1, };
++static int mt7981_wa_aice1_funcs[] = { 2, 2, };
++
++static int mt7981_wa_aice2_pins[] = { 0, 1, };
++static int mt7981_wa_aice2_funcs[] = { 3, 3, };
++
++static int mt7981_wa_aice3_pins[] = { 28, 29, };
++static int mt7981_wa_aice3_funcs[] = { 3, 3, };
++
++static int mt7981_wm_aice1_pins[] = { 9, 10, };
++static int mt7981_wm_aice1_funcs[] = { 2, 2, };
++
++static int mt7981_wm_aice2_pins[] = { 30, 31, };
++static int mt7981_wm_aice2_funcs[] = { 5, 5, };
++
++/* WM_UART */
++static int mt7981_wm_uart_0_pins[] = { 0, 1, };
++static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
++
++static int mt7981_wm_uart_1_pins[] = { 20, 21, };
++static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
++
++static int mt7981_wm_uart_2_pins[] = { 30, 31, };
++static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
++
++/* DFD */
++static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
++static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
++
++/* SYS_WATCHDOG */
++static int mt7981_watchdog_pins[] = { 2, };
++static int mt7981_watchdog_funcs[] = { 1, };
++
++static int mt7981_watchdog1_pins[] = { 13, };
++static int mt7981_watchdog1_funcs[] = { 5, };
++
++/* PCIE_PERESET_N */
++static int mt7981_pcie_pereset_pins[] = { 3, };
++static int mt7981_pcie_pereset_funcs[] = { 1, };
++
++/* JTAG */
++static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
++static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
++
++/* WM_JTAG */
++static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
++static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
++
++static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
++static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
++
++/* WO0_JTAG */
++static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
++static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
++
++static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
++static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
++
++/* UART2 */
++static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
++static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
++
++/* GBE_LED0 */
++static int mt7981_gbe_led0_pins[] = { 8, };
++static int mt7981_gbe_led0_funcs[] = { 3, };
++
++/* PTA_EXT */
++static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
++static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
++
++static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
++static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
++
++/* PWM2 */
++static int mt7981_pwm2_pins[] = { 7, };
++static int mt7981_pwm2_funcs[] = { 4, };
++
++/* NET_WO0_UART_TXD */
++static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
++static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
++
++static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
++static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
++
++static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
++static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
++
++/* SPI1 */
++static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
++static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
++
++/* I2C */
++static int mt7981_i2c0_0_pins[] = { 6, 7, };
++static int mt7981_i2c0_0_funcs[] = { 6, 6, };
++
++static int mt7981_i2c0_1_pins[] = { 30, 31, };
++static int mt7981_i2c0_1_funcs[] = { 4, 4, };
++
++static int mt7981_i2c0_2_pins[] = { 36, 37, };
++static int mt7981_i2c0_2_funcs[] = { 2, 2, };
++
++static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
++static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
++
++static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
++static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
++
++static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
++static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
++
++static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
++static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
++
++/* DFD_NTRST */
++static int mt7981_dfd_ntrst_pins[] = { 8, };
++static int mt7981_dfd_ntrst_funcs[] = { 6, };
++
++/* PWM0 */
++static int mt7981_pwm0_0_pins[] = { 13, };
++static int mt7981_pwm0_0_funcs[] = { 2, };
++
++static int mt7981_pwm0_1_pins[] = { 15, };
++static int mt7981_pwm0_1_funcs[] = { 1, };
++
++/* PWM1 */
++static int mt7981_pwm1_0_pins[] = { 14, };
++static int mt7981_pwm1_0_funcs[] = { 2, };
++
++static int mt7981_pwm1_1_pins[] = { 15, };
++static int mt7981_pwm1_1_funcs[] = { 3, };
++
++/* GBE_LED1 */
++static int mt7981_gbe_led1_pins[] = { 13, };
++static int mt7981_gbe_led1_funcs[] = { 3, };
++
++/* PCM */
++static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
++static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
++
++/* UDI */
++static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
++static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
++
++/* DRV_VBUS */
++static int mt7981_drv_vbus_pins[] = { 14, };
++static int mt7981_drv_vbus_funcs[] = { 1, };
++
++/* EMMC */
++static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
++static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
++
++/* SNFI */
++static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
++static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
++
++/* SPI0 */
++static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
++static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
++
++/* SPI0 */
++static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
++static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
++
++/* SPI1 */
++static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
++static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
++
++/* SPI2 */
++static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
++static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
++
++/* SPI2 */
++static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
++static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
++
++/* UART1 */
++static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
++static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
++
++static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
++static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
++
++/* UART2 */
++static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
++static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
++
++/* UART0 */
++static int mt7981_uart0_pins[] = { 32, 33, };
++static int mt7981_uart0_funcs[] = { 1, 1, };
++
++/* PCIE_CLK_REQ */
++static int mt7981_pcie_clk_pins[] = { 34, };
++static int mt7981_pcie_clk_funcs[] = { 2, };
++
++/* PCIE_WAKE_N */
++static int mt7981_pcie_wake_pins[] = { 35, };
++static int mt7981_pcie_wake_funcs[] = { 2, };
++
++/* MDC_MDIO */
++static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
++static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
++
++static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
++static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
++
++/* WF0_MODE1 */
++static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
++static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
++
++/* WF0_MODE3 */
++static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
++static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
++
++/* WF2G_LED */
++static int mt7981_wf2g_led0_pins[] = { 30, };
++static int mt7981_wf2g_led0_funcs[] = { 2, };
++
++static int mt7981_wf2g_led1_pins[] = { 34, };
++static int mt7981_wf2g_led1_funcs[] = { 1, };
++
++/* WF5G_LED */
++static int mt7981_wf5g_led0_pins[] = { 31, };
++static int mt7981_wf5g_led0_funcs[] = { 2, };
++
++static int mt7981_wf5g_led1_pins[] = { 35, };
++static int mt7981_wf5g_led1_funcs[] = { 1, };
++
++/* MT7531_INT */
++static int mt7981_mt7531_int_pins[] = { 38, };
++static int mt7981_mt7531_int_funcs[] = { 1, };
++
++/* ANT_SEL */
++static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
++static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
++
++static const struct group_desc mt7981_groups[] = {
++	/* @GPIO(0,1): WA_AICE(2) */
++	PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
++	/* @GPIO(0,1): WA_AICE(3) */
++	PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
++	/* @GPIO(0,1): WM_UART(5) */
++	PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
++	/* @GPIO(0,1,4,5): DFD(6) */
++	PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
++	/* @GPIO(2): SYS_WATCHDOG(1) */
++	PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
++	/* @GPIO(3): PCIE_PERESET_N(1) */
++	PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
++	/* @GPIO(4,8) JTAG(1) */
++	PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
++	/* @GPIO(4,8) WM_JTAG(2) */
++	PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
++	/* @GPIO(9,13) WO0_JTAG(1) */
++	PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
++	/* @GPIO(4,7) WM_JTAG(3) */
++	PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
++	/* @GPIO(8) GBE_LED0(3) */
++	PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
++	/* @GPIO(4,6) PTA_EXT(4) */
++	PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
++	/* @GPIO(7) PWM2(4) */
++	PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
++	/* @GPIO(8) NET_WO0_UART_TXD(4) */
++	PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
++	/* @GPIO(4,7) SPI1(5) */
++	PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
++	/* @GPIO(6,7) I2C(5) */
++	PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
++	/* @GPIO(0,1,4,5): DFD_NTRST(6) */
++	PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
++	/* @GPIO(9,10): WM_AICE(2) */
++	PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
++	/* @GPIO(13): PWM0(2) */
++	PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
++	/* @GPIO(15): PWM0(1) */
++	PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
++	/* @GPIO(14): PWM1(2) */
++	PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
++	/* @GPIO(15): PWM1(3) */
++	PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
++	/* @GPIO(14) NET_WO0_UART_TXD(3) */
++	PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
++	/* @GPIO(15) NET_WO0_UART_TXD(4) */
++	PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
++	/* @GPIO(13) GBE_LED0(3) */
++	PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
++	/* @GPIO(9,13) PCM(4) */
++	PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
++	/* @GPIO(13): SYS_WATCHDOG1(5) */
++	PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
++	/* @GPIO(9,13) UDI(4) */
++	PINCTRL_PIN_GROUP("udi", mt7981_udi),
++	/* @GPIO(14) DRV_VBUS(1) */
++	PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
++	/* @GPIO(15,25): EMMC(2) */
++	PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
++	/* @GPIO(16,21): SNFI(3) */
++	PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
++	/* @GPIO(16,19): SPI0(1) */
++	PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
++	/* @GPIO(20,21): SPI0(1) */
++	PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
++	/* @GPIO(22,25) SPI1(1) */
++	PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
++	/* @GPIO(26,29): SPI2(1) */
++	PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
++	/* @GPIO(30,31): SPI0(1) */
++	PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
++	/* @GPIO(16,19): UART1(4) */
++	PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
++	/* @GPIO(26,29): UART1(2) */
++	PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
++	/* @GPIO(22,25): UART1(3) */
++	PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
++	/* @GPIO(22,24) PTA_EXT(4) */
++	PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
++	/* @GPIO(20,21): WM_UART(4) */
++	PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
++	/* @GPIO(30,31): WM_UART(3) */
++	PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
++	/* @GPIO(20,24) WM_JTAG(5) */
++	PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
++	/* @GPIO(25,29) WO0_JTAG(5) */
++	PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
++	/* @GPIO(28,29): WA_AICE(3) */
++	PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
++	/* @GPIO(30,31): WM_AICE(5) */
++	PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
++	/* @GPIO(30,31): I2C(4) */
++	PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
++	/* @GPIO(30,31): I2C(6) */
++	PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
++	/* @GPIO(32,33): I2C(1) */
++	PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
++	/* @GPIO(32,33): I2C(2) */
++	PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
++	/* @GPIO(32,33): I2C(3) */
++	PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
++	/* @GPIO(32,33): I2C(5) */
++	PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
++	/* @GPIO(34): PCIE_CLK_REQ(2) */
++	PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
++	/* @GPIO(35): PCIE_WAKE_N(2) */
++	PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
++	/* @GPIO(36,37): I2C(2) */
++	PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
++	/* @GPIO(36,37): MDC_MDIO(1) */
++	PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
++	/* @GPIO(36,37): MDC_MDIO(3) */
++	PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
++	/* @GPIO(69,85): WF0_MODE1(1) */
++	PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
++	/* @GPIO(74,80): WF0_MODE3(3) */
++	PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
++	/* @GPIO(30): WF2G_LED(2) */
++	PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
++	/* @GPIO(34): WF2G_LED(1) */
++	PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
++	/* @GPIO(31): WF5G_LED(2) */
++	PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
++	/* @GPIO(35): WF5G_LED(1) */
++	PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
++	/* @GPIO(38): MT7531_INT(1) */
++	PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
++	/* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
++	PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
++};
++
++/* Joint those groups owning the same capability in user point of view which
++ * allows that people tend to use through the device tree.
++ */
++static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
++	"wa_aice3", "wm_aice1_2", };
++static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
++	"net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
++	"uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
++static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
++static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
++static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
++static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
++	"wo0_jtag_1", "wm_jtag_1", };
++static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
++	"wf2g_led1", "wf5g_led0", "wf5g_led1", };
++static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
++static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
++	"pwm1_0", "pwm1_1", };
++static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
++	"spi2_wp_hold", };
++static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
++	"sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
++static const char *mt7981_pcm_groups[] = { "pcm", };
++static const char *mt7981_udi_groups[] = { "udi", };
++static const char *mt7981_usb_groups[] = { "drv_vbus", };
++static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
++static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
++	"wf0_mode1", "wf0_mode3", "mt7531_int", };
++static const char *mt7981_ant_groups[] = { "ant_sel", };
++
++static const struct function_desc mt7981_functions[] = {
++	{"wa_aice",	mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
++	{"dfd",	mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
++	{"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
++	{"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
++	{"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
++	{"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
++	{"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
++	{"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
++	{"eth",	mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
++	{"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
++	{"led",	mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
++	{"pwm",	mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
++	{"spi",	mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
++	{"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
++	{"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
++	{"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
++	{"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
++};
++
++static const struct mtk_eint_hw mt7981_eint_hw = {
++	.port_mask = 7,
++	.ports     = 7,
++	.ap_num    = ARRAY_SIZE(mt7981_pins),
++	.db_cnt    = 16,
++};
++
++static const char * const mt7981_pinctrl_register_base_names[] = {
++	"gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
++	"iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
++};
++
++static struct mtk_pin_soc mt7981_data = {
++	.reg_cal = mt7981_reg_cals,
++	.pins = mt7981_pins,
++	.npins = ARRAY_SIZE(mt7981_pins),
++	.grps = mt7981_groups,
++	.ngrps = ARRAY_SIZE(mt7981_groups),
++	.funcs = mt7981_functions,
++	.nfuncs = ARRAY_SIZE(mt7981_functions),
++	.eint_hw = &mt7981_eint_hw,
++	.gpio_m = 0,
++	.ies_present = false,
++	.base_names = mt7981_pinctrl_register_base_names,
++	.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
++	.pull_type = mt7981_pull_type,
++	.bias_set_combo = mtk_pinconf_bias_set_combo,
++	.bias_get_combo = mtk_pinconf_bias_get_combo,
++	.drive_set = mtk_pinconf_drive_set_rev1,
++	.drive_get = mtk_pinconf_drive_get_rev1,
++	.adv_pull_get = mtk_pinconf_adv_pull_get,
++	.adv_pull_set = mtk_pinconf_adv_pull_set,
++};
++
++static const struct of_device_id mt7981_pinctrl_of_match[] = {
++	{ .compatible = "mediatek,mt7981-pinctrl", },
++	{}
++};
++
++static int mt7981_pinctrl_probe(struct platform_device *pdev)
++{
++	return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
++}
++
++static struct platform_driver mt7981_pinctrl_driver = {
++	.driver = {
++		.name = "mt7981-pinctrl",
++		.of_match_table = mt7981_pinctrl_of_match,
++	},
++	.probe = mt7981_pinctrl_probe,
++};
++
++static int __init mt7981_pinctrl_init(void)
++{
++	return platform_driver_register(&mt7981_pinctrl_driver);
++}
++arch_initcall(mt7981_pinctrl_init);

target/linux/mediatek/patches-6.6/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch

@@ -0,0 +1,30 @@
+From c0ad453e94e5c404efbcf668648d07eaa1a71ed7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <[email protected]>
+Date: Sat, 18 Feb 2023 09:51:06 +0300
+Subject: [PATCH] pinctrl: mediatek: add missing options to PINCTRL_MT7981
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are options missing from PINCTRL_MT7981 whilst being on every other
+pin controller. Add them.
+
+Signed-off-by: Arınç ÜNAL <[email protected]>
+Acked-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/mediatek/Kconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/pinctrl/mediatek/Kconfig
++++ b/drivers/pinctrl/mediatek/Kconfig
+@@ -130,6 +130,8 @@ config PINCTRL_MT7622
+ config PINCTRL_MT7981
+ 	bool "Mediatek MT7981 pin control"
+ 	depends on OF
++	depends on ARM64 || COMPILE_TEST
++	default ARM64 && ARCH_MEDIATEK
+ 	select PINCTRL_MTK_MOORE
+ 
+ config PINCTRL_MT7986

target/linux/mediatek/patches-6.6/217-v6.5-pinctrl-mediatek-fix-pull_type-data-for-MT7981.patch

@@ -0,0 +1,76 @@
+From 8f6f16fe1553ce63edfb98a39ef9d4754a0c39bf Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Fri, 18 Aug 2023 04:02:35 +0100
+Subject: [PATCH] pinctrl: mediatek: fix pull_type data for MT7981
+
+MediaTek has released pull_type data for MT7981 in their SDK.
+Use it and set functions to configure pin bias.
+
+Fixes: 6c83b2d94fcc ("pinctrl: add mt7981 pinctrl driver")
+Signed-off-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/7bcc8ead25dbfabc7f5a85d066224a926fbb4941.1692327317.git.daniel@makrotopia.org
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7981.c | 44 +++++++----------------
+ 1 file changed, 13 insertions(+), 31 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+@@ -457,37 +457,15 @@ static const unsigned int mt7981_pull_ty
+ 	MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
+ 	MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
+ 	MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
+-	MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
+-	MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
+-	MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
+-	MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
+-	MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
+-	MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
+-	MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
+-	MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
+-	MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
+-	MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
+-	MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
+-	MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
+-	MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
+-	MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
+-	MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
+-	MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
+-	MTK_PULL_PU_PD_TYPE,/*100*/
++	MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
++	MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
++	MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
++	MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
++	MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
++	MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
++	MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
++	MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
++	MTK_PULL_PU_PD_TYPE,/*56*/
+ };
+ 
+ static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
+@@ -1014,6 +992,10 @@ static struct mtk_pin_soc mt7981_data =
+ 	.ies_present = false,
+ 	.base_names = mt7981_pinctrl_register_base_names,
+ 	.nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
++	.bias_disable_set = mtk_pinconf_bias_disable_set,
++	.bias_disable_get = mtk_pinconf_bias_disable_get,
++	.bias_set = mtk_pinconf_bias_set,
++	.bias_get = mtk_pinconf_bias_get,
+ 	.pull_type = mt7981_pull_type,
+ 	.bias_set_combo = mtk_pinconf_bias_set_combo,
+ 	.bias_get_combo = mtk_pinconf_bias_get_combo,

target/linux/mediatek/patches-6.6/218-pinctrl-mediatek-mt7981-add-additional-uart-groups.patch

@@ -0,0 +1,65 @@
+From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Sat, 26 Aug 2023 21:06:14 +0100
+Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups
+
+Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups.
+
+Signed-off-by: Daniel Golle <[email protected]>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++---
+ 1 file changed, 13 insertions(+), 3 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
+@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = {
+ static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
+ static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
+ 
++static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
++static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
++
+ /* GBE_LED0 */
+ static int mt7981_gbe_led0_pins[] = { 8, };
+ static int mt7981_gbe_led0_funcs[] = { 3, };
+@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4,
+ static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
+ static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
+ 
++static int mt7981_uart1_2_pins[] = { 9, 10, };
++static int mt7981_uart1_2_funcs[] = { 2, 2, };
++
+ /* UART2 */
+ static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
+ static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
+@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr
+ 	PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
+ 	/* @GPIO(4,7) WM_JTAG(3) */
+ 	PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
++	/* @GPIO(4,5) WM_JTAG(4) */
++	PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
+ 	/* @GPIO(8) GBE_LED0(3) */
+ 	PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
+ 	/* @GPIO(4,6) PTA_EXT(4) */
+@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr
+ 	PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
+ 	/* @GPIO(26,29): UART1(2) */
+ 	PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
++	/* @GPIO(9,10): UART1(2) */
++	PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
+ 	/* @GPIO(22,25): UART1(3) */
+ 	PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
+ 	/* @GPIO(22,24) PTA_EXT(4) */
+@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr
+  */
+ static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
+ 	"wa_aice3", "wm_aice1_2", };
+-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
+-	"net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
+-	"uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
++static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
++	"net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
++	"uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
+ static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
+ static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
+ static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };

target/linux/mediatek/patches-6.6/219-v6.6-pinctrl-mediatek-assign-functions-to-configure-pin-b.patch

@@ -0,0 +1,41 @@
+From 0d8387fba9f151220e48dc3dcdc2335539708f13 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Fri, 18 Aug 2023 04:03:26 +0100
+Subject: [PATCH] pinctrl: mediatek: assign functions to configure pin bias on
+ MT7986
+
+Assign bias_disable_get/set and bias_get/set functions to allow
+configuring pin bias on MT7986.
+
+Fixes: 2c58d8dc9cd0 ("pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC")
+Signed-off-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/47f72372354312a839b9337e09476aadcc206e8b.1692327317.git.daniel@makrotopia.org
+Signed-off-by: Linus Walleij <[email protected]>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
+@@ -922,6 +922,10 @@ static struct mtk_pin_soc mt7986a_data =
+ 	.ies_present = false,
+ 	.base_names = mt7986_pinctrl_register_base_names,
+ 	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
++	.bias_disable_set = mtk_pinconf_bias_disable_set,
++	.bias_disable_get = mtk_pinconf_bias_disable_get,
++	.bias_set = mtk_pinconf_bias_set,
++	.bias_get = mtk_pinconf_bias_get,
+ 	.pull_type = mt7986_pull_type,
+ 	.bias_set_combo = mtk_pinconf_bias_set_combo,
+ 	.bias_get_combo = mtk_pinconf_bias_get_combo,
+@@ -944,6 +948,10 @@ static struct mtk_pin_soc mt7986b_data =
+ 	.ies_present = false,
+ 	.base_names = mt7986_pinctrl_register_base_names,
+ 	.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
++	.bias_disable_set = mtk_pinconf_bias_disable_set,
++	.bias_disable_get = mtk_pinconf_bias_disable_get,
++	.bias_set = mtk_pinconf_bias_set,
++	.bias_get = mtk_pinconf_bias_get,
+ 	.pull_type = mt7986_pull_type,
+ 	.bias_set_combo = mtk_pinconf_bias_set_combo,
+ 	.bias_get_combo = mtk_pinconf_bias_get_combo,

target/linux/mediatek/patches-6.6/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch

@@ -0,0 +1,536 @@
+From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:33 +0100
+Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with
+ mtk_clk_register_gates()
+
+Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
+introduces a helper function for the sole purpose of propagating a
+struct device pointer to the clk API when registering the mtk-gate
+clocks to take advantage of Runtime PM when/where needed and where
+a power domain is defined in devicetree.
+
+Function mtk_clk_register_gates() then becomes a wrapper around the
+new mtk_clk_register_gates_with_dev() function that will simply pass
+NULL as struct device: this is essential when registering drivers
+with CLK_OF_DECLARE instead of as a platform device, as there will
+be no struct device to pass... but we can as well simply have only
+one function that always takes such pointer as a param and pass NULL
+when unavoidable.
+
+This commit removes the mtk_clk_register_gates() wrapper and renames
+mtk_clk_register_gates_with_dev() to the former and all of the calls
+to either of the two functions were fixed in all drivers in order to
+reflect this change; also, to improve consistency with other kernel
+functions, the pointer to struct device was moved as the first param.
+
+Since a lot of MediaTek clock drivers are actually registering as a
+platform device, but were still registering the mtk-gate clocks
+without passing any struct device to the clock framework, they've
+been changed to pass a valid one now, as to make all those platforms
+able to use runtime power management where available.
+
+While at it, some much needed indentation changes were also done.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Reviewed-by: Markus Schneider-Pargmann <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+
+[[email protected]: dropped parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-gate.c            | 23 +++++++---------------
+ drivers/clk/mediatek/clk-gate.h            |  7 +------
+ drivers/clk/mediatek/clk-mt2701-aud.c      |  4 ++--
+ drivers/clk/mediatek/clk-mt2701-eth.c      |  4 ++--
+ drivers/clk/mediatek/clk-mt2701-g3d.c      |  2 +-
+ drivers/clk/mediatek/clk-mt2701-hif.c      |  4 ++--
+ drivers/clk/mediatek/clk-mt2701-mm.c       |  4 ++--
+ drivers/clk/mediatek/clk-mt2701.c          | 12 +++++------
+ drivers/clk/mediatek/clk-mt2712-mm.c       |  4 ++--
+ drivers/clk/mediatek/clk-mt2712.c          | 12 +++++------
+ drivers/clk/mediatek/clk-mt7622-aud.c      |  4 ++--
+ drivers/clk/mediatek/clk-mt7622-eth.c      |  8 ++++----
+ drivers/clk/mediatek/clk-mt7622-hif.c      |  8 ++++----
+ drivers/clk/mediatek/clk-mt7622.c          | 14 ++++++-------
+ drivers/clk/mediatek/clk-mt7629-eth.c      |  7 ++++---
+ drivers/clk/mediatek/clk-mt7629-hif.c      |  8 ++++----
+ drivers/clk/mediatek/clk-mt7629.c          | 10 +++++-----
+ drivers/clk/mediatek/clk-mt7986-eth.c      | 10 +++++-----
+ drivers/clk/mediatek/clk-mt7986-infracfg.c |  4 ++--
+ 19 files changed, 68 insertions(+), 81 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-gate.c
++++ b/drivers/clk/mediatek/clk-gate.c
+@@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no
+ };
+ EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
+ 
+-static struct clk_hw *mtk_clk_register_gate(const char *name,
++static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
+ 					 const char *parent_name,
+ 					 struct regmap *regmap, int set_ofs,
+ 					 int clr_ofs, int sta_ofs, u8 bit,
+ 					 const struct clk_ops *ops,
+-					 unsigned long flags, struct device *dev)
++					 unsigned long flags)
+ {
+ 	struct mtk_clk_gate *cg;
+ 	int ret;
+@@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru
+ 	kfree(cg);
+ }
+ 
+-int mtk_clk_register_gates_with_dev(struct device_node *node,
+-				    const struct mtk_gate *clks, int num,
+-				    struct clk_hw_onecell_data *clk_data,
+-				    struct device *dev)
++int mtk_clk_register_gates(struct device *dev, struct device_node *node,
++			   const struct mtk_gate *clks, int num,
++			   struct clk_hw_onecell_data *clk_data)
+ {
+ 	int i;
+ 	struct clk_hw *hw;
+@@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru
+ 			continue;
+ 		}
+ 
+-		hw = mtk_clk_register_gate(gate->name, gate->parent_name,
++		hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
+ 					    regmap,
+ 					    gate->regs->set_ofs,
+ 					    gate->regs->clr_ofs,
+ 					    gate->regs->sta_ofs,
+ 					    gate->shift, gate->ops,
+-					    gate->flags, dev);
++					    gate->flags);
+ 
+ 		if (IS_ERR(hw)) {
+ 			pr_err("Failed to register clk %s: %pe\n", gate->name,
+@@ -261,14 +260,6 @@ err:
+ 
+ 	return PTR_ERR(hw);
+ }
+-EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev);
+-
+-int mtk_clk_register_gates(struct device_node *node,
+-			   const struct mtk_gate *clks, int num,
+-			   struct clk_hw_onecell_data *clk_data)
+-{
+-	return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
+-}
+ EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
+ 
+ void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
+--- a/drivers/clk/mediatek/clk-gate.h
++++ b/drivers/clk/mediatek/clk-gate.h
+@@ -50,15 +50,10 @@ struct mtk_gate {
+ #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops)		\
+ 	GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
+ 
+-int mtk_clk_register_gates(struct device_node *node,
++int mtk_clk_register_gates(struct device *dev, struct device_node *node,
+ 			   const struct mtk_gate *clks, int num,
+ 			   struct clk_hw_onecell_data *clk_data);
+ 
+-int mtk_clk_register_gates_with_dev(struct device_node *node,
+-				    const struct mtk_gate *clks, int num,
+-				    struct clk_hw_onecell_data *clk_data,
+-				    struct device *dev);
+-
+ void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
+ 			      struct clk_hw_onecell_data *clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt2701-aud.c
++++ b/drivers/clk/mediatek/clk-mt2701-aud.c
+@@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
+ 
+-	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
++			       ARRAY_SIZE(audio_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r) {
+--- a/drivers/clk/mediatek/clk-mt2701-eth.c
++++ b/drivers/clk/mediatek/clk-mt2701-eth.c
+@@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
+ 
+-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
+-						clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
++			       ARRAY_SIZE(eth_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
++++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
+@@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
+ 
+-	mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
++	mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
+ 			       clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+--- a/drivers/clk/mediatek/clk-mt2701-hif.c
++++ b/drivers/clk/mediatek/clk-mt2701-hif.c
+@@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
+ 
+-	mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
+-						clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, hif_clks,
++			       ARRAY_SIZE(hif_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r) {
+--- a/drivers/clk/mediatek/clk-mt2701-mm.c
++++ b/drivers/clk/mediatek/clk-mt2701-mm.c
+@@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_MM_NR);
+ 
+-	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+-						clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, mm_clks,
++			       ARRAY_SIZE(mm_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -685,8 +685,8 @@ static int mtk_topckgen_init(struct plat
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ 				base, &mt2701_clk_lock, clk_data);
+ 
+-	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+-						clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, top_clks,
++			       ARRAY_SIZE(top_clks), clk_data);
+ 
+ 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ }
+@@ -789,8 +789,8 @@ static int mtk_infrasys_init(struct plat
+ 		}
+ 	}
+ 
+-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+-						infra_clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++			       ARRAY_SIZE(infra_clks), infra_clk_data);
+ 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ 						infra_clk_data);
+ 
+@@ -902,8 +902,8 @@ static int mtk_pericfg_init(struct platf
+ 	if (!clk_data)
+ 		return -ENOMEM;
+ 
+-	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+-						clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+ 	mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
+ 			&mt2701_clk_lock, clk_data);
+--- a/drivers/clk/mediatek/clk-mt2712-mm.c
++++ b/drivers/clk/mediatek/clk-mt2712-mm.c
+@@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
+-			clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, mm_clks,
++			       ARRAY_SIZE(mm_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt2712.c
++++ b/drivers/clk/mediatek/clk-mt2712.c
+@@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p
+ 			&mt2712_clk_lock, top_clk_data);
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+ 			&mt2712_clk_lock, top_clk_data);
+-	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+-			top_clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, top_clks,
++			       ARRAY_SIZE(top_clks), top_clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
+ 
+@@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+-			clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+@@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+-			clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt7622-aud.c
++++ b/drivers/clk/mediatek/clk-mt7622-aud.c
+@@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
++			       ARRAY_SIZE(audio_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r) {
+--- a/drivers/clk/mediatek/clk-mt7622-eth.c
++++ b/drivers/clk/mediatek/clk-mt7622-eth.c
+@@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
++			       ARRAY_SIZE(eth_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
++			       ARRAY_SIZE(sgmii_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt7622-hif.c
++++ b/drivers/clk/mediatek/clk-mt7622-hif.c
+@@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
++			       ARRAY_SIZE(ssusb_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
++			       ARRAY_SIZE(pcie_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt7622.c
++++ b/drivers/clk/mediatek/clk-mt7622.c
+@@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ 				  base, &mt7622_clk_lock, clk_data);
+ 
+-	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, top_clks,
++			       ARRAY_SIZE(top_clks), clk_data);
+ 
+ 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ }
+@@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+ 	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+ 				  clk_data);
+@@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl
+ 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ 			      clk_data);
+ 
+-	mtk_clk_register_gates(node, apmixed_clks,
++	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
+ 			       ARRAY_SIZE(apmixed_clks), clk_data);
+ 
+ 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+@@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+ 	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
+ 				    &mt7622_clk_lock, clk_data);
+--- a/drivers/clk/mediatek/clk-mt7629-eth.c
++++ b/drivers/clk/mediatek/clk-mt7629-eth.c
+@@ -82,7 +82,8 @@ static int clk_mt7629_ethsys_init(struct
+ 	if (!clk_data)
+ 		return -ENOMEM;
+ 
+-	mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
++			       CLK_ETH_NR_CLK, clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -106,8 +107,8 @@ static int clk_mt7629_sgmiisys_init(stru
+ 	if (!clk_data)
+ 		return -ENOMEM;
+ 
+-	mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
++			       CLK_SGMII_NR_CLK, clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt7629-hif.c
++++ b/drivers/clk/mediatek/clk-mt7629-hif.c
+@@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
++			       ARRAY_SIZE(ssusb_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+ 
+-	mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
++			       ARRAY_SIZE(pcie_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt7629.c
++++ b/drivers/clk/mediatek/clk-mt7629.c
+@@ -585,8 +585,8 @@ static int mtk_infrasys_init(struct plat
+ 	if (!clk_data)
+ 		return -ENOMEM;
+ 
+-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+ 	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+ 				  clk_data);
+@@ -610,8 +610,8 @@ static int mtk_pericfg_init(struct platf
+ 	if (!clk_data)
+ 		return -ENOMEM;
+ 
+-	mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
++			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+ 	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
+ 				    &mt7629_clk_lock, clk_data);
+@@ -637,7 +637,7 @@ static int mtk_apmixedsys_init(struct pl
+ 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+ 			      clk_data);
+ 
+-	mtk_clk_register_gates(node, apmixed_clks,
++	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
+ 			       ARRAY_SIZE(apmixed_clks), clk_data);
+ 
+ 	clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
+--- a/drivers/clk/mediatek/clk-mt7986-eth.c
++++ b/drivers/clk/mediatek/clk-mt7986-eth.c
+@@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s
+ 
+ 	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
+ 
+-	mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
+-			       clk_data);
++	mtk_clk_register_gates(NULL, node, sgmii0_clks,
++			       ARRAY_SIZE(sgmii0_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s
+ 
+ 	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
+ 
+-	mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
+-			       clk_data);
++	mtk_clk_register_gates(NULL, node, sgmii1_clks,
++			       ARRAY_SIZE(sgmii1_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+@@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc
+ 
+ 	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
+ 
+-	mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
++	mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
+@@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str
+ 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+ 	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
+ 			       &mt7986_clk_lock, clk_data);
+-	mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+-			       clk_data);
++	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
++			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r) {
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform
+ 	if (!clk_data)
+ 		return -ENOMEM;
+ 
+-	r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks,
+-					    clk_data, &pdev->dev);
++	r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
++				   clk_data);
+ 	if (r)
+ 		goto free_data;
+ 

target/linux/mediatek/patches-6.6/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch

@@ -0,0 +1,140 @@
+From b888303c7d23d7bd0c8667cfc657669e5d153fea Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:34 +0100
+Subject: [PATCH 02/15] clk: mediatek: cpumux: Propagate struct device where
+ possible
+
+Take a pointer to a struct device in mtk_clk_register_cpumuxes() and
+propagate the same to mtk_clk_register_cpumux() => clk_hw_register().
+Even though runtime pm is unlikely to be used with CPU muxes, this
+helps with code consistency and possibly opens to commonization of
+some mtk_clk_register_(x) functions.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Reviewed-by: Markus Schneider-Pargmann <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-cpumux.c          | 8 ++++----
+ drivers/clk/mediatek/clk-cpumux.h          | 2 +-
+ drivers/clk/mediatek/clk-mt2701.c          | 2 +-
+ drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++-
+ drivers/clk/mediatek/clk-mt7622.c          | 4 ++--
+ drivers/clk/mediatek/clk-mt7629.c          | 4 ++--
+ drivers/clk/mediatek/clk-mt8173.c          | 4 ++--
+ 7 files changed, 14 insertions(+), 13 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-cpumux.c
++++ b/drivers/clk/mediatek/clk-cpumux.c
+@@ -58,7 +58,7 @@ static const struct clk_ops clk_cpumux_o
+ };
+ 
+ static struct clk_hw *
+-mtk_clk_register_cpumux(const struct mtk_composite *mux,
++mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux,
+ 			struct regmap *regmap)
+ {
+ 	struct mtk_clk_cpumux *cpumux;
+@@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk
+ 	cpumux->regmap = regmap;
+ 	cpumux->hw.init = &init;
+ 
+-	ret = clk_hw_register(NULL, &cpumux->hw);
++	ret = clk_hw_register(dev, &cpumux->hw);
+ 	if (ret) {
+ 		kfree(cpumux);
+ 		return ERR_PTR(ret);
+@@ -102,7 +102,7 @@ static void mtk_clk_unregister_cpumux(st
+ 	kfree(cpumux);
+ }
+ 
+-int mtk_clk_register_cpumuxes(struct device_node *node,
++int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
+ 			      const struct mtk_composite *clks, int num,
+ 			      struct clk_hw_onecell_data *clk_data)
+ {
+@@ -125,7 +125,7 @@ int mtk_clk_register_cpumuxes(struct dev
+ 			continue;
+ 		}
+ 
+-		hw = mtk_clk_register_cpumux(mux, regmap);
++		hw = mtk_clk_register_cpumux(dev, mux, regmap);
+ 		if (IS_ERR(hw)) {
+ 			pr_err("Failed to register clk %s: %pe\n", mux->name,
+ 			       hw);
+--- a/drivers/clk/mediatek/clk-cpumux.h
++++ b/drivers/clk/mediatek/clk-cpumux.h
+@@ -11,7 +11,7 @@ struct clk_hw_onecell_data;
+ struct device_node;
+ struct mtk_composite;
+ 
+-int mtk_clk_register_cpumuxes(struct device_node *node,
++int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
+ 			      const struct mtk_composite *clks, int num,
+ 			      struct clk_hw_onecell_data *clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -761,7 +761,7 @@ static void __init mtk_infrasys_init_ear
+ 	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
+ 						infra_clk_data);
+ 
+-	mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
++	mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+ 				  infra_clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
+--- a/drivers/clk/mediatek/clk-mt6795-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c
+@@ -105,7 +105,8 @@ static int clk_mt6795_infracfg_probe(str
+ 	if (ret)
+ 		goto free_clk_data;
+ 
+-	ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
++	ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
++					ARRAY_SIZE(cpu_muxes), clk_data);
+ 	if (ret)
+ 		goto unregister_gates;
+ 
+--- a/drivers/clk/mediatek/clk-mt7622.c
++++ b/drivers/clk/mediatek/clk-mt7622.c
+@@ -638,8 +638,8 @@ static int mtk_infrasys_init(struct plat
+ 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ 			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+-	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+-				  clk_data);
++	mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
++				  ARRAY_SIZE(infra_muxes), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
+ 				   clk_data);
+--- a/drivers/clk/mediatek/clk-mt7629.c
++++ b/drivers/clk/mediatek/clk-mt7629.c
+@@ -588,8 +588,8 @@ static int mtk_infrasys_init(struct plat
+ 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ 			       ARRAY_SIZE(infra_clks), clk_data);
+ 
+-	mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
+-				  clk_data);
++	mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
++				  ARRAY_SIZE(infra_muxes), clk_data);
+ 
+ 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
+ 				      clk_data);
+--- a/drivers/clk/mediatek/clk-mt8173.c
++++ b/drivers/clk/mediatek/clk-mt8173.c
+@@ -892,8 +892,8 @@ static void __init mtk_infrasys_init(str
+ 						clk_data);
+ 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+ 
+-	mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
+-				  clk_data);
++	mtk_clk_register_cpumuxes(NULL, node, cpu_muxes,
++				  ARRAY_SIZE(cpu_muxes), clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)

target/linux/mediatek/patches-6.6/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch

@@ -0,0 +1,181 @@
+From f23375db001ec0fe9f565be75eff43adde15407e Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:35 +0100
+Subject: [PATCH 03/15] clk: mediatek: clk-mtk: Propagate struct device for
+ composites
+
+Like done for cpumux clocks, propagate struct device for composite
+clocks registered through clk-mtk helpers to be able to get runtime
+pm support for MTK clocks.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+
+[[email protected]: remove parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-mt2701.c | 10 ++++++----
+ drivers/clk/mediatek/clk-mt2712.c | 12 ++++++++----
+ drivers/clk/mediatek/clk-mt7622.c |  8 +++++---
+ drivers/clk/mediatek/clk-mt7629.c |  8 +++++---
+ drivers/clk/mediatek/clk-mtk.c    | 11 ++++++-----
+ drivers/clk/mediatek/clk-mtk.h    |  3 ++-
+ 6 files changed, 32 insertions(+), 20 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -679,8 +679,9 @@ static int mtk_topckgen_init(struct plat
+ 	mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
+ 								clk_data);
+ 
+-	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+-				base, &mt2701_clk_lock, clk_data);
++	mtk_clk_register_composites(&pdev->dev, top_muxes,
++				    ARRAY_SIZE(top_muxes), base,
++				    &mt2701_clk_lock, clk_data);
+ 
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ 				base, &mt2701_clk_lock, clk_data);
+@@ -905,8 +906,9 @@ static int mtk_pericfg_init(struct platf
+ 	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ 			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+-	mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
+-			&mt2701_clk_lock, clk_data);
++	mtk_clk_register_composites(&pdev->dev, peri_muxs,
++				    ARRAY_SIZE(peri_muxs), base,
++				    &mt2701_clk_lock, clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+--- a/drivers/clk/mediatek/clk-mt2712.c
++++ b/drivers/clk/mediatek/clk-mt2712.c
+@@ -1320,8 +1320,9 @@ static int clk_mt2712_top_probe(struct p
+ 	mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
+ 			top_clk_data);
+ 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
+-	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
+-			&mt2712_clk_lock, top_clk_data);
++	mtk_clk_register_composites(&pdev->dev, top_muxes,
++				    ARRAY_SIZE(top_muxes), base,
++				    &mt2712_clk_lock, top_clk_data);
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
+ 			&mt2712_clk_lock, top_clk_data);
+ 	mtk_clk_register_gates(&pdev->dev, node, top_clks,
+@@ -1395,8 +1396,11 @@ static int clk_mt2712_mcu_probe(struct p
+ 
+ 	clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
+ 
+-	mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
+-			&mt2712_clk_lock, clk_data);
++	r = mtk_clk_register_composites(&pdev->dev, mcu_muxes,
++					ARRAY_SIZE(mcu_muxes), base,
++					&mt2712_clk_lock, clk_data);
++	if (r)
++		dev_err(&pdev->dev, "Could not register composites: %d\n", r);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+--- a/drivers/clk/mediatek/clk-mt7622.c
++++ b/drivers/clk/mediatek/clk-mt7622.c
+@@ -615,8 +615,9 @@ static int mtk_topckgen_init(struct plat
+ 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+ 				 clk_data);
+ 
+-	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+-				    base, &mt7622_clk_lock, clk_data);
++	mtk_clk_register_composites(&pdev->dev, top_muxes,
++				    ARRAY_SIZE(top_muxes), base,
++				    &mt7622_clk_lock, clk_data);
+ 
+ 	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+ 				  base, &mt7622_clk_lock, clk_data);
+@@ -685,7 +686,8 @@ static int mtk_pericfg_init(struct platf
+ 	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ 			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+-	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
++	mtk_clk_register_composites(&pdev->dev, peri_muxes,
++				    ARRAY_SIZE(peri_muxes), base,
+ 				    &mt7622_clk_lock, clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+--- a/drivers/clk/mediatek/clk-mt7629.c
++++ b/drivers/clk/mediatek/clk-mt7629.c
+@@ -566,8 +566,9 @@ static int mtk_topckgen_init(struct plat
+ 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
+ 				 clk_data);
+ 
+-	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
+-				    base, &mt7629_clk_lock, clk_data);
++	mtk_clk_register_composites(&pdev->dev, top_muxes,
++				    ARRAY_SIZE(top_muxes), base,
++				    &mt7629_clk_lock, clk_data);
+ 
+ 	clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
+ 	clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
+@@ -613,7 +614,8 @@ static int mtk_pericfg_init(struct platf
+ 	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+ 			       ARRAY_SIZE(peri_clks), clk_data);
+ 
+-	mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
++	mtk_clk_register_composites(&pdev->dev, peri_muxes,
++				    ARRAY_SIZE(peri_muxes), base,
+ 				    &mt7629_clk_lock, clk_data);
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -197,8 +197,8 @@ void mtk_clk_unregister_factors(const st
+ }
+ EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors);
+ 
+-static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc,
+-		void __iomem *base, spinlock_t *lock)
++static struct clk_hw *mtk_clk_register_composite(struct device *dev,
++		const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock)
+ {
+ 	struct clk_hw *hw;
+ 	struct clk_mux *mux = NULL;
+@@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_c
+ 		div_ops = &clk_divider_ops;
+ 	}
+ 
+-	hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents,
++	hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents,
+ 		mux_hw, mux_ops,
+ 		div_hw, div_ops,
+ 		gate_hw, gate_ops,
+@@ -308,7 +308,8 @@ static void mtk_clk_unregister_composite
+ 	kfree(mux);
+ }
+ 
+-int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
++int mtk_clk_register_composites(struct device *dev,
++				const struct mtk_composite *mcs, int num,
+ 				void __iomem *base, spinlock_t *lock,
+ 				struct clk_hw_onecell_data *clk_data)
+ {
+@@ -327,7 +328,7 @@ int mtk_clk_register_composites(const st
+ 			continue;
+ 		}
+ 
+-		hw = mtk_clk_register_composite(mc, base, lock);
++		hw = mtk_clk_register_composite(dev, mc, base, lock);
+ 
+ 		if (IS_ERR(hw)) {
+ 			pr_err("Failed to register clk %s: %pe\n", mc->name,
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -149,7 +149,8 @@ struct mtk_composite {
+ 		.flags = 0,						\
+ 	}
+ 
+-int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
++int mtk_clk_register_composites(struct device *dev,
++				const struct mtk_composite *mcs, int num,
+ 				void __iomem *base, spinlock_t *lock,
+ 				struct clk_hw_onecell_data *clk_data);
+ void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,

target/linux/mediatek/patches-6.6/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch

@@ -0,0 +1,103 @@
+From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:36 +0100
+Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for
+ mtk-mux
+
+Like done for other clocks, propagate struct device for mtk mux clocks
+registered through clk-mux helpers to enable runtime pm support.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+
+[[email protected]: removed parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-mt7986-infracfg.c |  3 ++-
+ drivers/clk/mediatek/clk-mt7986-topckgen.c |  3 ++-
+ drivers/clk/mediatek/clk-mux.c             | 14 ++++++++------
+ drivers/clk/mediatek/clk-mux.h             |  3 ++-
+ 4 files changed, 14 insertions(+), 9 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
+@@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str
+ 		return -ENOMEM;
+ 
+ 	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+-	mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
++	mtk_clk_register_muxes(&pdev->dev, infra_muxes,
++			       ARRAY_SIZE(infra_muxes), node,
+ 			       &mt7986_clk_lock, clk_data);
+ 	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+ 			       ARRAY_SIZE(infra_clks), clk_data);
+--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
+@@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str
+ 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+ 				    clk_data);
+ 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+-	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
++	mtk_clk_register_muxes(&pdev->dev, top_muxes,
++			       ARRAY_SIZE(top_muxes), node,
+ 			       &mt7986_clk_lock, clk_data);
+ 
+ 	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
+--- a/drivers/clk/mediatek/clk-mux.c
++++ b/drivers/clk/mediatek/clk-mux.c
+@@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se
+ };
+ EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
+ 
+-static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux,
+-				 struct regmap *regmap,
+-				 spinlock_t *lock)
++static struct clk_hw *mtk_clk_register_mux(struct device *dev,
++					   const struct mtk_mux *mux,
++					   struct regmap *regmap,
++					   spinlock_t *lock)
+ {
+ 	struct mtk_clk_mux *clk_mux;
+ 	struct clk_init_data init = {};
+@@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m
+ 	clk_mux->lock = lock;
+ 	clk_mux->hw.init = &init;
+ 
+-	ret = clk_hw_register(NULL, &clk_mux->hw);
++	ret = clk_hw_register(dev, &clk_mux->hw);
+ 	if (ret) {
+ 		kfree(clk_mux);
+ 		return ERR_PTR(ret);
+@@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc
+ 	kfree(mux);
+ }
+ 
+-int mtk_clk_register_muxes(const struct mtk_mux *muxes,
++int mtk_clk_register_muxes(struct device *dev,
++			   const struct mtk_mux *muxes,
+ 			   int num, struct device_node *node,
+ 			   spinlock_t *lock,
+ 			   struct clk_hw_onecell_data *clk_data)
+@@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct
+ 			continue;
+ 		}
+ 
+-		hw = mtk_clk_register_mux(mux, regmap, lock);
++		hw = mtk_clk_register_mux(dev, mux, regmap, lock);
+ 
+ 		if (IS_ERR(hw)) {
+ 			pr_err("Failed to register clk %s: %pe\n", mux->name,
+--- a/drivers/clk/mediatek/clk-mux.h
++++ b/drivers/clk/mediatek/clk-mux.h
+@@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate
+ 			0, _upd_ofs, _upd, CLK_SET_RATE_PARENT,		\
+ 			mtk_mux_clr_set_upd_ops)
+ 
+-int mtk_clk_register_muxes(const struct mtk_mux *muxes,
++int mtk_clk_register_muxes(struct device *dev,
++			   const struct mtk_mux *muxes,
+ 			   int num, struct device_node *node,
+ 			   spinlock_t *lock,
+ 			   struct clk_hw_onecell_data *clk_data);

target/linux/mediatek/patches-6.6/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch

@@ -0,0 +1,74 @@
+From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:37 +0100
+Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops
+
+In order to migrate some (few) old clock drivers to the common
+mtk_clk_simple_probe() function, add dummy clock ops to be able
+to insert a dummy clock with ID 0 at the beginning of the list.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Miles Chen <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++
+ drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++
+ 2 files changed, 35 insertions(+)
+
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -18,6 +18,22 @@
+ #include "clk-mtk.h"
+ #include "clk-gate.h"
+ 
++const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
++EXPORT_SYMBOL_GPL(cg_regs_dummy);
++
++static int mtk_clk_dummy_enable(struct clk_hw *hw)
++{
++	return 0;
++}
++
++static void mtk_clk_dummy_disable(struct clk_hw *hw) { }
++
++const struct clk_ops mtk_clk_dummy_ops = {
++	.enable		= mtk_clk_dummy_enable,
++	.disable	= mtk_clk_dummy_disable,
++};
++EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops);
++
+ static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data,
+ 			      unsigned int clk_num)
+ {
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -22,6 +22,25 @@
+ 
+ struct platform_device;
+ 
++/*
++ * We need the clock IDs to start from zero but to maintain devicetree
++ * backwards compatibility we can't change bindings to start from zero.
++ * Only a few platforms are affected, so we solve issues given by the
++ * commonized MTK clocks probe function(s) by adding a dummy clock at
++ * the beginning where needed.
++ */
++#define CLK_DUMMY		0
++
++extern const struct clk_ops mtk_clk_dummy_ops;
++extern const struct mtk_gate_regs cg_regs_dummy;
++
++#define GATE_DUMMY(_id, _name) {				\
++		.id = _id,					\
++		.name = _name,					\
++		.regs = &cg_regs_dummy,				\
++		.ops = &mtk_clk_dummy_ops,			\
++	}
++
+ struct mtk_fixed_clk {
+ 	int id;
+ 	const char *name;

target/linux/mediatek/patches-6.6/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch

@@ -0,0 +1,790 @@
+From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:41 +0100
+Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where
+ possible
+
+mtk_clk_simple_probe() is a function that registers mtk gate clocks
+and, if reset data is present, a reset controller and across all of
+the MTK clock drivers, such a function is duplicated many times:
+switch to the common mtk_clk_simple_probe() function for all of the
+clock drivers that are registering as platform drivers.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Miles Chen <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+
+[[email protected]: removed parts not relevant for OpenWrt]
+---
+ drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++----
+ drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++--------
+ drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++--------------
+ drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++--------
+ drivers/clk/mediatek/clk-mt2712.c     | 83 ++++++++++----------------
+ drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++-----------
+ drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++---------------------
+ drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++----------------------
+ drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++----------------------
+ 9 files changed, 144 insertions(+), 406 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt2701-aud.c
++++ b/drivers/clk/mediatek/clk-mt2701-aud.c
+@@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3
+ };
+ 
+ static const struct mtk_gate audio_clks[] = {
++	GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
+ 	/* AUDIO0 */
+ 	GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
+ 	GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
+@@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[
+ 	GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
+ };
+ 
++static const struct mtk_clk_desc audio_desc = {
++	.clks = audio_clks,
++	.num_clks = ARRAY_SIZE(audio_clks),
++};
++
+ static const struct of_device_id of_match_clk_mt2701_aud[] = {
+-	{ .compatible = "mediatek,mt2701-audsys", },
+-	{}
++	{ .compatible = "mediatek,mt2701-audsys", .data = &audio_desc },
++	{ /* sentinel */ }
+ };
+ 
+ static int clk_mt2701_aud_probe(struct platform_device *pdev)
+ {
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+ 	int r;
+ 
+-	clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
+-			       ARRAY_SIZE(audio_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++	r = mtk_clk_simple_probe(pdev);
+ 	if (r) {
+ 		dev_err(&pdev->dev,
+ 			"could not register clock provider: %s: %d\n",
+ 			pdev->name, r);
+ 
+-		goto err_clk_provider;
++		return r;
+ 	}
+ 
+ 	r = devm_of_platform_populate(&pdev->dev);
+@@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p
+ 	return 0;
+ 
+ err_plat_populate:
+-	of_clk_del_provider(node);
+-err_clk_provider:
++	mtk_clk_simple_remove(pdev);
+ 	return r;
+ }
+ 
++static int clk_mt2701_aud_remove(struct platform_device *pdev)
++{
++	of_platform_depopulate(&pdev->dev);
++	return mtk_clk_simple_remove(pdev);
++}
++
+ static struct platform_driver clk_mt2701_aud_drv = {
+ 	.probe = clk_mt2701_aud_probe,
++	.remove = clk_mt2701_aud_remove,
+ 	.driver = {
+ 		.name = "clk-mt2701-aud",
+ 		.of_match_table = of_match_clk_mt2701_aud,
+--- a/drivers/clk/mediatek/clk-mt2701-eth.c
++++ b/drivers/clk/mediatek/clk-mt2701-eth.c
+@@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg
+ 	GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+ 
+ static const struct mtk_gate eth_clks[] = {
++	GATE_DUMMY(CLK_DUMMY, "eth_dummy"),
+ 	GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
+ 	GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
+ 	GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
+@@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static const struct of_device_id of_match_clk_mt2701_eth[] = {
+-	{ .compatible = "mediatek,mt2701-ethsys", },
+-	{}
++static const struct mtk_clk_desc eth_desc = {
++	.clks = eth_clks,
++	.num_clks = ARRAY_SIZE(eth_clks),
++	.rst_desc = &clk_rst_desc,
+ };
+ 
+-static int clk_mt2701_eth_probe(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	int r;
+-	struct device_node *node = pdev->dev.of_node;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
+-			       ARRAY_SIZE(eth_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return r;
+-}
++static const struct of_device_id of_match_clk_mt2701_eth[] = {
++	{ .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
++	{ /* sentinel */ }
++};
+ 
+ static struct platform_driver clk_mt2701_eth_drv = {
+-	.probe = clk_mt2701_eth_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt2701-eth",
+ 		.of_match_table = of_match_clk_mt2701_eth,
+--- a/drivers/clk/mediatek/clk-mt2701-g3d.c
++++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
+@@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg
+ };
+ 
+ static const struct mtk_gate g3d_clks[] = {
++	GATE_DUMMY(CLK_DUMMY, "g3d_dummy"),
+ 	GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
+ };
+ 
+@@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
+-			       clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return r;
+-}
++static const struct mtk_clk_desc g3d_desc = {
++	.clks = g3d_clks,
++	.num_clks = ARRAY_SIZE(g3d_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+ static const struct of_device_id of_match_clk_mt2701_g3d[] = {
+-	{
+-		.compatible = "mediatek,mt2701-g3dsys",
+-		.data = clk_mt2701_g3dsys_init,
+-	}, {
+-		/* sentinel */
+-	}
++	{ .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc },
++	{ /* sentinel */ }
+ };
+ 
+-static int clk_mt2701_g3d_probe(struct platform_device *pdev)
+-{
+-	int (*clk_init)(struct platform_device *);
+-	int r;
+-
+-	clk_init = of_device_get_match_data(&pdev->dev);
+-	if (!clk_init)
+-		return -EINVAL;
+-
+-	r = clk_init(pdev);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	return r;
+-}
+-
+ static struct platform_driver clk_mt2701_g3d_drv = {
+-	.probe = clk_mt2701_g3d_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt2701-g3d",
+ 		.of_match_table = of_match_clk_mt2701_g3d,
+--- a/drivers/clk/mediatek/clk-mt2701-hif.c
++++ b/drivers/clk/mediatek/clk-mt2701-hif.c
+@@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg
+ 	GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+ 
+ static const struct mtk_gate hif_clks[] = {
++	GATE_DUMMY(CLK_DUMMY, "hif_dummy"),
+ 	GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
+ 	GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
+ 	GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
+@@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static const struct of_device_id of_match_clk_mt2701_hif[] = {
+-	{ .compatible = "mediatek,mt2701-hifsys", },
+-	{}
++static const struct mtk_clk_desc hif_desc = {
++	.clks = hif_clks,
++	.num_clks = ARRAY_SIZE(hif_clks),
++	.rst_desc = &clk_rst_desc,
+ };
+ 
+-static int clk_mt2701_hif_probe(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	int r;
+-	struct device_node *node = pdev->dev.of_node;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, hif_clks,
+-			       ARRAY_SIZE(hif_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r) {
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-		return r;
+-	}
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return 0;
+-}
++static const struct of_device_id of_match_clk_mt2701_hif[] = {
++	{ .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },
++	{ /* sentinel */ }
++};
+ 
+ static struct platform_driver clk_mt2701_hif_drv = {
+-	.probe = clk_mt2701_hif_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt2701-hif",
+ 		.of_match_table = of_match_clk_mt2701_hif,
+--- a/drivers/clk/mediatek/clk-mt2712.c
++++ b/drivers/clk/mediatek/clk-mt2712.c
+@@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p
+ 	return r;
+ }
+ 
+-static int clk_mt2712_infra_probe(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	int r;
+-	struct device_node *node = pdev->dev.of_node;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, infra_clks,
+-			       ARRAY_SIZE(infra_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-
+-	if (r != 0)
+-		pr_err("%s(): could not register clock provider: %d\n",
+-			__func__, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
+-
+-	return r;
+-}
+-
+-static int clk_mt2712_peri_probe(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	int r;
+-	struct device_node *node = pdev->dev.of_node;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, peri_clks,
+-			       ARRAY_SIZE(peri_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-
+-	if (r != 0)
+-		pr_err("%s(): could not register clock provider: %d\n",
+-			__func__, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
+-
+-	return r;
+-}
+-
+ static int clk_mt2712_mcu_probe(struct platform_device *pdev)
+ {
+ 	struct clk_hw_onecell_data *clk_data;
+@@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc
+ 		.compatible = "mediatek,mt2712-topckgen",
+ 		.data = clk_mt2712_top_probe,
+ 	}, {
+-		.compatible = "mediatek,mt2712-infracfg",
+-		.data = clk_mt2712_infra_probe,
+-	}, {
+-		.compatible = "mediatek,mt2712-pericfg",
+-		.data = clk_mt2712_peri_probe,
+-	}, {
+ 		.compatible = "mediatek,mt2712-mcucfg",
+ 		.data = clk_mt2712_mcu_probe,
+ 	}, {
+@@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf
+ 	return r;
+ }
+ 
++static const struct mtk_clk_desc infra_desc = {
++	.clks = infra_clks,
++	.num_clks = ARRAY_SIZE(infra_clks),
++	.rst_desc = &clk_rst_desc[0],
++};
++
++static const struct mtk_clk_desc peri_desc = {
++	.clks = peri_clks,
++	.num_clks = ARRAY_SIZE(peri_clks),
++	.rst_desc = &clk_rst_desc[1],
++};
++
++static const struct of_device_id of_match_clk_mt2712_simple[] = {
++	{ .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc },
++	{ .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, },
++	{ /* sentinel */ }
++};
++
++static struct platform_driver clk_mt2712_simple_drv = {
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++	.driver = {
++		.name = "clk-mt2712-simple",
++		.of_match_table = of_match_clk_mt2712_simple,
++	},
++};
++
+ static struct platform_driver clk_mt2712_drv = {
+ 	.probe = clk_mt2712_probe,
+ 	.driver = {
+@@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712
+ 
+ static int __init clk_mt2712_init(void)
+ {
+-	return platform_driver_register(&clk_mt2712_drv);
++	int ret = platform_driver_register(&clk_mt2712_drv);
++
++	if (ret)
++		return ret;
++	return platform_driver_register(&clk_mt2712_simple_drv);
+ }
+ 
+ arch_initcall(clk_mt2712_init);
+--- a/drivers/clk/mediatek/clk-mt7622-aud.c
++++ b/drivers/clk/mediatek/clk-mt7622-aud.c
+@@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[
+ 	GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
+ };
+ 
+-static int clk_mt7622_audiosys_init(struct platform_device *pdev)
++static const struct mtk_clk_desc audio_desc = {
++	.clks = audio_clks,
++	.num_clks = ARRAY_SIZE(audio_clks),
++};
++
++static int clk_mt7622_aud_probe(struct platform_device *pdev)
+ {
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+ 	int r;
+ 
+-	clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, audio_clks,
+-			       ARRAY_SIZE(audio_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++	r = mtk_clk_simple_probe(pdev);
+ 	if (r) {
+ 		dev_err(&pdev->dev,
+ 			"could not register clock provider: %s: %d\n",
+ 			pdev->name, r);
+ 
+-		goto err_clk_provider;
++		return r;
+ 	}
+ 
+ 	r = devm_of_platform_populate(&pdev->dev);
+@@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru
+ 	return 0;
+ 
+ err_plat_populate:
+-	of_clk_del_provider(node);
+-err_clk_provider:
++	mtk_clk_simple_remove(pdev);
+ 	return r;
+ }
+ 
+-static const struct of_device_id of_match_clk_mt7622_aud[] = {
+-	{
+-		.compatible = "mediatek,mt7622-audsys",
+-		.data = clk_mt7622_audiosys_init,
+-	}, {
+-		/* sentinel */
+-	}
+-};
+-
+-static int clk_mt7622_aud_probe(struct platform_device *pdev)
++static int clk_mt7622_aud_remove(struct platform_device *pdev)
+ {
+-	int (*clk_init)(struct platform_device *);
+-	int r;
+-
+-	clk_init = of_device_get_match_data(&pdev->dev);
+-	if (!clk_init)
+-		return -EINVAL;
+-
+-	r = clk_init(pdev);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	return r;
++	of_platform_depopulate(&pdev->dev);
++	return mtk_clk_simple_remove(pdev);
+ }
+ 
++static const struct of_device_id of_match_clk_mt7622_aud[] = {
++	{ .compatible = "mediatek,mt7622-audsys", .data = &audio_desc },
++	{ /* sentinel */ }
++};
++
+ static struct platform_driver clk_mt7622_aud_drv = {
+ 	.probe = clk_mt7622_aud_probe,
++	.remove = clk_mt7622_aud_remove,
+ 	.driver = {
+ 		.name = "clk-mt7622-aud",
+ 		.of_match_table = of_match_clk_mt7622_aud,
+--- a/drivers/clk/mediatek/clk-mt7622-eth.c
++++ b/drivers/clk/mediatek/clk-mt7622-eth.c
+@@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static int clk_mt7622_ethsys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, eth_clks,
+-			       ARRAY_SIZE(eth_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return r;
+-}
+-
+-static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
+-			       ARRAY_SIZE(sgmii_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
++static const struct mtk_clk_desc eth_desc = {
++	.clks = eth_clks,
++	.num_clks = ARRAY_SIZE(eth_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+-	return r;
+-}
++static const struct mtk_clk_desc sgmii_desc = {
++	.clks = sgmii_clks,
++	.num_clks = ARRAY_SIZE(sgmii_clks),
++};
+ 
+ static const struct of_device_id of_match_clk_mt7622_eth[] = {
+-	{
+-		.compatible = "mediatek,mt7622-ethsys",
+-		.data = clk_mt7622_ethsys_init,
+-	}, {
+-		.compatible = "mediatek,mt7622-sgmiisys",
+-		.data = clk_mt7622_sgmiisys_init,
+-	}, {
+-		/* sentinel */
+-	}
++	{ .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
++	{ .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
++	{ /* sentinel */ }
+ };
+ 
+-static int clk_mt7622_eth_probe(struct platform_device *pdev)
+-{
+-	int (*clk_init)(struct platform_device *);
+-	int r;
+-
+-	clk_init = of_device_get_match_data(&pdev->dev);
+-	if (!clk_init)
+-		return -EINVAL;
+-
+-	r = clk_init(pdev);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	return r;
+-}
+-
+ static struct platform_driver clk_mt7622_eth_drv = {
+-	.probe = clk_mt7622_eth_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt7622-eth",
+ 		.of_match_table = of_match_clk_mt7622_eth,
+--- a/drivers/clk/mediatek/clk-mt7622-hif.c
++++ b/drivers/clk/mediatek/clk-mt7622-hif.c
+@@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
+-			       ARRAY_SIZE(ssusb_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return r;
+-}
+-
+-static int clk_mt7622_pciesys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
+-			       ARRAY_SIZE(pcie_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
++static const struct mtk_clk_desc ssusb_desc = {
++	.clks = ssusb_clks,
++	.num_clks = ARRAY_SIZE(ssusb_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+-	return r;
+-}
++static const struct mtk_clk_desc pcie_desc = {
++	.clks = pcie_clks,
++	.num_clks = ARRAY_SIZE(pcie_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+ static const struct of_device_id of_match_clk_mt7622_hif[] = {
+-	{
+-		.compatible = "mediatek,mt7622-pciesys",
+-		.data = clk_mt7622_pciesys_init,
+-	}, {
+-		.compatible = "mediatek,mt7622-ssusbsys",
+-		.data = clk_mt7622_ssusbsys_init,
+-	}, {
+-		/* sentinel */
+-	}
++	{ .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc },
++	{ .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc },
++	{ /* sentinel */ }
+ };
+ 
+-static int clk_mt7622_hif_probe(struct platform_device *pdev)
+-{
+-	int (*clk_init)(struct platform_device *);
+-	int r;
+-
+-	clk_init = of_device_get_match_data(&pdev->dev);
+-	if (!clk_init)
+-		return -EINVAL;
+-
+-	r = clk_init(pdev);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	return r;
+-}
+-
+ static struct platform_driver clk_mt7622_hif_drv = {
+-	.probe = clk_mt7622_hif_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt7622-hif",
+ 		.of_match_table = of_match_clk_mt7622_hif,
+--- a/drivers/clk/mediatek/clk-mt7629-hif.c
++++ b/drivers/clk/mediatek/clk-mt7629-hif.c
+@@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk
+ 	.rst_bank_nr = ARRAY_SIZE(rst_ofs),
+ };
+ 
+-static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
+-			       ARRAY_SIZE(ssusb_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
+-
+-	return r;
+-}
+-
+-static int clk_mt7629_pciesys_init(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-
+-	clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+-
+-	mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
+-			       ARRAY_SIZE(pcie_clks), clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
++static const struct mtk_clk_desc ssusb_desc = {
++	.clks = ssusb_clks,
++	.num_clks = ARRAY_SIZE(ssusb_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+-	return r;
+-}
++static const struct mtk_clk_desc pcie_desc = {
++	.clks = pcie_clks,
++	.num_clks = ARRAY_SIZE(pcie_clks),
++	.rst_desc = &clk_rst_desc,
++};
+ 
+ static const struct of_device_id of_match_clk_mt7629_hif[] = {
+-	{
+-		.compatible = "mediatek,mt7629-pciesys",
+-		.data = clk_mt7629_pciesys_init,
+-	}, {
+-		.compatible = "mediatek,mt7629-ssusbsys",
+-		.data = clk_mt7629_ssusbsys_init,
+-	}, {
+-		/* sentinel */
+-	}
++	{ .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc },
++	{ .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc },
++	{ /* sentinel */ }
+ };
+ 
+-static int clk_mt7629_hif_probe(struct platform_device *pdev)
+-{
+-	int (*clk_init)(struct platform_device *);
+-	int r;
+-
+-	clk_init = of_device_get_match_data(&pdev->dev);
+-	if (!clk_init)
+-		return -EINVAL;
+-
+-	r = clk_init(pdev);
+-	if (r)
+-		dev_err(&pdev->dev,
+-			"could not register clock provider: %s: %d\n",
+-			pdev->name, r);
+-
+-	return r;
+-}
+-
+ static struct platform_driver clk_mt7629_hif_drv = {
+-	.probe = clk_mt7629_hif_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt7629-hif",
+ 		.of_match_table = of_match_clk_mt7629_hif,

target/linux/mediatek/patches-6.6/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch

@@ -0,0 +1,189 @@
+From 7b6183108c8ccf0dc295f39cdf78bd8078455636 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:42 +0100
+Subject: [PATCH] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe()
+
+As a preparation to increase probe functions commonization across
+various MediaTek SoC clock controller drivers, extend function
+mtk_clk_simple_probe() to be able to register not only gates, but
+also fixed clocks, factors, muxes and composites.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Miles Chen <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Tested-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++---
+ drivers/clk/mediatek/clk-mtk.h |  10 ++++
+ 2 files changed, 103 insertions(+), 8 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mtk.c
++++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -11,12 +11,14 @@
+ #include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_address.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/slab.h>
+ 
+ #include "clk-mtk.h"
+ #include "clk-gate.h"
++#include "clk-mux.h"
+ 
+ const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
+ EXPORT_SYMBOL_GPL(cg_regs_dummy);
+@@ -466,20 +468,71 @@ int mtk_clk_simple_probe(struct platform
+ 	const struct mtk_clk_desc *mcd;
+ 	struct clk_hw_onecell_data *clk_data;
+ 	struct device_node *node = pdev->dev.of_node;
+-	int r;
++	void __iomem *base;
++	int num_clks, r;
+ 
+ 	mcd = of_device_get_match_data(&pdev->dev);
+ 	if (!mcd)
+ 		return -EINVAL;
+ 
+-	clk_data = mtk_alloc_clk_data(mcd->num_clks);
++	/* Composite clocks needs us to pass iomem pointer */
++	if (mcd->composite_clks) {
++		if (!mcd->shared_io)
++			base = devm_platform_ioremap_resource(pdev, 0);
++		else
++			base = of_iomap(node, 0);
++
++		if (IS_ERR_OR_NULL(base))
++			return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM;
++	}
++
++	/* Calculate how many clk_hw_onecell_data entries to allocate */
++	num_clks = mcd->num_clks + mcd->num_composite_clks;
++	num_clks += mcd->num_fixed_clks + mcd->num_factor_clks;
++	num_clks += mcd->num_mux_clks;
++
++	clk_data = mtk_alloc_clk_data(num_clks);
+ 	if (!clk_data)
+ 		return -ENOMEM;
+ 
+-	r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
+-				   clk_data);
+-	if (r)
+-		goto free_data;
++	if (mcd->fixed_clks) {
++		r = mtk_clk_register_fixed_clks(mcd->fixed_clks,
++						mcd->num_fixed_clks, clk_data);
++		if (r)
++			goto free_data;
++	}
++
++	if (mcd->factor_clks) {
++		r = mtk_clk_register_factors(mcd->factor_clks,
++					     mcd->num_factor_clks, clk_data);
++		if (r)
++			goto unregister_fixed_clks;
++	}
++
++	if (mcd->mux_clks) {
++		r = mtk_clk_register_muxes(&pdev->dev, mcd->mux_clks,
++					   mcd->num_mux_clks, node,
++					   mcd->clk_lock, clk_data);
++		if (r)
++			goto unregister_factors;
++	};
++
++	if (mcd->composite_clks) {
++		/* We don't check composite_lock because it's optional */
++		r = mtk_clk_register_composites(&pdev->dev,
++						mcd->composite_clks,
++						mcd->num_composite_clks,
++						base, mcd->clk_lock, clk_data);
++		if (r)
++			goto unregister_muxes;
++	}
++
++	if (mcd->clks) {
++		r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks,
++					   mcd->num_clks, clk_data);
++		if (r)
++			goto unregister_composites;
++	}
+ 
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r)
+@@ -497,9 +550,28 @@ int mtk_clk_simple_probe(struct platform
+ 	return r;
+ 
+ unregister_clks:
+-	mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++	if (mcd->clks)
++		mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++unregister_composites:
++	if (mcd->composite_clks)
++		mtk_clk_unregister_composites(mcd->composite_clks,
++					      mcd->num_composite_clks, clk_data);
++unregister_muxes:
++	if (mcd->mux_clks)
++		mtk_clk_unregister_muxes(mcd->mux_clks,
++					 mcd->num_mux_clks, clk_data);
++unregister_factors:
++	if (mcd->factor_clks)
++		mtk_clk_unregister_factors(mcd->factor_clks,
++					   mcd->num_factor_clks, clk_data);
++unregister_fixed_clks:
++	if (mcd->fixed_clks)
++		mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
++					      mcd->num_fixed_clks, clk_data);
+ free_data:
+ 	mtk_free_clk_data(clk_data);
++	if (mcd->shared_io && base)
++		iounmap(base);
+ 	return r;
+ }
+ EXPORT_SYMBOL_GPL(mtk_clk_simple_probe);
+@@ -511,7 +583,20 @@ int mtk_clk_simple_remove(struct platfor
+ 	struct device_node *node = pdev->dev.of_node;
+ 
+ 	of_clk_del_provider(node);
+-	mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++	if (mcd->clks)
++		mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
++	if (mcd->composite_clks)
++		mtk_clk_unregister_composites(mcd->composite_clks,
++					      mcd->num_composite_clks, clk_data);
++	if (mcd->mux_clks)
++		mtk_clk_unregister_muxes(mcd->mux_clks,
++					 mcd->num_mux_clks, clk_data);
++	if (mcd->factor_clks)
++		mtk_clk_unregister_factors(mcd->factor_clks,
++					   mcd->num_factor_clks, clk_data);
++	if (mcd->fixed_clks)
++		mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
++					      mcd->num_fixed_clks, clk_data);
+ 	mtk_free_clk_data(clk_data);
+ 
+ 	return 0;
+--- a/drivers/clk/mediatek/clk-mtk.h
++++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -215,7 +215,17 @@ void mtk_clk_unregister_ref2usb_tx(struc
+ struct mtk_clk_desc {
+ 	const struct mtk_gate *clks;
+ 	size_t num_clks;
++	const struct mtk_composite *composite_clks;
++	size_t num_composite_clks;
++	const struct mtk_fixed_clk *fixed_clks;
++	size_t num_fixed_clks;
++	const struct mtk_fixed_factor *factor_clks;
++	size_t num_factor_clks;
++	const struct mtk_mux *mux_clks;
++	size_t num_mux_clks;
+ 	const struct mtk_clk_rst_desc *rst_desc;
++	spinlock_t *clk_lock;
++	bool shared_io;
+ };
+ 
+ int mtk_clk_simple_probe(struct platform_device *pdev);

target/linux/mediatek/patches-6.6/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch

@@ -0,0 +1,97 @@
+From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:52 +0100
+Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some
+ clocks enabled
+
+Instead of calling clk_prepare_enable() on a bunch of clocks at probe
+time, set the CLK_IS_CRITICAL flag to the same as these are required
+to be always on, and this is the right way of achieving that.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Reviewed-by: Miles Chen <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++-----------
+ 1 file changed, 24 insertions(+), 22 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
+@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[]
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
+ 			     f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
+ 			     0x1C0, 10),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
+-			     0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
++				   f_26m_adc_parents, 0x020, 0x024, 0x028,
++				   24, 1, 31, 0x1C0, 11,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	/* CLK_CFG_3 */
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
+-			     dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
+-			     0x1C0, 12),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
+-			     0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
+-			     0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
++				   dramc_md32_parents, 0x030, 0x034, 0x038,
++				   0, 1, 7, 0x1C0, 12,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
++				   sysaxi_parents, 0x030, 0x034, 0x038,
++				   8, 2, 15, 0x1C0, 13,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
++				   sysapb_parents, 0x030, 0x034, 0x038,
++				   16, 2, 23, 0x1C0, 14,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
+ 			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
+ 			     31, 0x1C0, 15),
+@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[]
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
+ 			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
+ 			     0x1C0, 21),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
+-			     sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
+-			     0x1C0, 22),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
++				   sgm_reg_parents, 0x050, 0x054, 0x058,
++				   16, 1, 23, 0x1C0, 22,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
+ 			     0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
+ 	/* CLK_CFG_6 */
+@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[]
+ 			     f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
+ 			     0x1C0, 27),
+ 	/* CLK_CFG_7 */
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
+-			     f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
+-			     0x1C0, 28),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
++				   f_26m_adc_parents, 0x070, 0x074, 0x078,
++				   0, 1, 7, 0x1C0, 28,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
+ 			     0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
+@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str
+ 			       ARRAY_SIZE(top_muxes), node,
+ 			       &mt7986_clk_lock, clk_data);
+ 
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
+-	clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
+-
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 
+ 	if (r) {

target/linux/mediatek/patches-6.6/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch

@@ -0,0 +1,88 @@
+From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Fri, 20 Jan 2023 10:20:53 +0100
+Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to
+ mtk_clk_simple_probe()
+
+There are no more non-common calls in clk_mt7986_topckgen_probe():
+migrate this driver to mtk_clk_simple_probe().
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Miles Chen <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Tested-by: Mingming Su <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++-----------------
+ 1 file changed, 13 insertions(+), 42 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
+@@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[]
+ 			     0x1C4, 5),
+ };
+ 
+-static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
+-{
+-	struct clk_hw_onecell_data *clk_data;
+-	struct device_node *node = pdev->dev.of_node;
+-	int r;
+-	void __iomem *base;
+-	int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
+-		 ARRAY_SIZE(top_muxes);
+-
+-	base = of_iomap(node, 0);
+-	if (!base) {
+-		pr_err("%s(): ioremap failed\n", __func__);
+-		return -ENOMEM;
+-	}
+-
+-	clk_data = mtk_alloc_clk_data(nr);
+-	if (!clk_data)
+-		return -ENOMEM;
+-
+-	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
+-				    clk_data);
+-	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+-	mtk_clk_register_muxes(&pdev->dev, top_muxes,
+-			       ARRAY_SIZE(top_muxes), node,
+-			       &mt7986_clk_lock, clk_data);
+-
+-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+-
+-	if (r) {
+-		pr_err("%s(): could not register clock provider: %d\n",
+-		       __func__, r);
+-		goto free_topckgen_data;
+-	}
+-	return r;
+-
+-free_topckgen_data:
+-	mtk_free_clk_data(clk_data);
+-	return r;
+-}
++static const struct mtk_clk_desc topck_desc = {
++	.fixed_clks = top_fixed_clks,
++	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
++	.factor_clks = top_divs,
++	.num_factor_clks = ARRAY_SIZE(top_divs),
++	.mux_clks = top_muxes,
++	.num_mux_clks = ARRAY_SIZE(top_muxes),
++	.clk_lock = &mt7986_clk_lock,
++};
+ 
+ static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
+-	{ .compatible = "mediatek,mt7986-topckgen", },
+-	{}
++	{ .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc },
++	{ /* sentinel */ }
+ };
+ 
+ static struct platform_driver clk_mt7986_topckgen_drv = {
+-	.probe = clk_mt7986_topckgen_probe,
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
+ 	.driver = {
+ 		.name = "clk-mt7986-topckgen",
+ 		.of_match_table = of_match_clk_mt7986_topckgen,

target/linux/mediatek/patches-6.6/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch

@@ -0,0 +1,38 @@
+From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <[email protected]>
+Date: Mon, 6 Mar 2023 15:05:21 +0100
+Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set
+ critical clock
+
+Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
+flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
+
+Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Chen-Yu Tsai <[email protected]>
+Tested-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
++++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
+@@ -42,7 +42,7 @@
+ 		 "clkxtal")
+ 
+ static const struct mtk_pll_data plls[] = {
+-	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
++	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
+ 	    0x0200, 4, 0, 0x0204, 0),
+ 	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
+ 	    0x0210, 4, 0, 0x0214, 0),
+@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru
+ 
+ 	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+ 
+-	clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
+-
+ 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ 	if (r) {
+ 		pr_err("%s(): could not register clock provider: %d\n",

target/linux/mediatek/patches-6.6/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch

@@ -0,0 +1,237 @@
+From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Thu, 26 Jan 2023 03:34:05 +0000
+Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs
+
+Add MT7981 clock dt-bindings, include topckgen, apmixedsys,
+infracfg, and ethernet subsystem clocks.
+
+Acked-by: Krzysztof Kozlowski <[email protected]>
+Signed-off-by: Jianhui Zhao <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ .../dt-bindings/clock/mediatek,mt7981-clk.h   | 215 ++++++++++++++++++
+ 1 file changed, 215 insertions(+)
+ create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h
+@@ -0,0 +1,215 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Wenzhen.Yu <[email protected]>
++ * Author: Jianhui Zhao <[email protected]>
++ * Author: Daniel Golle <[email protected]>
++ */
++
++#ifndef _DT_BINDINGS_CLK_MT7981_H
++#define _DT_BINDINGS_CLK_MT7981_H
++
++/* TOPCKGEN */
++#define CLK_TOP_CB_CKSQ_40M		0
++#define CLK_TOP_CB_M_416M		1
++#define CLK_TOP_CB_M_D2			2
++#define CLK_TOP_CB_M_D3			3
++#define CLK_TOP_M_D3_D2			4
++#define CLK_TOP_CB_M_D4			5
++#define CLK_TOP_CB_M_D8			6
++#define CLK_TOP_M_D8_D2			7
++#define CLK_TOP_CB_MM_720M		8
++#define CLK_TOP_CB_MM_D2		9
++#define CLK_TOP_CB_MM_D3		10
++#define CLK_TOP_CB_MM_D3_D5		11
++#define CLK_TOP_CB_MM_D4		12
++#define CLK_TOP_CB_MM_D6		13
++#define CLK_TOP_MM_D6_D2		14
++#define CLK_TOP_CB_MM_D8		15
++#define CLK_TOP_CB_APLL2_196M		16
++#define CLK_TOP_APLL2_D2		17
++#define CLK_TOP_APLL2_D4		18
++#define CLK_TOP_NET1_2500M		19
++#define CLK_TOP_CB_NET1_D4		20
++#define CLK_TOP_CB_NET1_D5		21
++#define CLK_TOP_NET1_D5_D2		22
++#define CLK_TOP_NET1_D5_D4		23
++#define CLK_TOP_CB_NET1_D8		24
++#define CLK_TOP_NET1_D8_D2		25
++#define CLK_TOP_NET1_D8_D4		26
++#define CLK_TOP_CB_NET2_800M		27
++#define CLK_TOP_CB_NET2_D2		28
++#define CLK_TOP_CB_NET2_D4		29
++#define CLK_TOP_NET2_D4_D2		30
++#define CLK_TOP_NET2_D4_D4		31
++#define CLK_TOP_CB_NET2_D6		32
++#define CLK_TOP_CB_WEDMCU_208M		33
++#define CLK_TOP_CB_SGM_325M		34
++#define CLK_TOP_CKSQ_40M_D2		35
++#define CLK_TOP_CB_RTC_32K		36
++#define CLK_TOP_CB_RTC_32P7K		37
++#define CLK_TOP_USB_TX250M		38
++#define CLK_TOP_FAUD			39
++#define CLK_TOP_NFI1X			40
++#define CLK_TOP_USB_EQ_RX250M		41
++#define CLK_TOP_USB_CDR_CK		42
++#define CLK_TOP_USB_LN0_CK		43
++#define CLK_TOP_SPINFI_BCK		44
++#define CLK_TOP_SPI			45
++#define CLK_TOP_SPIM_MST		46
++#define CLK_TOP_UART_BCK		47
++#define CLK_TOP_PWM_BCK			48
++#define CLK_TOP_I2C_BCK			49
++#define CLK_TOP_PEXTP_TL		50
++#define CLK_TOP_EMMC_208M		51
++#define CLK_TOP_EMMC_400M		52
++#define CLK_TOP_DRAMC_REF		53
++#define CLK_TOP_DRAMC_MD32		54
++#define CLK_TOP_SYSAXI			55
++#define CLK_TOP_SYSAPB			56
++#define CLK_TOP_ARM_DB_MAIN		57
++#define CLK_TOP_AP2CNN_HOST		58
++#define CLK_TOP_NETSYS			59
++#define CLK_TOP_NETSYS_500M		60
++#define CLK_TOP_NETSYS_WED_MCU		61
++#define CLK_TOP_NETSYS_2X		62
++#define CLK_TOP_SGM_325M		63
++#define CLK_TOP_SGM_REG			64
++#define CLK_TOP_F26M			65
++#define CLK_TOP_EIP97B			66
++#define CLK_TOP_USB3_PHY		67
++#define CLK_TOP_AUD			68
++#define CLK_TOP_A1SYS			69
++#define CLK_TOP_AUD_L			70
++#define CLK_TOP_A_TUNER			71
++#define CLK_TOP_U2U3_REF		72
++#define CLK_TOP_U2U3_SYS		73
++#define CLK_TOP_U2U3_XHCI		74
++#define CLK_TOP_USB_FRMCNT		75
++#define CLK_TOP_NFI1X_SEL		76
++#define CLK_TOP_SPINFI_SEL		77
++#define CLK_TOP_SPI_SEL			78
++#define CLK_TOP_SPIM_MST_SEL		79
++#define CLK_TOP_UART_SEL		80
++#define CLK_TOP_PWM_SEL			81
++#define CLK_TOP_I2C_SEL			82
++#define CLK_TOP_PEXTP_TL_SEL		83
++#define CLK_TOP_EMMC_208M_SEL		84
++#define CLK_TOP_EMMC_400M_SEL		85
++#define CLK_TOP_F26M_SEL		86
++#define CLK_TOP_DRAMC_SEL		87
++#define CLK_TOP_DRAMC_MD32_SEL		88
++#define CLK_TOP_SYSAXI_SEL		89
++#define CLK_TOP_SYSAPB_SEL		90
++#define CLK_TOP_ARM_DB_MAIN_SEL		91
++#define CLK_TOP_AP2CNN_HOST_SEL		92
++#define CLK_TOP_NETSYS_SEL		93
++#define CLK_TOP_NETSYS_500M_SEL		94
++#define CLK_TOP_NETSYS_MCU_SEL		95
++#define CLK_TOP_NETSYS_2X_SEL		96
++#define CLK_TOP_SGM_325M_SEL		97
++#define CLK_TOP_SGM_REG_SEL		98
++#define CLK_TOP_EIP97B_SEL		99
++#define CLK_TOP_USB3_PHY_SEL		100
++#define CLK_TOP_AUD_SEL			101
++#define CLK_TOP_A1SYS_SEL		102
++#define CLK_TOP_AUD_L_SEL		103
++#define CLK_TOP_A_TUNER_SEL		104
++#define CLK_TOP_U2U3_SEL		105
++#define CLK_TOP_U2U3_SYS_SEL		106
++#define CLK_TOP_U2U3_XHCI_SEL		107
++#define CLK_TOP_USB_FRMCNT_SEL		108
++#define CLK_TOP_AUD_I2S_M		109
++
++/* INFRACFG */
++#define CLK_INFRA_66M_MCK		0
++#define CLK_INFRA_UART0_SEL		1
++#define CLK_INFRA_UART1_SEL		2
++#define CLK_INFRA_UART2_SEL		3
++#define CLK_INFRA_SPI0_SEL		4
++#define CLK_INFRA_SPI1_SEL		5
++#define CLK_INFRA_SPI2_SEL		6
++#define CLK_INFRA_PWM1_SEL		7
++#define CLK_INFRA_PWM2_SEL		8
++#define CLK_INFRA_PWM3_SEL		9
++#define CLK_INFRA_PWM_BSEL		10
++#define CLK_INFRA_PCIE_SEL		11
++#define CLK_INFRA_GPT_STA		12
++#define CLK_INFRA_PWM_HCK		13
++#define CLK_INFRA_PWM_STA		14
++#define CLK_INFRA_PWM1_CK		15
++#define CLK_INFRA_PWM2_CK		16
++#define CLK_INFRA_PWM3_CK		17
++#define CLK_INFRA_CQ_DMA_CK		18
++#define CLK_INFRA_AUD_BUS_CK		19
++#define CLK_INFRA_AUD_26M_CK		20
++#define CLK_INFRA_AUD_L_CK		21
++#define CLK_INFRA_AUD_AUD_CK		22
++#define CLK_INFRA_AUD_EG2_CK		23
++#define CLK_INFRA_DRAMC_26M_CK		24
++#define CLK_INFRA_DBG_CK		25
++#define CLK_INFRA_AP_DMA_CK		26
++#define CLK_INFRA_SEJ_CK		27
++#define CLK_INFRA_SEJ_13M_CK		28
++#define CLK_INFRA_THERM_CK		29
++#define CLK_INFRA_I2C0_CK		30
++#define CLK_INFRA_UART0_CK		31
++#define CLK_INFRA_UART1_CK		32
++#define CLK_INFRA_UART2_CK		33
++#define CLK_INFRA_SPI2_CK		34
++#define CLK_INFRA_SPI2_HCK_CK		35
++#define CLK_INFRA_NFI1_CK		36
++#define CLK_INFRA_SPINFI1_CK		37
++#define CLK_INFRA_NFI_HCK_CK		38
++#define CLK_INFRA_SPI0_CK		39
++#define CLK_INFRA_SPI1_CK		40
++#define CLK_INFRA_SPI0_HCK_CK		41
++#define CLK_INFRA_SPI1_HCK_CK		42
++#define CLK_INFRA_FRTC_CK		43
++#define CLK_INFRA_MSDC_CK		44
++#define CLK_INFRA_MSDC_HCK_CK		45
++#define CLK_INFRA_MSDC_133M_CK		46
++#define CLK_INFRA_MSDC_66M_CK		47
++#define CLK_INFRA_ADC_26M_CK		48
++#define CLK_INFRA_ADC_FRC_CK		49
++#define CLK_INFRA_FBIST2FPC_CK		50
++#define CLK_INFRA_I2C_MCK_CK		51
++#define CLK_INFRA_I2C_PCK_CK		52
++#define CLK_INFRA_IUSB_133_CK		53
++#define CLK_INFRA_IUSB_66M_CK		54
++#define CLK_INFRA_IUSB_SYS_CK		55
++#define CLK_INFRA_IUSB_CK		56
++#define CLK_INFRA_IPCIE_CK		57
++#define CLK_INFRA_IPCIE_PIPE_CK		58
++#define CLK_INFRA_IPCIER_CK		59
++#define CLK_INFRA_IPCIEB_CK		60
++
++/* APMIXEDSYS */
++#define CLK_APMIXED_ARMPLL		0
++#define CLK_APMIXED_NET2PLL		1
++#define CLK_APMIXED_MMPLL		2
++#define CLK_APMIXED_SGMPLL		3
++#define CLK_APMIXED_WEDMCUPLL		4
++#define CLK_APMIXED_NET1PLL		5
++#define CLK_APMIXED_MPLL		6
++#define CLK_APMIXED_APLL2		7
++
++/* SGMIISYS_0 */
++#define CLK_SGM0_TX_EN			0
++#define CLK_SGM0_RX_EN			1
++#define CLK_SGM0_CK0_EN			2
++#define CLK_SGM0_CDR_CK0_EN		3
++
++/* SGMIISYS_1 */
++#define CLK_SGM1_TX_EN			0
++#define CLK_SGM1_RX_EN			1
++#define CLK_SGM1_CK1_EN			2
++#define CLK_SGM1_CDR_CK1_EN		3
++
++/* ETHSYS */
++#define CLK_ETH_FE_EN			0
++#define CLK_ETH_GP2_EN			1
++#define CLK_ETH_GP1_EN			2
++#define CLK_ETH_WOCPU0_EN		3
++
++#endif /* _DT_BINDINGS_CLK_MT7981_H */

target/linux/mediatek/patches-6.6/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch

@@ -0,0 +1,932 @@
+From 8efeeb9c8b4ecf4fb4a74be9403aba951403bbaa Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Thu, 26 Jan 2023 03:34:24 +0000
+Subject: [PATCH] clk: mediatek: add MT7981 clock support
+
+Add MT7981 clock support, include topckgen, apmixedsys, infracfg and
+ethernet subsystem clocks.
+
+The drivers are based on clk-mt7981.c which can be found in MediaTek's
+SDK sources. To be fit for upstream inclusion the driver has been split
+into clock domains and the infracfg part has been significantly
+de-bloated by removing all the 1:1 factors (aliases).
+
+Signed-off-by: Jianhui Zhao <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+[[email protected]: Add module license]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/Kconfig               |  17 +
+ drivers/clk/mediatek/Makefile              |   4 +
+ drivers/clk/mediatek/clk-mt7981-apmixed.c  | 102 +++++
+ drivers/clk/mediatek/clk-mt7981-eth.c      | 118 ++++++
+ drivers/clk/mediatek/clk-mt7981-infracfg.c | 207 ++++++++++
+ drivers/clk/mediatek/clk-mt7981-topckgen.c | 422 +++++++++++++++++++++
+ 6 files changed, 870 insertions(+)
+ create mode 100644 drivers/clk/mediatek/clk-mt7981-apmixed.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7981-eth.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7981-infracfg.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7981-topckgen.c
+
+--- a/drivers/clk/mediatek/Kconfig
++++ b/drivers/clk/mediatek/Kconfig
+@@ -381,6 +381,23 @@ config COMMON_CLK_MT7629_HIFSYS
+ 	  This driver supports MediaTek MT7629 HIFSYS clocks providing
+ 	  to PCI-E and USB.
+ 
++config COMMON_CLK_MT7981
++	bool "Clock driver for MediaTek MT7981"
++	depends on ARCH_MEDIATEK || COMPILE_TEST
++	select COMMON_CLK_MEDIATEK
++	default ARCH_MEDIATEK
++	help
++	  This driver supports MediaTek MT7981 basic clocks and clocks
++	  required for various peripherals found on this SoC.
++
++config COMMON_CLK_MT7981_ETHSYS
++	tristate "Clock driver for MediaTek MT7981 ETHSYS"
++	depends on COMMON_CLK_MT7981
++	default COMMON_CLK_MT7981
++	help
++	  This driver adds support for clocks for Ethernet and SGMII
++	  required on MediaTek MT7981 SoC.
++
+ config COMMON_CLK_MT7986
+ 	bool "Clock driver for MediaTek MT7986"
+ 	depends on ARCH_MEDIATEK || COMPILE_TEST
+--- a/drivers/clk/mediatek/Makefile
++++ b/drivers/clk/mediatek/Makefile
+@@ -52,6 +52,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
+ obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
+ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
+ obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o
++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
++obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
++obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c
+@@ -0,0 +1,102 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ * Author: Wenzhen Yu <[email protected]>
++ * Author: Jianhui Zhao <[email protected]>
++ * Author: Daniel Golle <[email protected]>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++
++#include "clk-gate.h"
++#include "clk-mtk.h"
++#include "clk-mux.h"
++#include "clk-pll.h"
++
++#include <dt-bindings/clock/mediatek,mt7981-clk.h>
++#include <linux/clk.h>
++
++#define MT7981_PLL_FMAX (2500UL * MHZ)
++#define CON0_MT7981_RST_BAR BIT(27)
++
++#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
++		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \
++		 _div_table, _parent_name)                                     \
++	{                                                                      \
++		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \
++		.en_mask = _en_mask, .flags = _flags,                          \
++		.rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX,  \
++		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
++		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \
++		.pcw_shift = _pcw_shift, .div_table = _div_table,              \
++		.parent_name = _parent_name,                                   \
++	}
++
++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \
++	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \
++	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \
++		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \
++		 "clkxtal")
++
++static const struct mtk_pll_data plls[] = {
++	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
++	    32, 0x0200, 4, 0, 0x0204, 0),
++	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
++	    0x0210, 4, 0, 0x0214, 0),
++	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
++	    0x0220, 4, 0, 0x0224, 0),
++	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
++	    0x0230, 4, 0, 0x0234, 0),
++	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
++	    0x0240, 4, 0, 0x0244, 0),
++	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
++	    0x0250, 4, 0, 0x0254, 0),
++	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
++	    0x0260, 4, 0, 0x0264, 0),
++	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
++	    0x0278, 4, 0, 0x027C, 0),
++};
++
++static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
++	{ .compatible = "mediatek,mt7981-apmixedsys", },
++	{ /* sentinel */ }
++};
++
++static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
++{
++	struct clk_hw_onecell_data *clk_data;
++	struct device_node *node = pdev->dev.of_node;
++	int r;
++
++	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
++	if (!clk_data)
++		return -ENOMEM;
++
++	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
++
++	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++	if (r) {
++		pr_err("%s(): could not register clock provider: %d\n",
++		       __func__, r);
++		goto free_apmixed_data;
++	}
++	return r;
++
++free_apmixed_data:
++	mtk_free_clk_data(clk_data);
++	return r;
++}
++
++static struct platform_driver clk_mt7981_apmixed_drv = {
++	.probe = clk_mt7981_apmixed_probe,
++	.driver = {
++		.name = "clk-mt7981-apmixed",
++		.of_match_table = of_match_clk_mt7981_apmixed,
++	},
++};
++builtin_platform_driver(clk_mt7981_apmixed_drv);
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7981-eth.c
+@@ -0,0 +1,118 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ * Author: Wenzhen Yu <[email protected]>
++ * Author: Jianhui Zhao <[email protected]>
++ * Author: Daniel Golle <[email protected]>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++
++#include "clk-mtk.h"
++#include "clk-gate.h"
++
++#include <dt-bindings/clock/mediatek,mt7981-clk.h>
++
++static const struct mtk_gate_regs sgmii0_cg_regs = {
++	.set_ofs = 0xE4,
++	.clr_ofs = 0xE4,
++	.sta_ofs = 0xE4,
++};
++
++#define GATE_SGMII0(_id, _name, _parent, _shift) {	\
++		.id = _id,				\
++		.name = _name,				\
++		.parent_name = _parent,			\
++		.regs = &sgmii0_cg_regs,			\
++		.shift = _shift,			\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
++	}
++
++static const struct mtk_gate sgmii0_clks[] __initconst = {
++	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
++	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
++	GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
++	GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
++};
++
++static const struct mtk_gate_regs sgmii1_cg_regs = {
++	.set_ofs = 0xE4,
++	.clr_ofs = 0xE4,
++	.sta_ofs = 0xE4,
++};
++
++#define GATE_SGMII1(_id, _name, _parent, _shift) {	\
++		.id = _id,				\
++		.name = _name,				\
++		.parent_name = _parent,			\
++		.regs = &sgmii1_cg_regs,			\
++		.shift = _shift,			\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
++	}
++
++static const struct mtk_gate sgmii1_clks[] __initconst = {
++	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
++	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
++	GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
++	GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
++};
++
++static const struct mtk_gate_regs eth_cg_regs = {
++	.set_ofs = 0x30,
++	.clr_ofs = 0x30,
++	.sta_ofs = 0x30,
++};
++
++#define GATE_ETH(_id, _name, _parent, _shift) {	\
++		.id = _id,				\
++		.name = _name,				\
++		.parent_name = _parent,			\
++		.regs = &eth_cg_regs,			\
++		.shift = _shift,			\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
++	}
++
++static const struct mtk_gate eth_clks[] __initconst = {
++	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
++	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
++	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
++	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
++};
++
++static const struct mtk_clk_desc eth_desc = {
++	.clks = eth_clks,
++	.num_clks = ARRAY_SIZE(eth_clks),
++};
++
++static const struct mtk_clk_desc sgmii0_desc = {
++	.clks = sgmii0_clks,
++	.num_clks = ARRAY_SIZE(sgmii0_clks),
++};
++
++static const struct mtk_clk_desc sgmii1_desc = {
++	.clks = sgmii1_clks,
++	.num_clks = ARRAY_SIZE(sgmii1_clks),
++};
++
++static const struct of_device_id of_match_clk_mt7981_eth[] = {
++	{ .compatible = "mediatek,mt7981-ethsys", .data = &eth_desc },
++	{ .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc },
++	{ .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc },
++	{ /* sentinel */ }
++};
++
++static struct platform_driver clk_mt7981_eth_drv = {
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++	.driver = {
++		.name = "clk-mt7981-eth",
++		.of_match_table = of_match_clk_mt7981_eth,
++	},
++};
++module_platform_driver(clk_mt7981_eth_drv);
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c
+@@ -0,0 +1,207 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ * Author: Wenzhen Yu <[email protected]>
++ * Author: Jianhui Zhao <[email protected]>
++ * Author: Daniel Golle <[email protected]>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++
++#include <dt-bindings/clock/mediatek,mt7981-clk.h>
++#include <linux/clk.h>
++
++static DEFINE_SPINLOCK(mt7981_clk_lock);
++
++static const struct mtk_fixed_factor infra_divs[] = {
++	FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
++};
++
++static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
++								"uart_sel" };
++
++static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
++							      "spi_sel" };
++
++static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
++							      "spim_mst_sel" };
++
++static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
++
++static const char *const infra_pwm_bsel_parents[] __initconst = {
++	"cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
++};
++
++static const char *const infra_pcie_parents[] __initconst = {
++	"cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
++};
++
++static const struct mtk_mux infra_muxes[] = {
++	/* MODULE_CLK_SEL_0 */
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
++			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
++			     -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
++			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
++			     -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
++			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
++			     -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
++			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
++			     -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
++			     infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
++			     -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
++			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
++			     -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
++			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
++			     -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
++			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
++			     -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
++			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
++			     -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
++			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
++			     2, -1, -1, -1),
++	/* MODULE_CLK_SEL_1 */
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
++			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
++			     -1, -1, -1),
++};
++
++static const struct mtk_gate_regs infra0_cg_regs = {
++	.set_ofs = 0x40,
++	.clr_ofs = 0x44,
++	.sta_ofs = 0x48,
++};
++
++static const struct mtk_gate_regs infra1_cg_regs = {
++	.set_ofs = 0x50,
++	.clr_ofs = 0x54,
++	.sta_ofs = 0x58,
++};
++
++static const struct mtk_gate_regs infra2_cg_regs = {
++	.set_ofs = 0x60,
++	.clr_ofs = 0x64,
++	.sta_ofs = 0x68,
++};
++
++#define GATE_INFRA0(_id, _name, _parent, _shift)                               \
++	{                                                                      \
++		.id = _id, .name = _name, .parent_name = _parent,              \
++		.regs = &infra0_cg_regs, .shift = _shift,                      \
++		.ops = &mtk_clk_gate_ops_setclr,                               \
++	}
++
++#define GATE_INFRA1(_id, _name, _parent, _shift)                               \
++	{                                                                      \
++		.id = _id, .name = _name, .parent_name = _parent,              \
++		.regs = &infra1_cg_regs, .shift = _shift,                      \
++		.ops = &mtk_clk_gate_ops_setclr,                               \
++	}
++
++#define GATE_INFRA2(_id, _name, _parent, _shift)                               \
++	{                                                                      \
++		.id = _id, .name = _name, .parent_name = _parent,              \
++		.regs = &infra2_cg_regs, .shift = _shift,                      \
++		.ops = &mtk_clk_gate_ops_setclr,                               \
++	}
++
++static const struct mtk_gate infra_clks[] = {
++	/* INFRA0 */
++	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
++	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
++	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
++	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
++	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
++	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
++
++	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
++	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
++	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
++	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
++	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
++	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
++		    14),
++	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
++	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
++	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
++	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
++	GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
++	/* INFRA1 */
++	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
++	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
++	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
++	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
++	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
++	GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
++	GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
++	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
++	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
++	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
++	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
++	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
++	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
++		    13),
++	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
++		    14),
++	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
++	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
++	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
++	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
++	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
++	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
++	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
++	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
++	GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
++	GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
++	/* INFRA2 */
++	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
++	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
++	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
++	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
++	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
++	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
++		    13),
++	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
++	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
++};
++
++static const struct mtk_clk_desc infracfg_desc = {
++	.factor_clks = infra_divs,
++	.num_factor_clks = ARRAY_SIZE(infra_divs),
++	.mux_clks = infra_muxes,
++	.num_mux_clks = ARRAY_SIZE(infra_muxes),
++	.clks = infra_clks,
++	.num_clks = ARRAY_SIZE(infra_clks),
++	.clk_lock = &mt7981_clk_lock,
++};
++
++static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
++	{ .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc },
++	{ /* sentinel */ }
++};
++
++static struct platform_driver clk_mt7981_infracfg_drv = {
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++	.driver = {
++		.name = "clk-mt7981-infracfg",
++		.of_match_table = of_match_clk_mt7981_infracfg,
++	},
++};
++builtin_platform_driver(clk_mt7981_infracfg_drv);
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
+@@ -0,0 +1,422 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ * Author: Wenzhen Yu <[email protected]>
++ * Author: Jianhui Zhao <[email protected]>
++ */
++
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++
++#include <dt-bindings/clock/mediatek,mt7981-clk.h>
++#include <linux/clk.h>
++
++static DEFINE_SPINLOCK(mt7981_clk_lock);
++
++static const struct mtk_fixed_factor top_divs[] = {
++	FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
++	FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
++	FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
++	FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
++	FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
++	FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
++	FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
++	FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
++	FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
++	FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
++	FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
++	FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
++	FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
++	FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
++	FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
++	FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
++	FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
++	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
++	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
++	FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
++	FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
++	FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
++	FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
++	FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
++	FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
++	FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
++	FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
++	FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
++	FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
++	FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
++	FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
++	FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
++	FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
++	FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
++	FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
++	FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
++	FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
++	FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
++	FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
++	FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
++	FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
++	FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
++	FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
++	FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
++	FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
++	FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
++	FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
++	FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
++	FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
++	FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
++	FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
++	FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
++	FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
++	FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
++	FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
++	FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
++	FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
++	FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
++	FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
++	FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
++	FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
++	FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
++	FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
++	FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
++	FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
++	FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
++	FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
++	FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
++	FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
++	FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
++	FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
++	FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
++	FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
++	FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
++	FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
++	FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
++};
++
++static const char * const nfi1x_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_mm_d4",
++	"net1_d8_d2",
++	"cb_net2_d6",
++	"cb_m_d4",
++	"cb_mm_d8",
++	"net1_d8_d4",
++	"cb_m_d8"
++};
++
++static const char * const spinfi_parents[] __initconst = {
++	"cksq_40m_d2",
++	"cb_cksq_40m",
++	"net1_d5_d4",
++	"cb_m_d4",
++	"cb_mm_d8",
++	"net1_d8_d4",
++	"mm_d6_d2",
++	"cb_m_d8"
++};
++
++static const char * const spi_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_m_d2",
++	"cb_mm_d4",
++	"net1_d8_d2",
++	"cb_net2_d6",
++	"net1_d5_d4",
++	"cb_m_d4",
++	"net1_d8_d4"
++};
++
++static const char * const uart_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_m_d8",
++	"m_d8_d2"
++};
++
++static const char * const pwm_parents[] __initconst = {
++	"cb_cksq_40m",
++	"net1_d8_d2",
++	"net1_d5_d4",
++	"cb_m_d4",
++	"m_d8_d2",
++	"cb_rtc_32k"
++};
++
++static const char * const i2c_parents[] __initconst = {
++	"cb_cksq_40m",
++	"net1_d5_d4",
++	"cb_m_d4",
++	"net1_d8_d4"
++};
++
++static const char * const pextp_tl_ck_parents[] __initconst = {
++	"cb_cksq_40m",
++	"net1_d5_d4",
++	"cb_m_d4",
++	"cb_rtc_32k"
++};
++
++static const char * const emmc_208m_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_m_d2",
++	"cb_net2_d4",
++	"cb_apll2_196m",
++	"cb_mm_d4",
++	"net1_d8_d2",
++	"cb_mm_d6"
++};
++
++static const char * const emmc_400m_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_net2_d2",
++	"cb_mm_d2",
++	"cb_net2_d2"
++};
++
++static const char * const csw_f26m_parents[] __initconst = {
++	"cksq_40m_d2",
++	"m_d8_d2"
++};
++
++static const char * const dramc_md32_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_m_d2",
++	"cb_wedmcu_208m"
++};
++
++static const char * const sysaxi_parents[] __initconst = {
++	"cb_cksq_40m",
++	"net1_d8_d2"
++};
++
++static const char * const sysapb_parents[] __initconst = {
++	"cb_cksq_40m",
++	"m_d3_d2"
++};
++
++static const char * const arm_db_main_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_net2_d6"
++};
++
++static const char * const ap2cnn_host_parents[] __initconst = {
++	"cb_cksq_40m",
++	"net1_d8_d4"
++};
++
++static const char * const netsys_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_mm_d2"
++};
++
++static const char * const netsys_500m_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_net1_d5"
++};
++
++static const char * const netsys_mcu_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_mm_720m",
++	"cb_net1_d4",
++	"cb_net1_d5",
++	"cb_m_416m"
++};
++
++static const char * const netsys_2x_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_net2_800m",
++	"cb_mm_720m"
++};
++
++static const char * const sgm_325m_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_sgm_325m"
++};
++
++static const char * const sgm_reg_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_net2_d4"
++};
++
++static const char * const eip97b_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_net1_d5",
++	"cb_m_416m",
++	"cb_mm_d2",
++	"net1_d5_d2"
++};
++
++static const char * const aud_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_apll2_196m"
++};
++
++static const char * const a1sys_parents[] __initconst = {
++	"cb_cksq_40m",
++	"apll2_d4"
++};
++
++static const char * const aud_l_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_apll2_196m",
++	"m_d8_d2"
++};
++
++static const char * const a_tuner_parents[] __initconst = {
++	"cb_cksq_40m",
++	"apll2_d4",
++	"m_d8_d2"
++};
++
++static const char * const u2u3_parents[] __initconst = {
++	"cb_cksq_40m",
++	"m_d8_d2"
++};
++
++static const char * const u2u3_sys_parents[] __initconst = {
++	"cb_cksq_40m",
++	"net1_d5_d4"
++};
++
++static const char * const usb_frmcnt_parents[] __initconst = {
++	"cb_cksq_40m",
++	"cb_mm_d3_d5"
++};
++
++static const struct mtk_mux top_muxes[] = {
++	/* CLK_CFG_0 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
++			     0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
++			     0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
++			     0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
++			     0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
++	/* CLK_CFG_1 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
++			     0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
++			     0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
++			     0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
++			     pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
++			     0x1C0, 7),
++	/* CLK_CFG_2 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
++			     emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
++			     0x1C0, 8),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
++			     emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
++			     0x1C0, 9),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
++				   csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
++				   0x1C0, 10,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
++				   csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
++				   31, 0x1C0, 11,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++	/* CLK_CFG_3 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
++				   dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
++				   7, 0x1C0, 12,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
++				   sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
++				   0x1C0, 13,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
++				   sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
++				   23, 0x1C0, 14,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
++			     arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
++			     0x1C0, 15),
++	/* CLK_CFG_4 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
++			     ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
++			     0x1C0, 16),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
++			     0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
++			     netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
++			     0x1C0, 18),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
++			     netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
++			     0x1C0, 19),
++	/* CLK_CFG_5 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
++			     netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
++			     0x1C0, 20),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
++			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
++			     0x1C0, 21),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
++			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
++			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
++	/* CLK_CFG_6 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
++			     csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
++			     7, 0x1C0, 24),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
++			     0x064, 0x068, 8, 1, 15, 0x1C0, 25),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
++			     0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
++			     0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
++	/* CLK_CFG_7 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
++			     a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
++			     0x1C0, 28),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
++			     0x074, 0x078, 8, 1, 15, 0x1C0, 29),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
++			     u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
++			     0x1C0, 30),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
++			     u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
++			     0x1C4, 0),
++	/* CLK_CFG_8 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
++			     usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
++			     0x1C4, 1),
++};
++
++static struct mtk_composite top_aud_divs[] = {
++	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
++		0x0420, 0, 0x0420, 8, 8),
++};
++
++static const struct mtk_clk_desc topck_desc = {
++	.factor_clks = top_divs,
++	.num_factor_clks = ARRAY_SIZE(top_divs),
++	.mux_clks = top_muxes,
++	.num_mux_clks = ARRAY_SIZE(top_muxes),
++	.composite_clks = top_aud_divs,
++	.num_composite_clks = ARRAY_SIZE(top_aud_divs),
++	.clk_lock = &mt7981_clk_lock,
++};
++
++static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
++	{ .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc },
++	{ /* sentinel */ }
++};
++
++static struct platform_driver clk_mt7981_topckgen_drv = {
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++	.driver = {
++		.name = "clk-mt7981-topckgen",
++		.of_match_table = of_match_clk_mt7981_topckgen,
++	},
++};
++builtin_platform_driver(clk_mt7981_topckgen_drv);

target/linux/mediatek/patches-6.6/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch

@@ -0,0 +1,30 @@
+From fc157139e6b7f8dfb6430ac7191ba754027705e8 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Sun, 18 Feb 2024 01:59:59 +0000
+Subject: [PATCH] clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
+
+Without the SGM_REG_SEL clock enabled the system freezes if trying to
+access registers used by MT7981 clock drivers itself.
+Mark SGM_REG_SEL as critical to make sure it is always enabled to
+prevent freezes on boot depending on probe order.
+
+Fixes: 813c3b53b55ba ("clk: mediatek: add MT7981 clock support")
+Signed-off-by: Daniel Golle <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7981-topckgen.c
++++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
+@@ -359,8 +359,9 @@ static const struct mtk_mux top_muxes[]
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
+ 			     sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
+ 			     0x1C0, 21),
+-	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
+-			     0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
++				   0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22,
++				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ 	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
+ 			     0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
+ 	/* CLK_CFG_6 */

target/linux/mediatek/patches-6.6/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch

@@ -0,0 +1,26 @@
+--- a/drivers/pinctrl/mediatek/Kconfig
++++ b/drivers/pinctrl/mediatek/Kconfig
+@@ -141,6 +141,13 @@ config PINCTRL_MT7986
+ 	default ARM64 && ARCH_MEDIATEK
+ 	select PINCTRL_MTK_MOORE
+ 
++config PINCTRL_MT7988
++	bool "Mediatek MT7988 pin control"
++	depends on OF
++	depends on ARM64 || COMPILE_TEST
++	default ARCH_MEDIATEK
++	select PINCTRL_MTK_MOORE
++
+ config PINCTRL_MT8167
+ 	bool "Mediatek MT8167 pin control"
+ 	depends on OF
+--- a/drivers/pinctrl/mediatek/Makefile
++++ b/drivers/pinctrl/mediatek/Makefile
+@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-
+ obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
+ obj-$(CONFIG_PINCTRL_MT7981)	+= pinctrl-mt7981.o
+ obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
++obj-$(CONFIG_PINCTRL_MT7988)	+= pinctrl-mt7988.o
+ obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
+ obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
+ obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o

target/linux/mediatek/patches-6.6/241-v6.3-dt-bindings-clock-Add-compatibles-for-MT7981.patch

@@ -0,0 +1,75 @@
+From cc4d9e0c77494fcf6bccbc57e23db0007cf681b7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Thu, 26 Jan 2023 03:33:46 +0000
+Subject: [PATCH] dt-bindings: clock: Add compatibles for MT7981
+
+Add compatible string for MT7981 to existing bindings at
+ - mediatek,apmixedsys.yaml
+ - mediatek,topckgen.yaml
+ - mediatek,ethsys.txt
+ - mediatek,infracfg.yaml
+ - mediatek,sgmiisys.txt
+
+Signed-off-by: Jianhui Zhao <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+Link: https://lore.kernel.org/r/cc85ee470c781ff4013f6c21c92c0a21574b12b2.1674703830.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt        | 1 +
+ .../devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml     | 1 +
+ .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt      | 2 ++
+ .../devicetree/bindings/clock/mediatek,apmixedsys.yaml          | 1 +
+ Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml  | 1 +
+ 5 files changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+@@ -10,6 +10,7 @@ Required Properties:
+ 	- "mediatek,mt7622-ethsys", "syscon"
+ 	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
+ 	- "mediatek,mt7629-ethsys", "syscon"
++	- "mediatek,mt7981-ethsys", "syscon"
+ 	- "mediatek,mt7986-ethsys", "syscon"
+ - #clock-cells: Must be 1
+ - #reset-cells: Must be 1
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+@@ -28,6 +28,7 @@ properties:
+               - mediatek,mt6797-infracfg
+               - mediatek,mt7622-infracfg
+               - mediatek,mt7629-infracfg
++              - mediatek,mt7981-infracfg
+               - mediatek,mt7986-infracfg
+               - mediatek,mt8135-infracfg
+               - mediatek,mt8167-infracfg
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+@@ -8,6 +8,8 @@ Required Properties:
+ - compatible: Should be:
+ 	- "mediatek,mt7622-sgmiisys", "syscon"
+ 	- "mediatek,mt7629-sgmiisys", "syscon"
++	- "mediatek,mt7981-sgmiisys_0", "syscon"
++	- "mediatek,mt7981-sgmiisys_1", "syscon"
+ 	- "mediatek,mt7986-sgmiisys_0", "syscon"
+ 	- "mediatek,mt7986-sgmiisys_1", "syscon"
+ - #clock-cells: Must be 1
+--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+@@ -20,6 +20,7 @@ properties:
+       - enum:
+           - mediatek,mt6797-apmixedsys
+           - mediatek,mt7622-apmixedsys
++          - mediatek,mt7981-apmixedsys
+           - mediatek,mt7986-apmixedsys
+           - mediatek,mt8135-apmixedsys
+           - mediatek,mt8173-apmixedsys
+--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+@@ -35,6 +35,7 @@ properties:
+               - mediatek,mt6779-topckgen
+               - mediatek,mt6795-topckgen
+               - mediatek,mt7629-topckgen
++              - mediatek,mt7981-topckgen
+               - mediatek,mt7986-topckgen
+               - mediatek,mt8167-topckgen
+               - mediatek,mt8183-topckgen

target/linux/mediatek/patches-6.6/242-v6.4-dt-bindings-arm-mediatek-sgmiisys-Convert-to-DT-sche.patch

@@ -0,0 +1,107 @@
+From d4f08a703565abf47baa5a77d05365cf4598d55c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Sun, 19 Mar 2023 12:56:52 +0000
+Subject: [PATCH 1/2] dt-bindings: arm: mediatek: sgmiisys: Convert to DT
+ schema
+
+Convert mediatek,sgmiiisys bindings to DT schema format.
+Add maintainer Matthias Brugger, no maintainers were listed in the
+original documentation.
+As this node is also referenced by the Ethernet controller and used
+as SGMII PCS add this fact to the description.
+Move the file to Documentation/devicetree/bindings/net/pcs/ which seems
+more appropriate given that the great majority of registers are related
+to SGMII PCS functionality and only one register represents clock bits.
+
+Reviewed-by: Rob Herring <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ .../arm/mediatek/mediatek,sgmiisys.txt        | 27 ----------
+ .../bindings/net/pcs/mediatek,sgmiisys.yaml   | 49 +++++++++++++++++++
+ 2 files changed, 49 insertions(+), 27 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+ create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
++++ /dev/null
+@@ -1,27 +0,0 @@
+-MediaTek SGMIISYS controller
+-============================
+-
+-The MediaTek SGMIISYS controller provides various clocks to the system.
+-
+-Required Properties:
+-
+-- compatible: Should be:
+-	- "mediatek,mt7622-sgmiisys", "syscon"
+-	- "mediatek,mt7629-sgmiisys", "syscon"
+-	- "mediatek,mt7981-sgmiisys_0", "syscon"
+-	- "mediatek,mt7981-sgmiisys_1", "syscon"
+-	- "mediatek,mt7986-sgmiisys_0", "syscon"
+-	- "mediatek,mt7986-sgmiisys_1", "syscon"
+-- #clock-cells: Must be 1
+-
+-The SGMIISYS controller uses the common clk binding from
+-Documentation/devicetree/bindings/clock/clock-bindings.txt
+-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+-
+-Example:
+-
+-sgmiisys: sgmiisys@1b128000 {
+-	compatible = "mediatek,mt7622-sgmiisys", "syscon";
+-	reg = <0 0x1b128000 0 0x1000>;
+-	#clock-cells = <1>;
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+@@ -0,0 +1,49 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek SGMIISYS Controller
++
++maintainers:
++  - Matthias Brugger <[email protected]>
++
++description:
++  The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
++  to the ethernet subsystem to which it is attached.
++
++properties:
++  compatible:
++    items:
++      - enum:
++          - mediatek,mt7622-sgmiisys
++          - mediatek,mt7629-sgmiisys
++          - mediatek,mt7986-sgmiisys_0
++          - mediatek,mt7986-sgmiisys_1
++      - const: syscon
++
++  reg:
++    maxItems: 1
++
++  '#clock-cells':
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - '#clock-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++      sgmiisys: syscon@1b128000 {
++        compatible = "mediatek,mt7622-sgmiisys", "syscon";
++        reg = <0 0x1b128000 0 0x1000>;
++        #clock-cells = <1>;
++      };
++    };

target/linux/mediatek/patches-6.6/243-v6.4-dt-bindings-net-pcs-mediatek-sgmiisys-add-MT7981-SoC.patch

@@ -0,0 +1,37 @@
+From 4f7eb19c4f44078100659f6ba073b0cc7191bc91 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Sun, 19 Mar 2023 12:57:04 +0000
+Subject: [PATCH 2/2] dt-bindings: net: pcs: mediatek,sgmiisys: add MT7981 SoC
+
+Add mediatek,pnswap boolean property needed on many boards using the
+MediaTek MT7981 SoC.
+
+Reviewed-by: Rob Herring <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+Signed-off-by: Jakub Kicinski <[email protected]>
+---
+ .../devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml      | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+@@ -19,6 +19,8 @@ properties:
+       - enum:
+           - mediatek,mt7622-sgmiisys
+           - mediatek,mt7629-sgmiisys
++          - mediatek,mt7981-sgmiisys_0
++          - mediatek,mt7981-sgmiisys_1
+           - mediatek,mt7986-sgmiisys_0
+           - mediatek,mt7986-sgmiisys_1
+       - const: syscon
+@@ -29,6 +31,10 @@ properties:
+   '#clock-cells':
+     const: 1
+ 
++  mediatek,pnswap:
++    description: Invert polarity of the SGMII data lanes
++    type: boolean
++
+ required:
+   - compatible
+   - reg

target/linux/mediatek/patches-6.6/244-v6.8-dt-bindings-arm-mediatek-move-ethsys-controller-conv.patch

@@ -0,0 +1,113 @@
+From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
+Date: Sun, 19 Nov 2023 22:24:16 +0100
+Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
+ to DT schema
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DT schema helps validating DTS files. Binding was moved to clock/ as
+this hardware is a clock provider. Example required a small fix for
+"reg" value (1 address cell + 1 size cell).
+
+Signed-off-by: Rafał Miłecki <[email protected]>
+Reviewed-by: Rob Herring <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ .../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
+ .../bindings/clock/mediatek,ethsys.yaml       | 54 +++++++++++++++++++
+ 2 files changed, 54 insertions(+), 29 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
++++ /dev/null
+@@ -1,29 +0,0 @@
+-Mediatek ethsys controller
+-============================
+-
+-The Mediatek ethsys controller provides various clocks to the system.
+-
+-Required Properties:
+-
+-- compatible: Should be:
+-	- "mediatek,mt2701-ethsys", "syscon"
+-	- "mediatek,mt7622-ethsys", "syscon"
+-	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
+-	- "mediatek,mt7629-ethsys", "syscon"
+-	- "mediatek,mt7981-ethsys", "syscon"
+-	- "mediatek,mt7986-ethsys", "syscon"
+-- #clock-cells: Must be 1
+-- #reset-cells: Must be 1
+-
+-The ethsys controller uses the common clk binding from
+-Documentation/devicetree/bindings/clock/clock-bindings.txt
+-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+-
+-Example:
+-
+-ethsys: clock-controller@1b000000 {
+-	compatible = "mediatek,mt2701-ethsys", "syscon";
+-	reg = <0 0x1b000000 0 0x1000>;
+-	#clock-cells = <1>;
+-	#reset-cells = <1>;
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+@@ -0,0 +1,54 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Mediatek ethsys controller
++
++description:
++  The available clocks are defined in dt-bindings/clock/mt*-clk.h.
++
++maintainers:
++  - James Liao <[email protected]>
++
++properties:
++  compatible:
++    oneOf:
++      - items:
++          - enum:
++              - mediatek,mt2701-ethsys
++              - mediatek,mt7622-ethsys
++              - mediatek,mt7629-ethsys
++              - mediatek,mt7981-ethsys
++              - mediatek,mt7986-ethsys
++          - const: syscon
++      - items:
++          - const: mediatek,mt7623-ethsys
++          - const: mediatek,mt2701-ethsys
++          - const: syscon
++
++  reg:
++    maxItems: 1
++
++  "#clock-cells":
++    const: 1
++
++  "#reset-cells":
++    const: 1
++
++required:
++  - reg
++  - "#clock-cells"
++  - "#reset-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    clock-controller@1b000000 {
++        compatible = "mediatek,mt2701-ethsys", "syscon";
++        reg = <0x1b000000 0x1000>;
++        #clock-cells = <1>;
++        #reset-cells = <1>;
++    };

target/linux/mediatek/patches-6.6/245-v6.8-dt-bindings-reset-mediatek-add-MT7988-ethwarp-reset-.patch

@@ -0,0 +1,35 @@
+From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Sun, 17 Dec 2023 21:49:45 +0000
+Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset
+ IDs
+
+Add reset ID for ethwarp subsystem allowing to reset the built-in
+Ethernet switch of the MediaTek MT7988 SoC.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Acked-by: Krzysztof Kozlowski <[email protected]>
+Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+ create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h
+
+--- /dev/null
++++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2023 Daniel Golle <[email protected]>
++ * Author: Daniel Golle <[email protected]>
++ */
++
++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
++#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
++
++/* ETHWARP resets */
++#define MT7988_ETHWARP_RST_SWITCH		0
++
++#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */

target/linux/mediatek/patches-6.6/246-v6.8-dt-bindings-clock-mediatek-add-MT7988-clock-IDs.patch

@@ -0,0 +1,302 @@
+From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sun, 17 Dec 2023 21:49:33 +0000
+Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs
+
+Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg,
+ethernet and xfipll subsystem clocks.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+Acked-by: Krzysztof Kozlowski <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ .../dt-bindings/clock/mediatek,mt7988-clk.h   | 280 ++++++++++++++++++
+ 1 file changed, 280 insertions(+)
+ create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h
+@@ -0,0 +1,280 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ * Author: Xiufeng Li <[email protected]>
++ */
++
++#ifndef _DT_BINDINGS_CLK_MT7988_H
++#define _DT_BINDINGS_CLK_MT7988_H
++
++/* APMIXEDSYS */
++
++#define CLK_APMIXED_NETSYSPLL			0
++#define CLK_APMIXED_MPLL			1
++#define CLK_APMIXED_MMPLL			2
++#define CLK_APMIXED_APLL2			3
++#define CLK_APMIXED_NET1PLL			4
++#define CLK_APMIXED_NET2PLL			5
++#define CLK_APMIXED_WEDMCUPLL			6
++#define CLK_APMIXED_SGMPLL			7
++#define CLK_APMIXED_ARM_B			8
++#define CLK_APMIXED_CCIPLL2_B			9
++#define CLK_APMIXED_USXGMIIPLL			10
++#define CLK_APMIXED_MSDCPLL			11
++
++/* TOPCKGEN */
++
++#define CLK_TOP_XTAL				0
++#define CLK_TOP_XTAL_D2				1
++#define CLK_TOP_RTC_32K				2
++#define CLK_TOP_RTC_32P7K			3
++#define CLK_TOP_MPLL_D2				4
++#define CLK_TOP_MPLL_D3_D2			5
++#define CLK_TOP_MPLL_D4				6
++#define CLK_TOP_MPLL_D8				7
++#define CLK_TOP_MPLL_D8_D2			8
++#define CLK_TOP_MMPLL_D2			9
++#define CLK_TOP_MMPLL_D3_D5			10
++#define CLK_TOP_MMPLL_D4			11
++#define CLK_TOP_MMPLL_D6_D2			12
++#define CLK_TOP_MMPLL_D8			13
++#define CLK_TOP_APLL2_D4			14
++#define CLK_TOP_NET1PLL_D4			15
++#define CLK_TOP_NET1PLL_D5			16
++#define CLK_TOP_NET1PLL_D5_D2			17
++#define CLK_TOP_NET1PLL_D5_D4			18
++#define CLK_TOP_NET1PLL_D8			19
++#define CLK_TOP_NET1PLL_D8_D2			20
++#define CLK_TOP_NET1PLL_D8_D4			21
++#define CLK_TOP_NET1PLL_D8_D8			22
++#define CLK_TOP_NET1PLL_D8_D16			23
++#define CLK_TOP_NET2PLL_D2			24
++#define CLK_TOP_NET2PLL_D4			25
++#define CLK_TOP_NET2PLL_D4_D4			26
++#define CLK_TOP_NET2PLL_D4_D8			27
++#define CLK_TOP_NET2PLL_D6			28
++#define CLK_TOP_NET2PLL_D8			29
++#define CLK_TOP_NETSYS_SEL			30
++#define CLK_TOP_NETSYS_500M_SEL			31
++#define CLK_TOP_NETSYS_2X_SEL			32
++#define CLK_TOP_NETSYS_GSW_SEL			33
++#define CLK_TOP_ETH_GMII_SEL			34
++#define CLK_TOP_NETSYS_MCU_SEL			35
++#define CLK_TOP_NETSYS_PAO_2X_SEL		36
++#define CLK_TOP_EIP197_SEL			37
++#define CLK_TOP_AXI_INFRA_SEL			38
++#define CLK_TOP_UART_SEL			39
++#define CLK_TOP_EMMC_250M_SEL			40
++#define CLK_TOP_EMMC_400M_SEL			41
++#define CLK_TOP_SPI_SEL				42
++#define CLK_TOP_SPIM_MST_SEL			43
++#define CLK_TOP_NFI1X_SEL			44
++#define CLK_TOP_SPINFI_SEL			45
++#define CLK_TOP_PWM_SEL				46
++#define CLK_TOP_I2C_SEL				47
++#define CLK_TOP_PCIE_MBIST_250M_SEL		48
++#define CLK_TOP_PEXTP_TL_SEL			49
++#define CLK_TOP_PEXTP_TL_P1_SEL			50
++#define CLK_TOP_PEXTP_TL_P2_SEL			51
++#define CLK_TOP_PEXTP_TL_P3_SEL			52
++#define CLK_TOP_USB_SYS_SEL			53
++#define CLK_TOP_USB_SYS_P1_SEL			54
++#define CLK_TOP_USB_XHCI_SEL			55
++#define CLK_TOP_USB_XHCI_P1_SEL			56
++#define CLK_TOP_USB_FRMCNT_SEL			57
++#define CLK_TOP_USB_FRMCNT_P1_SEL		58
++#define CLK_TOP_AUD_SEL				59
++#define CLK_TOP_A1SYS_SEL			60
++#define CLK_TOP_AUD_L_SEL			61
++#define CLK_TOP_A_TUNER_SEL			62
++#define CLK_TOP_SSPXTP_SEL			63
++#define CLK_TOP_USB_PHY_SEL			64
++#define CLK_TOP_USXGMII_SBUS_0_SEL		65
++#define CLK_TOP_USXGMII_SBUS_1_SEL		66
++#define CLK_TOP_SGM_0_SEL			67
++#define CLK_TOP_SGM_SBUS_0_SEL			68
++#define CLK_TOP_SGM_1_SEL			69
++#define CLK_TOP_SGM_SBUS_1_SEL			70
++#define CLK_TOP_XFI_PHY_0_XTAL_SEL		71
++#define CLK_TOP_XFI_PHY_1_XTAL_SEL		72
++#define CLK_TOP_SYSAXI_SEL			73
++#define CLK_TOP_SYSAPB_SEL			74
++#define CLK_TOP_ETH_REFCK_50M_SEL		75
++#define CLK_TOP_ETH_SYS_200M_SEL		76
++#define CLK_TOP_ETH_SYS_SEL			77
++#define CLK_TOP_ETH_XGMII_SEL			78
++#define CLK_TOP_BUS_TOPS_SEL			79
++#define CLK_TOP_NPU_TOPS_SEL			80
++#define CLK_TOP_DRAMC_SEL			81
++#define CLK_TOP_DRAMC_MD32_SEL			82
++#define CLK_TOP_INFRA_F26M_SEL			83
++#define CLK_TOP_PEXTP_P0_SEL			84
++#define CLK_TOP_PEXTP_P1_SEL			85
++#define CLK_TOP_PEXTP_P2_SEL			86
++#define CLK_TOP_PEXTP_P3_SEL			87
++#define CLK_TOP_DA_XTP_GLB_P0_SEL		88
++#define CLK_TOP_DA_XTP_GLB_P1_SEL		89
++#define CLK_TOP_DA_XTP_GLB_P2_SEL		90
++#define CLK_TOP_DA_XTP_GLB_P3_SEL		91
++#define CLK_TOP_CKM_SEL				92
++#define CLK_TOP_DA_SEL				93
++#define CLK_TOP_PEXTP_SEL			94
++#define CLK_TOP_TOPS_P2_26M_SEL			95
++#define CLK_TOP_MCUSYS_BACKUP_625M_SEL		96
++#define CLK_TOP_NETSYS_SYNC_250M_SEL		97
++#define CLK_TOP_MACSEC_SEL			98
++#define CLK_TOP_NETSYS_TOPS_400M_SEL		99
++#define CLK_TOP_NETSYS_PPEFB_250M_SEL		100
++#define CLK_TOP_NETSYS_WARP_SEL			101
++#define CLK_TOP_ETH_MII_SEL			102
++#define CLK_TOP_NPU_SEL				103
++#define CLK_TOP_AUD_I2S_M			104
++
++/* MCUSYS */
++
++#define CLK_MCU_BUS_DIV_SEL			0
++#define CLK_MCU_ARM_DIV_SEL			1
++
++/* INFRACFG_AO */
++
++#define CLK_INFRA_MUX_UART0_SEL			0
++#define CLK_INFRA_MUX_UART1_SEL			1
++#define CLK_INFRA_MUX_UART2_SEL			2
++#define CLK_INFRA_MUX_SPI0_SEL			3
++#define CLK_INFRA_MUX_SPI1_SEL			4
++#define CLK_INFRA_MUX_SPI2_SEL			5
++#define CLK_INFRA_PWM_SEL			6
++#define CLK_INFRA_PWM_CK1_SEL			7
++#define CLK_INFRA_PWM_CK2_SEL			8
++#define CLK_INFRA_PWM_CK3_SEL			9
++#define CLK_INFRA_PWM_CK4_SEL			10
++#define CLK_INFRA_PWM_CK5_SEL			11
++#define CLK_INFRA_PWM_CK6_SEL			12
++#define CLK_INFRA_PWM_CK7_SEL			13
++#define CLK_INFRA_PWM_CK8_SEL			14
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL	15
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL	16
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL	17
++#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL	18
++
++/* INFRACFG */
++
++#define CLK_INFRA_PCIE_PERI_26M_CK_P0		19
++#define CLK_INFRA_PCIE_PERI_26M_CK_P1		20
++#define CLK_INFRA_PCIE_PERI_26M_CK_P2		21
++#define CLK_INFRA_PCIE_PERI_26M_CK_P3		22
++#define CLK_INFRA_66M_GPT_BCK			23
++#define CLK_INFRA_66M_PWM_HCK			24
++#define CLK_INFRA_66M_PWM_BCK			25
++#define CLK_INFRA_66M_PWM_CK1			26
++#define CLK_INFRA_66M_PWM_CK2			27
++#define CLK_INFRA_66M_PWM_CK3			28
++#define CLK_INFRA_66M_PWM_CK4			29
++#define CLK_INFRA_66M_PWM_CK5			30
++#define CLK_INFRA_66M_PWM_CK6			31
++#define CLK_INFRA_66M_PWM_CK7			32
++#define CLK_INFRA_66M_PWM_CK8			33
++#define CLK_INFRA_133M_CQDMA_BCK		34
++#define CLK_INFRA_66M_AUD_SLV_BCK		35
++#define CLK_INFRA_AUD_26M			36
++#define CLK_INFRA_AUD_L				37
++#define CLK_INFRA_AUD_AUD			38
++#define CLK_INFRA_AUD_EG2			39
++#define CLK_INFRA_DRAMC_F26M			40
++#define CLK_INFRA_133M_DBG_ACKM			41
++#define CLK_INFRA_66M_AP_DMA_BCK		42
++#define CLK_INFRA_66M_SEJ_BCK			43
++#define CLK_INFRA_PRE_CK_SEJ_F13M		44
++#define CLK_INFRA_26M_THERM_SYSTEM		45
++#define CLK_INFRA_I2C_BCK			46
++#define CLK_INFRA_52M_UART0_CK			47
++#define CLK_INFRA_52M_UART1_CK			48
++#define CLK_INFRA_52M_UART2_CK			49
++#define CLK_INFRA_NFI				50
++#define CLK_INFRA_SPINFI			51
++#define CLK_INFRA_66M_NFI_HCK			52
++#define CLK_INFRA_104M_SPI0			53
++#define CLK_INFRA_104M_SPI1			54
++#define CLK_INFRA_104M_SPI2_BCK			55
++#define CLK_INFRA_66M_SPI0_HCK			56
++#define CLK_INFRA_66M_SPI1_HCK			57
++#define CLK_INFRA_66M_SPI2_HCK			58
++#define CLK_INFRA_66M_FLASHIF_AXI		59
++#define CLK_INFRA_RTC				60
++#define CLK_INFRA_26M_ADC_BCK			61
++#define CLK_INFRA_RC_ADC			62
++#define CLK_INFRA_MSDC400			63
++#define CLK_INFRA_MSDC2_HCK			64
++#define CLK_INFRA_133M_MSDC_0_HCK		65
++#define CLK_INFRA_66M_MSDC_0_HCK		66
++#define CLK_INFRA_133M_CPUM_BCK			67
++#define CLK_INFRA_BIST2FPC			68
++#define CLK_INFRA_I2C_X16W_MCK_CK_P1		69
++#define CLK_INFRA_I2C_X16W_PCK_CK_P1		70
++#define CLK_INFRA_133M_USB_HCK			71
++#define CLK_INFRA_133M_USB_HCK_CK_P1		72
++#define CLK_INFRA_66M_USB_HCK			73
++#define CLK_INFRA_66M_USB_HCK_CK_P1		74
++#define CLK_INFRA_USB_SYS			75
++#define CLK_INFRA_USB_SYS_CK_P1			76
++#define CLK_INFRA_USB_REF			77
++#define CLK_INFRA_USB_CK_P1			78
++#define CLK_INFRA_USB_FRMCNT			79
++#define CLK_INFRA_USB_FRMCNT_CK_P1		80
++#define CLK_INFRA_USB_PIPE			81
++#define CLK_INFRA_USB_PIPE_CK_P1		82
++#define CLK_INFRA_USB_UTMI			83
++#define CLK_INFRA_USB_UTMI_CK_P1		84
++#define CLK_INFRA_USB_XHCI			85
++#define CLK_INFRA_USB_XHCI_CK_P1		86
++#define CLK_INFRA_PCIE_GFMUX_TL_P0		87
++#define CLK_INFRA_PCIE_GFMUX_TL_P1		88
++#define CLK_INFRA_PCIE_GFMUX_TL_P2		89
++#define CLK_INFRA_PCIE_GFMUX_TL_P3		90
++#define CLK_INFRA_PCIE_PIPE_P0			91
++#define CLK_INFRA_PCIE_PIPE_P1			92
++#define CLK_INFRA_PCIE_PIPE_P2			93
++#define CLK_INFRA_PCIE_PIPE_P3			94
++#define CLK_INFRA_133M_PCIE_CK_P0		95
++#define CLK_INFRA_133M_PCIE_CK_P1		96
++#define CLK_INFRA_133M_PCIE_CK_P2		97
++#define CLK_INFRA_133M_PCIE_CK_P3		98
++
++/* ETHDMA */
++
++#define CLK_ETHDMA_XGP1_EN			0
++#define CLK_ETHDMA_XGP2_EN			1
++#define CLK_ETHDMA_XGP3_EN			2
++#define CLK_ETHDMA_FE_EN			3
++#define CLK_ETHDMA_GP2_EN			4
++#define CLK_ETHDMA_GP1_EN			5
++#define CLK_ETHDMA_GP3_EN			6
++#define CLK_ETHDMA_ESW_EN			7
++#define CLK_ETHDMA_CRYPT0_EN			8
++#define CLK_ETHDMA_NR_CLK			9
++
++/* SGMIISYS_0 */
++
++#define CLK_SGM0_TX_EN				0
++#define CLK_SGM0_RX_EN				1
++#define CLK_SGMII0_NR_CLK			2
++
++/* SGMIISYS_1 */
++
++#define CLK_SGM1_TX_EN				0
++#define CLK_SGM1_RX_EN				1
++#define CLK_SGMII1_NR_CLK			2
++
++/* ETHWARP */
++
++#define CLK_ETHWARP_WOCPU2_EN			0
++#define CLK_ETHWARP_WOCPU1_EN			1
++#define CLK_ETHWARP_WOCPU0_EN			2
++#define CLK_ETHWARP_NR_CLK			3
++
++/* XFIPLL */
++#define CLK_XFIPLL_PLL				0
++#define CLK_XFIPLL_PLL_EN			1
++
++#endif /* _DT_BINDINGS_CLK_MT7988_H */

target/linux/mediatek/patches-6.6/247-v6.8-dt-bindings-clock-mediatek-add-clock-controllers-of-.patch

@@ -0,0 +1,260 @@
+From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Sun, 17 Dec 2023 21:49:55 +0000
+Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of
+ MT7988
+
+Add various clock controllers found in the MT7988 SoC to existing
+bindings (if applicable) and add files for the new ethwarp, mcusys
+and xfi-pll clock controllers not previously present in any SoC.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
+Reviewed-by: Krzysztof Kozlowski <[email protected]>
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ .../arm/mediatek/mediatek,infracfg.yaml       |  1 +
+ .../bindings/clock/mediatek,apmixedsys.yaml   |  1 +
+ .../bindings/clock/mediatek,ethsys.yaml       |  1 +
+ .../clock/mediatek,mt7988-ethwarp.yaml        | 52 +++++++++++++++
+ .../clock/mediatek,mt7988-xfi-pll.yaml        | 48 ++++++++++++++
+ .../bindings/clock/mediatek,topckgen.yaml     |  2 +
+ .../bindings/net/pcs/mediatek,sgmiisys.yaml   | 65 ++++++++++++++++---
+ 7 files changed, 161 insertions(+), 9 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
+ create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
+
+--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+@@ -30,6 +30,7 @@ properties:
+               - mediatek,mt7629-infracfg
+               - mediatek,mt7981-infracfg
+               - mediatek,mt7986-infracfg
++              - mediatek,mt7988-infracfg
+               - mediatek,mt8135-infracfg
+               - mediatek,mt8167-infracfg
+               - mediatek,mt8173-infracfg
+--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+@@ -22,6 +22,7 @@ properties:
+           - mediatek,mt7622-apmixedsys
+           - mediatek,mt7981-apmixedsys
+           - mediatek,mt7986-apmixedsys
++          - mediatek,mt7988-apmixedsys
+           - mediatek,mt8135-apmixedsys
+           - mediatek,mt8173-apmixedsys
+           - mediatek,mt8516-apmixedsys
+--- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
+@@ -22,6 +22,7 @@ properties:
+               - mediatek,mt7629-ethsys
+               - mediatek,mt7981-ethsys
+               - mediatek,mt7986-ethsys
++              - mediatek,mt7988-ethsys
+           - const: syscon
+       - items:
+           - const: mediatek,mt7623-ethsys
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
+@@ -0,0 +1,52 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek MT7988 ethwarp Controller
++
++maintainers:
++  - Daniel Golle <[email protected]>
++
++description:
++  The Mediatek MT7988 ethwarp controller provides clocks and resets for the
++  Ethernet related subsystems found the MT7988 SoC.
++  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
++
++properties:
++  compatible:
++    items:
++      - const: mediatek,mt7988-ethwarp
++
++  reg:
++    maxItems: 1
++
++  '#clock-cells':
++    const: 1
++
++  '#reset-cells':
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - '#clock-cells'
++  - '#reset-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/reset/ti-syscon.h>
++    soc {
++        #address-cells = <2>;
++        #size-cells = <2>;
++
++        clock-controller@15031000 {
++            compatible = "mediatek,mt7988-ethwarp";
++            reg = <0 0x15031000 0 0x1000>;
++            #clock-cells = <1>;
++            #reset-cells = <1>;
++        };
++    };
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
+@@ -0,0 +1,48 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek MT7988 XFI PLL Clock Controller
++
++maintainers:
++  - Daniel Golle <[email protected]>
++
++description:
++  The MediaTek XFI PLL controller provides the 156.25MHz clock for the
++  Ethernet SerDes PHY from the 40MHz top_xtal clock.
++
++properties:
++  compatible:
++    const: mediatek,mt7988-xfi-pll
++
++  reg:
++    maxItems: 1
++
++  resets:
++    maxItems: 1
++
++  '#clock-cells':
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - resets
++  - '#clock-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    soc {
++        #address-cells = <2>;
++        #size-cells = <2>;
++        clock-controller@11f40000 {
++            compatible = "mediatek,mt7988-xfi-pll";
++            reg = <0 0x11f40000 0 0x1000>;
++            resets = <&watchdog 16>;
++            #clock-cells = <1>;
++        };
++    };
+--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
++++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+@@ -37,6 +37,8 @@ properties:
+               - mediatek,mt7629-topckgen
+               - mediatek,mt7981-topckgen
+               - mediatek,mt7986-topckgen
++              - mediatek,mt7988-mcusys
++              - mediatek,mt7988-topckgen
+               - mediatek,mt8167-topckgen
+               - mediatek,mt8183-topckgen
+           - const: syscon
+--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+@@ -15,15 +15,22 @@ description:
+ 
+ properties:
+   compatible:
+-    items:
+-      - enum:
+-          - mediatek,mt7622-sgmiisys
+-          - mediatek,mt7629-sgmiisys
+-          - mediatek,mt7981-sgmiisys_0
+-          - mediatek,mt7981-sgmiisys_1
+-          - mediatek,mt7986-sgmiisys_0
+-          - mediatek,mt7986-sgmiisys_1
+-      - const: syscon
++    oneOf:
++      - items:
++          - enum:
++              - mediatek,mt7622-sgmiisys
++              - mediatek,mt7629-sgmiisys
++              - mediatek,mt7981-sgmiisys_0
++              - mediatek,mt7981-sgmiisys_1
++              - mediatek,mt7986-sgmiisys_0
++              - mediatek,mt7986-sgmiisys_1
++          - const: syscon
++      - items:
++          - enum:
++              - mediatek,mt7988-sgmiisys0
++              - mediatek,mt7988-sgmiisys1
++          - const: simple-mfd
++          - const: syscon
+ 
+   reg:
+     maxItems: 1
+@@ -35,11 +42,51 @@ properties:
+     description: Invert polarity of the SGMII data lanes
+     type: boolean
+ 
++  pcs:
++    type: object
++    description: MediaTek LynxI HSGMII PCS
++    properties:
++      compatible:
++        const: mediatek,mt7988-sgmii
++
++      clocks:
++        maxItems: 3
++
++      clock-names:
++        items:
++          - const: sgmii_sel
++          - const: sgmii_tx
++          - const: sgmii_rx
++
++    required:
++      - compatible
++      - clocks
++      - clock-names
++
++    additionalProperties: false
++
+ required:
+   - compatible
+   - reg
+   - '#clock-cells'
+ 
++allOf:
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - mediatek,mt7988-sgmiisys0
++              - mediatek,mt7988-sgmiisys1
++
++    then:
++      required:
++        - pcs
++
++    else:
++      properties:
++        pcs: false
++
+ additionalProperties: false
+ 
+ examples:

target/linux/mediatek/patches-6.6/248-v6.8-clk-mediatek-add-pcw_chg_bit-control-for-PLLs-of-MT7.patch

@@ -0,0 +1,50 @@
+From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sun, 17 Dec 2023 21:50:07 +0000
+Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
+
+Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
+of the previously hardcoded PCW_CHG_MASK macro if set.
+This will needed for clocks on the MT7988 SoC.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/clk-pll.c | 5 +++--
+ drivers/clk/mediatek/clk-pll.h | 1 +
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-pll.c
++++ b/drivers/clk/mediatek/clk-pll.c
+@@ -23,7 +23,7 @@
+ #define CON0_BASE_EN		BIT(0)
+ #define CON0_PWR_ON		BIT(0)
+ #define CON0_ISO_EN		BIT(1)
+-#define PCW_CHG_MASK		BIT(31)
++#define PCW_CHG_BIT		31
+ 
+ #define AUDPLL_TUNER_EN		BIT(31)
+ 
+@@ -141,7 +141,8 @@ static void mtk_pll_set_rate_regs(struct
+ 			pll->data->pcw_shift);
+ 	val |= pcw << pll->data->pcw_shift;
+ 	writel(val, pll->pcw_addr);
+-	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
++	chg = readl(pll->pcw_chg_addr) |
++	      BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
+ 	writel(chg, pll->pcw_chg_addr);
+ 	if (pll->tuner_addr)
+ 		writel(val + 1, pll->tuner_addr);
+--- a/drivers/clk/mediatek/clk-pll.h
++++ b/drivers/clk/mediatek/clk-pll.h
+@@ -46,6 +46,7 @@ struct mtk_pll_data {
+ 	const char *parent_name;
+ 	u32 en_reg;
+ 	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
++	u8 pcw_chg_bit;
+ };
+ 
+ int mtk_clk_register_plls(struct device_node *node,

target/linux/mediatek/patches-6.6/249-v6.8-clk-mediatek-add-drivers-for-MT7988-SoC.patch

@@ -0,0 +1,1026 @@
+From 4b4719437d85f0173d344f2c76fa1a5b7f7d184b Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Sun, 17 Dec 2023 21:50:15 +0000
+Subject: [PATCH 4/4] clk: mediatek: add drivers for MT7988 SoC
+
+Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
+typical MediaTek designs.
+
+Also add driver for XFIPLL clock generating the 156.25MHz clock for
+the XFI SerDes. It needs an undocumented software workaround and has
+an unknown internal design.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
+[[email protected]: Add module license to infracfg file]
+Signed-off-by: Stephen Boyd <[email protected]>
+---
+ drivers/clk/mediatek/Kconfig               |   9 +
+ drivers/clk/mediatek/Makefile              |   5 +
+ drivers/clk/mediatek/clk-mt7988-apmixed.c  | 114 ++++++++
+ drivers/clk/mediatek/clk-mt7988-eth.c      | 150 ++++++++++
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 275 +++++++++++++++++
+ drivers/clk/mediatek/clk-mt7988-topckgen.c | 325 +++++++++++++++++++++
+ drivers/clk/mediatek/clk-mt7988-xfipll.c   |  82 ++++++
+ 7 files changed, 960 insertions(+)
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-apmixed.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-eth.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-infracfg.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-topckgen.c
+ create mode 100644 drivers/clk/mediatek/clk-mt7988-xfipll.c
+
+--- a/drivers/clk/mediatek/Kconfig
++++ b/drivers/clk/mediatek/Kconfig
+@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS
+ 	  This driver adds support for clocks for Ethernet and SGMII
+ 	  required on MediaTek MT7986 SoC.
+ 
++config COMMON_CLK_MT7988
++	tristate "Clock driver for MediaTek MT7988"
++	depends on ARCH_MEDIATEK || COMPILE_TEST
++	select COMMON_CLK_MEDIATEK
++	default ARCH_MEDIATEK
++	help
++	  This driver supports MediaTek MT7988 basic clocks and clocks
++	  required for various periperals found on this SoC.
++
+ config COMMON_CLK_MT8135
+ 	bool "Clock driver for MediaTek MT8135"
+ 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
+--- a/drivers/clk/mediatek/Makefile
++++ b/drivers/clk/mediatek/Makefile
+@@ -60,6 +60,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
+ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
+ obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o
+ obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+ obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
+ obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c
+@@ -0,0 +1,114 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ * Author: Xiufeng Li <[email protected]>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include "clk-pll.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++#define MT7988_PLL_FMAX (2500UL * MHZ)
++#define MT7988_PCW_CHG_BIT 2
++
++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg,	\
++	    _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift,		\
++	    _pcw_chg_reg)									\
++	{											\
++		.id = _id,									\
++		.name = _name,									\
++		.reg = _reg,									\
++		.pwr_reg = _pwr_reg,								\
++		.en_mask = _en_mask,								\
++		.flags = _flags,								\
++		.rst_bar_mask = BIT(_rst_bar_mask),						\
++		.fmax = MT7988_PLL_FMAX,							\
++		.pcwbits = _pcwbits,								\
++		.pd_reg = _pd_reg,								\
++		.pd_shift = _pd_shift,								\
++		.tuner_reg = _tuner_reg,							\
++		.tuner_en_reg = _tuner_en_reg,							\
++		.tuner_en_bit = _tuner_en_bit,							\
++		.pcw_reg = _pcw_reg,								\
++		.pcw_shift = _pcw_shift,							\
++		.pcw_chg_reg = _pcw_chg_reg,							\
++		.pcw_chg_bit = MT7988_PCW_CHG_BIT,						\
++		.parent_name = "clkxtal",							\
++	}
++
++static const struct mtk_pll_data plls[] = {
++	PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
++	    0, 0, 0x0108, 0, 0x0104),
++	PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
++	    0, 0, 0, 0x0118, 0, 0x0114),
++	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
++	    0, 0, 0, 0x0128, 0, 0x0124),
++	PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
++	    0x0700, 1, 0x0138, 0, 0x0134),
++	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
++	    0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
++	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,
++	    32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),
++	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
++	    0, 0, 0x0168, 0, 0x0164),
++	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
++	    0x0178, 0, 0x0174),
++	PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,
++	    0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),
++	PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
++	    0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
++	PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
++	    0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
++	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,
++	    0, 0x0318, 0, 0x0314),
++};
++
++static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
++	{ .compatible = "mediatek,mt7988-apmixedsys" },
++	{ /* sentinel */ }
++};
++
++static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
++{
++	struct clk_hw_onecell_data *clk_data;
++	struct device_node *node = pdev->dev.of_node;
++	int r;
++
++	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
++	if (!clk_data)
++		return -ENOMEM;
++
++	r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
++	if (r)
++		goto free_apmixed_data;
++
++	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
++	if (r)
++		goto unregister_plls;
++
++	return r;
++
++unregister_plls:
++	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
++free_apmixed_data:
++	mtk_free_clk_data(clk_data);
++	return r;
++}
++
++static struct platform_driver clk_mt7988_apmixed_drv = {
++	.probe = clk_mt7988_apmixed_probe,
++	.driver = {
++		.name = "clk-mt7988-apmixed",
++		.of_match_table = of_match_clk_mt7988_apmixed,
++	},
++};
++builtin_platform_driver(clk_mt7988_apmixed_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-eth.c
+@@ -0,0 +1,150 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ * Author: Xiufeng Li <[email protected]>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "reset.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++#include <dt-bindings/reset/mediatek,mt7988-resets.h>
++
++static const struct mtk_gate_regs ethdma_cg_regs = {
++	.set_ofs = 0x30,
++	.clr_ofs = 0x30,
++	.sta_ofs = 0x30,
++};
++
++#define GATE_ETHDMA(_id, _name, _parent, _shift)		\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &ethdma_cg_regs,			\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_gate ethdma_clks[] = {
++	GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
++	GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
++	GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
++	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
++	GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
++	GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
++	GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
++	GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
++	GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29),
++};
++
++static const struct mtk_clk_desc ethdma_desc = {
++	.clks = ethdma_clks,
++	.num_clks = ARRAY_SIZE(ethdma_clks),
++};
++
++static const struct mtk_gate_regs sgmii_cg_regs = {
++	.set_ofs = 0xe4,
++	.clr_ofs = 0xe4,
++	.sta_ofs = 0xe4,
++};
++
++#define GATE_SGMII(_id, _name, _parent, _shift)			\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &sgmii_cg_regs,				\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_gate sgmii0_clks[] = {
++	GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
++	GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
++};
++
++static const struct mtk_clk_desc sgmii0_desc = {
++	.clks = sgmii0_clks,
++	.num_clks = ARRAY_SIZE(sgmii0_clks),
++};
++
++static const struct mtk_gate sgmii1_clks[] = {
++	GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
++	GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
++};
++
++static const struct mtk_clk_desc sgmii1_desc = {
++	.clks = sgmii1_clks,
++	.num_clks = ARRAY_SIZE(sgmii1_clks),
++};
++
++static const struct mtk_gate_regs ethwarp_cg_regs = {
++	.set_ofs = 0x14,
++	.clr_ofs = 0x14,
++	.sta_ofs = 0x14,
++};
++
++#define GATE_ETHWARP(_id, _name, _parent, _shift)		\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &ethwarp_cg_regs,			\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_gate ethwarp_clks[] = {
++	GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13),
++	GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14),
++	GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15),
++};
++
++static u16 ethwarp_rst_ofs[] = { 0x8 };
++
++static u16 ethwarp_idx_map[] = {
++	[MT7988_ETHWARP_RST_SWITCH] = 9,
++};
++
++static const struct mtk_clk_rst_desc ethwarp_rst_desc = {
++	.version = MTK_RST_SIMPLE,
++	.rst_bank_ofs = ethwarp_rst_ofs,
++	.rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs),
++	.rst_idx_map = ethwarp_idx_map,
++	.rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map),
++};
++
++static const struct mtk_clk_desc ethwarp_desc = {
++	.clks = ethwarp_clks,
++	.num_clks = ARRAY_SIZE(ethwarp_clks),
++	.rst_desc = &ethwarp_rst_desc,
++};
++
++static const struct of_device_id of_match_clk_mt7988_eth[] = {
++	{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
++	{ .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc },
++	{ .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc },
++	{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
++
++static struct platform_driver clk_mt7988_eth_drv = {
++	.driver = {
++		.name = "clk-mt7988-eth",
++		.of_match_table = of_match_clk_mt7988_eth,
++	},
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_eth_drv);
++
++MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -0,0 +1,275 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ * Author: Xiufeng Li <[email protected]>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++static DEFINE_SPINLOCK(mt7988_clk_lock);
++
++static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel",
++								   "uart_sel" };
++
++static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel",
++								   "uart_sel" };
++
++static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel",
++								   "uart_sel" };
++
++static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" };
++
++static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" };
++
++static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k",
++								 "csw_infra_f26m_sel", "sysaxi_sel",
++								 "pwm_sel" };
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel"
++};
++
++static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
++	"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel"
++};
++
++static const struct mtk_mux infra_muxes[] = {
++	/* MODULE_CLK_SEL_0 */
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
++			     infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
++			     infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
++			     infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
++			     0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
++			     0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
++			     0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
++			     0x0010, 0x0014, 14, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
++			     0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
++	/* MODULE_CLK_SEL_1 */
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
++			     infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
++			     -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
++			     infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
++			     -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
++			     infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
++			     -1, -1),
++	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
++			     infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
++			     -1, -1),
++};
++
++static const struct mtk_gate_regs infra0_cg_regs = {
++	.set_ofs = 0x10,
++	.clr_ofs = 0x14,
++	.sta_ofs = 0x18,
++};
++
++static const struct mtk_gate_regs infra1_cg_regs = {
++	.set_ofs = 0x40,
++	.clr_ofs = 0x44,
++	.sta_ofs = 0x48,
++};
++
++static const struct mtk_gate_regs infra2_cg_regs = {
++	.set_ofs = 0x50,
++	.clr_ofs = 0x54,
++	.sta_ofs = 0x58,
++};
++
++static const struct mtk_gate_regs infra3_cg_regs = {
++	.set_ofs = 0x60,
++	.clr_ofs = 0x64,
++	.sta_ofs = 0x68,
++};
++
++#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags)                                 \
++	GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
++		       _flags)
++
++#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
++
++#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
++
++static const struct mtk_gate infra_clks[] = {
++	/* INFRA0 */
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0",
++		    "csw_infra_f26m_sel", 7),
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
++		    "csw_infra_f26m_sel", 8),
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
++		    "csw_infra_f26m_sel", 9),
++	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
++		    "csw_infra_f26m_sel", 10),
++	/* INFRA1 */
++	GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9),
++	GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10),
++	GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12),
++	GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13),
++	GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14),
++	GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
++	GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
++	GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
++	GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19,
++			  CLK_IS_CRITICAL),
++	/* JTAG */
++	GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21),
++	GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29),
++	GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30),
++	/* INFRA2 */
++	GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel",
++		    0),
++	GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
++	GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3),
++	GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4),
++	GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5),
++	GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
++	GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
++	GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
++	GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
++	GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
++	GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
++	GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
++	GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL),
++	GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20),
++	GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21),
++	GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22),
++	GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23),
++	GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24),
++	GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25),
++	GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26),
++	GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
++	GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
++	GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
++	/* INFRA3 */
++	GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0),
++	GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1),
++	GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2),
++	GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3),
++	GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
++	GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5),
++	GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
++	GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
++	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8,
++			  CLK_IS_CRITICAL),
++	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",
++			  9, CLK_IS_CRITICAL),
++	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
++	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),
++	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
++	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13),
++	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
++	GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
++		    "infra_pcie_gfmux_tl_o_p0_sel", 20),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
++		    "infra_pcie_gfmux_tl_o_p1_sel", 21),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
++		    "infra_pcie_gfmux_tl_o_p2_sel", 22),
++	GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
++		    "infra_pcie_gfmux_tl_o_p3_sel", 23),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26),
++	GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30),
++	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
++};
++
++static const struct mtk_clk_desc infra_desc = {
++	.clks = infra_clks,
++	.num_clks = ARRAY_SIZE(infra_clks),
++	.mux_clks = infra_muxes,
++	.num_mux_clks = ARRAY_SIZE(infra_muxes),
++	.clk_lock = &mt7988_clk_lock,
++};
++
++static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
++	{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
++
++static struct platform_driver clk_mt7988_infracfg_drv = {
++	.driver = {
++		.name = "clk-mt7988-infracfg",
++		.of_match_table = of_match_clk_mt7988_infracfg,
++	},
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_infracfg_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c
+@@ -0,0 +1,325 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Sam Shih <[email protected]>
++ * Author: Xiufeng Li <[email protected]>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include "clk-mux.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++static DEFINE_SPINLOCK(mt7988_clk_lock);
++
++static const struct mtk_fixed_clk top_fixed_clks[] = {
++	FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
++};
++
++static const struct mtk_fixed_factor top_divs[] = {
++	FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
++	FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
++	FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
++	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
++	FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
++	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
++	FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
++	FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
++	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
++	FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
++	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
++	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
++	FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
++	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
++	FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
++	FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
++	FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
++	FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
++	FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
++	FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
++	FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
++	FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
++	FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
++	FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
++	FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
++	FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
++	FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
++	FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
++	FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
++};
++
++static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" };
++static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" };
++static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" };
++static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" };
++static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
++static const char *const netsys_mcu_parents[] = { "top_xtal",	"net2pll",    "mmpll",
++						  "net1pll_d4", "net1pll_d5", "mpll" };
++static const char *const eip197_parents[] = { "top_xtal", "netsyspll",	"net2pll",
++					      "mmpll",	  "net1pll_d4", "net1pll_d5" };
++static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
++static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" };
++static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" };
++static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",	 "mmpll_d2",
++						 "mpll_d2",  "mmpll_d4", "net1pll_d8_d2" };
++static const char *const spi_parents[] = { "top_xtal",	    "mpll_d2",	    "mmpll_d4",
++					   "net1pll_d8_d2", "net2pll_d6",   "net1pll_d5_d4",
++					   "mpll_d4",	    "net1pll_d8_d4" };
++static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6",
++					     "mpll_d4",	 "mmpll_d8", "net1pll_d8_d4", "mpll_d8" };
++static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4",
++					      "mpll_d4",     "mmpll_d8", "net1pll_d8_d4",
++					      "mmpll_d6_d2", "mpll_d8" };
++static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4",
++					   "mpll_d4",  "mpll_d8_d2",	"top_rtc_32k" };
++static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4",
++					   "net1pll_d8_d4" };
++static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" };
++static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8",
++						   "mpll_d8_d2", "top_rtc_32k" };
++static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
++static const char *const aud_parents[] = { "top_xtal", "apll2" };
++static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
++static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" };
++static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
++static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" };
++static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
++static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
++static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" };
++static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
++static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" };
++static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" };
++static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
++static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" };
++static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" };
++static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" };
++static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" };
++static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" };
++static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" };
++
++static const struct mtk_mux top_muxes[] = {
++	/* CLK_CFG_0 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
++			     0, 2, 7, 0x1c0, 0),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
++			     0x004, 0x008, 8, 2, 15, 0x1C0, 1),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
++			     0x004, 0x008, 16, 2, 23, 0x1C0, 2),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
++			     0x004, 0x008, 24, 2, 31, 0x1C0, 3),
++	/* CLK_CFG_1 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
++			     0x018, 0, 1, 7, 0x1C0, 4),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010,
++			     0x014, 0x018, 8, 3, 15, 0x1C0, 5),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents,
++			     0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,
++			     24, 3, 31, 0x1c0, 7),
++	/* CLK_CFG_2 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020,
++				   0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,
++			     15, 0x1c0, 9),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
++			     0x024, 0x028, 16, 2, 23, 0x1C0, 10),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020,
++			     0x024, 0x028, 24, 3, 31, 0x1C0, 11),
++	/* CLK_CFG_3 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7,
++			     0x1c0, 12),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038,
++			     8, 3, 15, 0x1c0, 13),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,
++			     3, 23, 0x1c0, 14),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038,
++			     24, 3, 31, 0x1c0, 15),
++	/* CLK_CFG_4 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
++			     0x1c0, 16),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15,
++			     0x1c0, 17),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
++			     pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,
++			     0x044, 0x048, 24, 3, 31, 0x1C0, 19),
++	/* CLK_CFG_5 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,
++			     0x054, 0x058, 0, 3, 7, 0x1C0, 20),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,
++			     0x054, 0x058, 8, 3, 15, 0x1C0, 21),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,
++			     0x054, 0x058, 16, 3, 23, 0x1C0, 22),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054,
++			     0x058, 24, 1, 31, 0x1C0, 23),
++	/* CLK_CFG_6 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060,
++			     0x064, 0x068, 0, 1, 7, 0x1C0, 24),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064,
++			     0x068, 8, 1, 15, 0x1C0, 25),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060,
++			     0x064, 0x068, 16, 1, 23, 0x1C0, 26),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060,
++			     0x064, 0x068, 24, 1, 31, 0x1C0, 27),
++	/* CLK_CFG_7 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents,
++			     0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15,
++			     0x1c0, 29),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,
++			     1, 23, 0x1c0, 30),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,
++			     2, 31, 0x1c4, 0),
++	/* CLK_CFG_8 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088,
++			     0, 1, 7, 0x1c4, 1),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088,
++			     8, 1, 15, 0x1c4, 2),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084,
++			     0x088, 16, 1, 23, 0x1c4, 3),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
++			     usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
++	/* CLK_CFG_9 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
++			     usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8,
++			     1, 15, 0x1c4, 6),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
++				   0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24,
++			     1, 31, 0x1c4, 8),
++	/* CLK_CFG_10 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
++				   0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
++			     0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
++			     0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11),
++	/* CLK_CFG_11 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,
++				   0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4,
++				   0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents,
++			     0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents,
++			     0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,
++			     0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16),
++	/* CLK_CFG_12 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0,
++			     0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4,
++			     0x0c8, 8, 2, 15, 0x1C4, 18),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4,
++			     0x0c8, 16, 1, 23, 0x1C4, 19),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4,
++				   0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),
++	/* CLK_CFG_13 */
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
++				   0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
++				   0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4,
++			     0x0d8, 16, 1, 23, 0x1C4, 23),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4,
++			     0x0d8, 24, 1, 31, 0x1C4, 24),
++	/* CLK_CFG_14 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4,
++			     0x0e8, 0, 1, 7, 0x1C4, 25),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4,
++			     0x0e8, 8, 1, 15, 0x1C4, 26),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents,
++			     0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents,
++			     0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28),
++	/* CLK_CFG_15 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents,
++			     0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents,
++			     0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1,
++			     23, 0x1c8, 0),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1,
++			     31, 0x1C8, 1),
++	/* CLK_CFG_16 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108,
++			     0, 1, 7, 0x1c8, 2),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100,
++			     0x104, 0x108, 8, 1, 15, 0x1C8, 3),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
++			     mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
++			     pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
++	/* CLK_CFG_17 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118,
++			     0, 2, 7, 0x1c8, 6),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
++			     netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
++			     pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110,
++			     0x114, 0x118, 24, 2, 31, 0x1C8, 9),
++	/* CLK_CFG_18 */
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124,
++			     0x128, 0, 1, 7, 0x1c8, 10),
++	MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128,
++			     8, 2, 15, 0x1c8, 11),
++};
++
++static const struct mtk_composite top_aud_divs[] = {
++	DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8),
++};
++
++static const struct mtk_clk_desc topck_desc = {
++	.fixed_clks = top_fixed_clks,
++	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
++	.factor_clks = top_divs,
++	.num_factor_clks = ARRAY_SIZE(top_divs),
++	.mux_clks = top_muxes,
++	.num_mux_clks = ARRAY_SIZE(top_muxes),
++	.composite_clks = top_aud_divs,
++	.num_composite_clks = ARRAY_SIZE(top_aud_divs),
++	.clk_lock = &mt7988_clk_lock,
++};
++
++static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" };
++
++static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" };
++
++static struct mtk_composite mcu_muxes[] = {
++	/* bus_pll_divider_cfg */
++	MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,
++		       CLK_IS_CRITICAL),
++	/* mp2_pll_divider_cfg */
++	MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1,
++		       CLK_IS_CRITICAL),
++};
++
++static const struct mtk_clk_desc mcusys_desc = {
++	.composite_clks = mcu_muxes,
++	.num_composite_clks = ARRAY_SIZE(mcu_muxes),
++};
++
++static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
++	{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
++	{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
++
++static struct platform_driver clk_mt7988_topckgen_drv = {
++	.probe = mtk_clk_simple_probe,
++	.remove = mtk_clk_simple_remove,
++	.driver = {
++		.name = "clk-mt7988-topckgen",
++		.of_match_table = of_match_clk_mt7988_topckgen,
++	},
++};
++module_platform_driver(clk_mt7988_topckgen_drv);
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/clk/mediatek/clk-mt7988-xfipll.c
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 Daniel Golle <[email protected]>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "clk-mtk.h"
++#include "clk-gate.h"
++#include <dt-bindings/clock/mediatek,mt7988-clk.h>
++
++/* Register to control USXGMII XFI PLL analog */
++#define XFI_PLL_ANA_GLB8		0x108
++#define RG_XFI_PLL_ANA_SWWA		0x02283248
++
++static const struct mtk_gate_regs xfipll_cg_regs = {
++	.set_ofs = 0x8,
++	.clr_ofs = 0x8,
++	.sta_ofs = 0x8,
++};
++
++#define GATE_XFIPLL(_id, _name, _parent, _shift)		\
++	{							\
++		.id = _id,					\
++		.name = _name,					\
++		.parent_name = _parent,				\
++		.regs = &xfipll_cg_regs,			\
++		.shift = _shift,				\
++		.ops = &mtk_clk_gate_ops_no_setclr_inv,		\
++	}
++
++static const struct mtk_fixed_factor xfipll_divs[] = {
++	FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32),
++};
++
++static const struct mtk_gate xfipll_clks[] = {
++	GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31),
++};
++
++static const struct mtk_clk_desc xfipll_desc = {
++	.clks = xfipll_clks,
++	.num_clks = ARRAY_SIZE(xfipll_clks),
++	.factor_clks = xfipll_divs,
++	.num_factor_clks = ARRAY_SIZE(xfipll_divs),
++};
++
++static int clk_mt7988_xfipll_probe(struct platform_device *pdev)
++{
++	struct device_node *node = pdev->dev.of_node;
++	void __iomem *base = of_iomap(node, 0);
++
++	if (!base)
++		return -ENOMEM;
++
++	/* Apply software workaround for USXGMII PLL TCL issue */
++	writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);
++	iounmap(base);
++
++	return mtk_clk_simple_probe(pdev);
++};
++
++static const struct of_device_id of_match_clk_mt7988_xfipll[] = {
++	{ .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll);
++
++static struct platform_driver clk_mt7988_xfipll_drv = {
++	.driver = {
++		.name = "clk-mt7988-xfipll",
++		.of_match_table = of_match_clk_mt7988_xfipll,
++	},
++	.probe = clk_mt7988_xfipll_probe,
++	.remove = mtk_clk_simple_remove,
++};
++module_platform_driver(clk_mt7988_xfipll_drv);
++
++MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");
++MODULE_LICENSE("GPL");

target/linux/mediatek/patches-6.6/250-clk-mediatek-add-infracfg-reset-controller-for-mt798.patch

@@ -0,0 +1,57 @@
+From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Wed, 17 Jan 2024 19:41:11 +0100
+Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988
+
+Infracfg can also operate as reset controller, add support for it.
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -14,6 +14,10 @@
+ #include "clk-gate.h"
+ #include "clk-mux.h"
+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++#include <dt-bindings/reset/mediatek,mt7988-resets.h>
++
++#define	MT7988_INFRA_RST0_SET_OFFSET	0x70
++#define	MT7988_INFRA_RST1_SET_OFFSET	0x80
+ 
+ static DEFINE_SPINLOCK(mt7988_clk_lock);
+ 
+@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[
+ 	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
+ };
+ 
++static u16 infra_rst_ofs[] = {
++	MT7988_INFRA_RST0_SET_OFFSET,
++	MT7988_INFRA_RST1_SET_OFFSET,
++};
++
++static u16 infra_idx_map[] = {
++	[MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
++	[MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
++};
++
++static struct mtk_clk_rst_desc infra_rst_desc = {
++	.version = MTK_RST_SET_CLR,
++	.rst_bank_ofs = infra_rst_ofs,
++	.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
++	.rst_idx_map = infra_idx_map,
++	.rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
++};
++
+ static const struct mtk_clk_desc infra_desc = {
+ 	.clks = infra_clks,
+ 	.num_clks = ARRAY_SIZE(infra_clks),
+ 	.mux_clks = infra_muxes,
+ 	.num_mux_clks = ARRAY_SIZE(infra_muxes),
+ 	.clk_lock = &mt7988_clk_lock,
++	.rst_desc = &infra_rst_desc,
+ };
+ 
+ static const struct of_device_id of_match_clk_mt7988_infracfg[] = {

target/linux/mediatek/patches-6.6/250-dt-bindings-reset-mediatek-add-MT7988-reset-IDs.patch

@@ -0,0 +1,25 @@
+From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001
+From: Frank Wunderlich <[email protected]>
+Date: Wed, 17 Jan 2024 19:41:10 +0100
+Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs
+
+Add reset constants for using as index in driver and dts.
+
+Signed-off-by: Frank Wunderlich <[email protected]>
+---
+ include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/include/dt-bindings/reset/mediatek,mt7988-resets.h
++++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
+@@ -10,4 +10,10 @@
+ /* ETHWARP resets */
+ #define MT7988_ETHWARP_RST_SWITCH		0
+ 
++/* INFRA resets */
++#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST	0
++#define MT7988_INFRA_RST1_THERM_CTRL_SWRST	1
++
++
+ #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
++

target/linux/mediatek/patches-6.6/251-v6.8-watchdog-mediatek-mt7988-add-wdt-support.patch

@@ -0,0 +1,125 @@
+From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Mon, 20 Nov 2023 18:22:31 +0000
+Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support
+
+Add support for watchdog and reset generator unit of the MediaTek
+MT7988 SoC.
+
+Signed-off-by: Daniel Golle <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Reviewed-by: Guenter Roeck <[email protected]>
+Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org
+Signed-off-by: Guenter Roeck <[email protected]>
+Signed-off-by: Wim Van Sebroeck <[email protected]>
+---
+ drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+--- a/drivers/watchdog/mtk_wdt.c
++++ b/drivers/watchdog/mtk_wdt.c
+@@ -56,9 +56,13 @@
+ #define WDT_SWSYSRST		0x18U
+ #define WDT_SWSYS_RST_KEY	0x88000000
+ 
++#define WDT_SWSYSRST_EN		0xfc
++
+ #define DRV_NAME		"mtk-wdt"
+ #define DRV_VERSION		"1.0"
+ 
++#define MT7988_TOPRGU_SW_RST_NUM	24
++
+ static bool nowayout = WATCHDOG_NOWAYOUT;
+ static unsigned int timeout;
+ 
+@@ -68,10 +72,12 @@ struct mtk_wdt_dev {
+ 	spinlock_t lock; /* protects WDT_SWSYSRST reg */
+ 	struct reset_controller_dev rcdev;
+ 	bool disable_wdt_extrst;
++	bool has_swsysrst_en;
+ };
+ 
+ struct mtk_wdt_data {
+ 	int toprgu_sw_rst_num;
++	bool has_swsysrst_en;
+ };
+ 
+ static const struct mtk_wdt_data mt2712_data = {
+@@ -82,6 +88,11 @@ static const struct mtk_wdt_data mt7986_
+ 	.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
+ };
+ 
++static const struct mtk_wdt_data mt7988_data = {
++	.toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM,
++	.has_swsysrst_en = true,
++};
++
+ static const struct mtk_wdt_data mt8183_data = {
+ 	.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
+ };
+@@ -98,6 +109,28 @@ static const struct mtk_wdt_data mt8195_
+ 	.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
+ };
+ 
++/**
++ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
++ * @data: Pointer to instance of driver data.
++ * @id: Bit number identifying the reset to be enabled or disabled.
++ * @enable: If true, enable software control for that bit, disable otherwise.
++ *
++ * Context: The caller must hold lock of struct mtk_wdt_dev.
++ */
++static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
++					unsigned long id, bool enable)
++{
++	u32 tmp;
++
++	tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
++	if (enable)
++		tmp |= BIT(id);
++	else
++		tmp &= ~BIT(id);
++
++	writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
++}
++
+ static int toprgu_reset_update(struct reset_controller_dev *rcdev,
+ 			       unsigned long id, bool assert)
+ {
+@@ -108,6 +141,9 @@ static int toprgu_reset_update(struct re
+ 
+ 	spin_lock_irqsave(&data->lock, flags);
+ 
++	if (assert && data->has_swsysrst_en)
++		toprgu_reset_sw_en_unlocked(data, id, true);
++
+ 	tmp = readl(data->wdt_base + WDT_SWSYSRST);
+ 	if (assert)
+ 		tmp |= BIT(id);
+@@ -116,6 +152,9 @@ static int toprgu_reset_update(struct re
+ 	tmp |= WDT_SWSYS_RST_KEY;
+ 	writel(tmp, data->wdt_base + WDT_SWSYSRST);
+ 
++	if (!assert && data->has_swsysrst_en)
++		toprgu_reset_sw_en_unlocked(data, id, false);
++
+ 	spin_unlock_irqrestore(&data->lock, flags);
+ 
+ 	return 0;
+@@ -393,6 +432,8 @@ static int mtk_wdt_probe(struct platform
+ 						       wdt_data->toprgu_sw_rst_num);
+ 		if (err)
+ 			return err;
++
++		mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
+ 	}
+ 
+ 	mtk_wdt->disable_wdt_extrst =
+@@ -427,6 +468,7 @@ static const struct of_device_id mtk_wdt
+ 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
+ 	{ .compatible = "mediatek,mt6589-wdt" },
+ 	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
++	{ .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
+ 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
+ 	{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
+ 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },

target/linux/mediatek/patches-6.6/252-clk-mediatek-mt7988-infracfg-fix-clocks-for-2nd-PCIe.patch

@@ -0,0 +1,31 @@
+From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <[email protected]>
+Date: Mon, 11 Mar 2024 17:14:19 +0000
+Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port
+
+Due to what seems to be an undocumented oddity in MediaTek's MT7988
+SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
+CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
+
+This currently leads to PCIe port 2 not working in Linux.
+
+Reflect the apparent relationship in the clk driver to make sure PCIe
+port 2 of the MT7988 SoC works.
+
+Suggested-by: Sam Shih <[email protected]>
+Signed-off-by: Daniel Golle <[email protected]>
+---
+ drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
++++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
+@@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[
+ 	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
+ 		    "csw_infra_f26m_sel", 8),
+ 	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
+-		    "csw_infra_f26m_sel", 9),
++		    "infra_pcie_peri_ck_26m_ck_p3", 9),
+ 	GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
+ 		    "csw_infra_f26m_sel", 10),
+ 	/* INFRA1 */

target/linux/mediatek/patches-6.6/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch

@@ -0,0 +1,47 @@
+From 24e961b93d292d0dd6380213d22a071a99ea787d Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Tue, 25 Oct 2022 15:29:53 +0200
+Subject: [PATCH 1/6] mmc: mediatek: add support for MT7986 SoC
+
+Adding mt7986 own characteristics and of_device_id to have support
+of MT7986 SoC.
+
+Signed-off-by: Sam Shih <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Ulf Hansson <[email protected]>
+---
+ drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -552,6 +552,19 @@ static const struct mtk_mmc_compatible m
+ 	.support_64g = false,
+ };
+ 
++static const struct mtk_mmc_compatible mt7986_compat = {
++	.clk_div_bits = 12,
++	.recheck_sdio_irq = true,
++	.hs400_tune = false,
++	.pad_tune_reg = MSDC_PAD_TUNE0,
++	.async_fifo = true,
++	.data_tune = true,
++	.busy_check = true,
++	.stop_clk_fix = true,
++	.enhance_rx = true,
++	.support_64g = true,
++};
++
+ static const struct mtk_mmc_compatible mt8135_compat = {
+ 	.clk_div_bits = 8,
+ 	.recheck_sdio_irq = true,
+@@ -609,6 +622,7 @@ static const struct of_device_id msdc_of
+ 	{ .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
+ 	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
+ 	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
++	{ .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
+ 	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
+ 	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
+ 	{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},

target/linux/mediatek/patches-6.6/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch

@@ -0,0 +1,57 @@
+From 7b438d0377fbd520b475a68bdd9de1692393f22d Mon Sep 17 00:00:00 2001
+From: Mengqi Zhang <[email protected]>
+Date: Sun, 6 Nov 2022 11:39:24 +0800
+Subject: [PATCH 2/6] mmc: mtk-sd: add Inline Crypto Engine clock control
+
+Add crypto clock control and ungate it before CQHCI init.
+
+Signed-off-by: Mengqi Zhang <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Ulf Hansson <[email protected]>
+---
+ drivers/mmc/host/mtk-sd.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -452,6 +452,7 @@ struct msdc_host {
+ 	struct clk *bus_clk;	/* bus clock which used to access register */
+ 	struct clk *src_clk_cg; /* msdc source clock control gate */
+ 	struct clk *sys_clk_cg;	/* msdc subsys clock control gate */
++	struct clk *crypto_clk; /* msdc crypto clock control gate */
+ 	struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
+ 	u32 mclk;		/* mmc subsystem clock frequency */
+ 	u32 src_clk_freq;	/* source clock frequency */
+@@ -840,6 +841,7 @@ static void msdc_set_busy_timeout(struct
+ static void msdc_gate_clock(struct msdc_host *host)
+ {
+ 	clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
++	clk_disable_unprepare(host->crypto_clk);
+ 	clk_disable_unprepare(host->src_clk_cg);
+ 	clk_disable_unprepare(host->src_clk);
+ 	clk_disable_unprepare(host->bus_clk);
+@@ -855,6 +857,7 @@ static int msdc_ungate_clock(struct msdc
+ 	clk_prepare_enable(host->bus_clk);
+ 	clk_prepare_enable(host->src_clk);
+ 	clk_prepare_enable(host->src_clk_cg);
++	clk_prepare_enable(host->crypto_clk);
+ 	ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
+ 	if (ret) {
+ 		dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
+@@ -2670,6 +2673,15 @@ static int msdc_drv_probe(struct platfor
+ 		goto host_free;
+ 	}
+ 
++	/* only eMMC has crypto property */
++	if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
++		host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
++		if (IS_ERR(host->crypto_clk))
++			host->crypto_clk = NULL;
++		else
++			mmc->caps2 |= MMC_CAP2_CRYPTO;
++	}
++
+ 	host->irq = platform_get_irq(pdev, 0);
+ 	if (host->irq < 0) {
+ 		ret = host->irq;

target/linux/mediatek/patches-6.6/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch

@@ -0,0 +1,36 @@
+From 4b323f02b6e8df1b04292635ef829e7f723bf50e Mon Sep 17 00:00:00 2001
+From: Yu Zhe <[email protected]>
+Date: Thu, 10 Nov 2022 15:28:19 +0800
+Subject: [PATCH 3/6] mmc: mtk-sd: fix two spelling mistakes in comment
+
+spelling mistake fix : "alreay" -> "already"
+		       "checksume" -> "checksum"
+
+Signed-off-by: Yu Zhe <[email protected]>
+Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Ulf Hansson <[email protected]>
+---
+ drivers/mmc/host/mtk-sd.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -750,7 +750,7 @@ static inline void msdc_dma_setup(struct
+ 		else
+ 			bd[j].bd_info &= ~BDMA_DESC_EOL;
+ 
+-		/* checksume need to clear first */
++		/* checksum need to clear first */
+ 		bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
+ 		bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
+ 	}
+@@ -1229,7 +1229,7 @@ static bool msdc_cmd_done(struct msdc_ho
+ 		     !host->hs400_tuning))
+ 			/*
+ 			 * should not clear fifo/interrupt as the tune data
+-			 * may have alreay come when cmd19/cmd21 gets response
++			 * may have already come when cmd19/cmd21 gets response
+ 			 * CRC error.
+ 			 */
+ 			msdc_reset_hw(host);

target/linux/mediatek/patches-6.6/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch

@@ -0,0 +1,39 @@
+From b98e7e8daf0ebab9dcc36812378a71e1be0b5089 Mon Sep 17 00:00:00 2001
+From: ChanWoo Lee <[email protected]>
+Date: Thu, 24 Nov 2022 17:00:31 +0900
+Subject: [PATCH 4/6] mmc: Avoid open coding by using mmc_op_tuning()
+
+Replace code with the already defined function. No functional changes.
+
+Signed-off-by: ChanWoo Lee <[email protected]>
+Reviewed-by: Adrian Hunter <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Ulf Hansson <[email protected]>
+---
+ drivers/mmc/host/mtk-sd.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -1224,9 +1224,7 @@ static bool msdc_cmd_done(struct msdc_ho
+ 
+ 	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
+ 		if (events & MSDC_INT_CMDTMO ||
+-		    (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
+-		     cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 &&
+-		     !host->hs400_tuning))
++		    (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
+ 			/*
+ 			 * should not clear fifo/interrupt as the tune data
+ 			 * may have already come when cmd19/cmd21 gets response
+@@ -1320,9 +1318,7 @@ static void msdc_cmd_next(struct msdc_ho
+ {
+ 	if ((cmd->error &&
+ 	    !(cmd->error == -EILSEQ &&
+-	      (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
+-	       cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 ||
+-	       host->hs400_tuning))) ||
++	      (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) ||
+ 	    (mrq->sbc && mrq->sbc->error))
+ 		msdc_request_done(host, mrq);
+ 	else if (cmd == mrq->sbc)

target/linux/mediatek/patches-6.6/330-snand-mtk-bmt-support.patch

@@ -0,0 +1,34 @@
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -19,6 +19,7 @@
+ #include <linux/string.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/spi-mem.h>
++#include <linux/mtd/mtk_bmt.h>
+ 
+ static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
+ {
+@@ -1344,6 +1345,7 @@ static int spinand_probe(struct spi_mem
+ 	if (ret)
+ 		return ret;
+ 
++	mtk_bmt_attach(mtd);
+ 	ret = mtd_device_register(mtd, NULL, 0);
+ 	if (ret)
+ 		goto err_spinand_cleanup;
+@@ -1351,6 +1353,7 @@ static int spinand_probe(struct spi_mem
+ 	return 0;
+ 
+ err_spinand_cleanup:
++	mtk_bmt_detach(mtd);
+ 	spinand_cleanup(spinand);
+ 
+ 	return ret;
+@@ -1369,6 +1372,7 @@ static int spinand_remove(struct spi_mem
+ 	if (ret)
+ 		return ret;
+ 
++	mtk_bmt_detach(mtd);
+ 	spinand_cleanup(spinand);
+ 
+ 	return 0;

target/linux/mediatek/patches-6.6/331-mt7622-rfb1-enable-bmt.patch

@@ -0,0 +1,10 @@
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -548,6 +548,7 @@
+ 		spi-tx-bus-width = <4>;
+ 		spi-rx-bus-width = <4>;
+ 		nand-ecc-engine = <&snfi>;
++		mediatek,bmt-v2;
+ 
+ 		partitions {
+ 			compatible = "fixed-partitions";

target/linux/mediatek/patches-6.6/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch

@@ -0,0 +1,122 @@
+From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001
+From: Davide Fioravanti <[email protected]>
+Date: Fri, 8 Jan 2021 15:35:24 +0100
+Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA
+
+Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf
+
+Signed-off-by: Davide Fioravanti <[email protected]>
+---
+ drivers/mtd/nand/spi/Makefile  |  2 +-
+ drivers/mtd/nand/spi/core.c    |  1 +
+ drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++
+ include/linux/mtd/spinand.h    |  1 +
+ 4 files changed, 79 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/mtd/nand/spi/fidelix.c
+
+--- a/drivers/mtd/nand/spi/Makefile
++++ b/drivers/mtd/nand/spi/Makefile
+@@ -1,3 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0
+-spinand-objs := core.o ato.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
++spinand-objs := core.o ato.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
+ obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -940,6 +940,7 @@ static const struct nand_ops spinand_ops
+ static const struct spinand_manufacturer *spinand_manufacturers[] = {
+ 	&ato_spinand_manufacturer,
+ 	&esmt_c8_spinand_manufacturer,
++	&fidelix_spinand_manufacturer,
+ 	&etron_spinand_manufacturer,
+ 	&gigadevice_spinand_manufacturer,
+ 	&macronix_spinand_manufacturer,
+--- /dev/null
++++ b/drivers/mtd/nand/spi/fidelix.c
+@@ -0,0 +1,76 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2020 Davide Fioravanti <[email protected]>
++ */
++
++#include <linux/device.h>
++#include <linux/kernel.h>
++#include <linux/mtd/spinand.h>
++
++#define SPINAND_MFR_FIDELIX		0xE5
++#define FIDELIX_ECCSR_MASK		0x0F
++
++static SPINAND_OP_VARIANTS(read_cache_variants,
++		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
++		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
++
++static SPINAND_OP_VARIANTS(write_cache_variants,
++		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
++		SPINAND_PROG_LOAD(true, 0, NULL, 0));
++
++static SPINAND_OP_VARIANTS(update_cache_variants,
++		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
++		SPINAND_PROG_LOAD(false, 0, NULL, 0));
++
++static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section,
++				  struct mtd_oob_region *region)
++{
++	if (section > 3)
++		return -ERANGE;
++
++	region->offset = (16 * section) + 8;
++	region->length = 8;
++
++	return 0;
++}
++
++static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section,
++				   struct mtd_oob_region *region)
++{
++	if (section > 3)
++		return -ERANGE;
++
++	region->offset = (16 * section) + 2;
++	region->length = 6;
++
++	return 0;
++}
++
++static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = {
++	.ecc = fm35x1ga_ooblayout_ecc,
++	.free = fm35x1ga_ooblayout_free,
++};
++
++static const struct spinand_info fidelix_spinand_table[] = {
++	SPINAND_INFO("FM35X1GA",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
++		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(4, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)),
++};
++
++static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = {
++};
++
++const struct spinand_manufacturer fidelix_spinand_manufacturer = {
++	.id = SPINAND_MFR_FIDELIX,
++	.name = "Fidelix",
++	.chips = fidelix_spinand_table,
++	.nchips = ARRAY_SIZE(fidelix_spinand_table),
++	.ops = &fidelix_spinand_manuf_ops,
++};
+--- a/include/linux/mtd/spinand.h
++++ b/include/linux/mtd/spinand.h
+@@ -263,6 +263,7 @@ struct spinand_manufacturer {
+ extern const struct spinand_manufacturer ato_spinand_manufacturer;
+ extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
+ extern const struct spinand_manufacturer etron_spinand_manufacturer;
++extern const struct spinand_manufacturer fidelix_spinand_manufacturer;
+ extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
+ extern const struct spinand_manufacturer macronix_spinand_manufacturer;
+ extern const struct spinand_manufacturer micron_spinand_manufacturer;

target/linux/mediatek/patches-6.6/350-21-cpufreq-mediatek-Add-support-for-MT7988.patch

@@ -0,0 +1,41 @@
+From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001
+From: Sam Shih <[email protected]>
+Date: Tue, 28 Feb 2023 19:59:22 +0800
+Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988
+
+This add cpufreq support for mediatek MT7988 SoC.
+
+The platform data of MT7988 is different from previous MediaTek SoCs,
+so we add a new compatible and platform data for it.
+
+Signed-off-by: Sam Shih <[email protected]>
+---
+ drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/cpufreq/mediatek-cpufreq.c
++++ b/drivers/cpufreq/mediatek-cpufreq.c
+@@ -709,6 +709,15 @@ static const struct mtk_cpufreq_platform
+ 	.ccifreq_supported = false,
+ };
+ 
++static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
++	.min_volt_shift = 100000,
++	.max_volt_shift = 200000,
++	.proc_max_volt = 900000,
++	.sram_min_volt = 0,
++	.sram_max_volt = 1150000,
++	.ccifreq_supported = true,
++};
++
+ static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
+ 	.min_volt_shift = 100000,
+ 	.max_volt_shift = 200000,
+@@ -742,6 +751,7 @@ static const struct of_device_id mtk_cpu
+ 	{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
+ 	{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
+ 	{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
++	{ .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
+ 	{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
+ 	{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
+ 	{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },

target/linux/mediatek/patches-6.6/351-pinctrl-add-mt7988-pd-pulltype-support.patch

@@ -0,0 +1,99 @@
+--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+@@ -601,6 +601,30 @@ out:
+ 	return err;
+ }
+ 
++static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
++				const struct mtk_pin_desc *desc,
++				u32 pullup, u32 arg)
++{
++    int err, pd;
++
++	if (arg == MTK_DISABLE)
++		pd = 0;
++	else if ((arg == MTK_ENABLE) && pullup)
++		pd = 0;
++	else if ((arg == MTK_ENABLE) && !pullup)
++		pd = 1;
++	else {
++		err = -EINVAL;
++		goto out;
++	}
++
++	err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
++
++out:
++	return err;
++
++}
++
+ static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
+ 				const struct mtk_pin_desc *desc,
+ 				u32 pullup, u32 arg)
+@@ -755,6 +779,12 @@ int mtk_pinconf_bias_set_combo(struct mt
+ 			return err;
+ 	}
+ 
++	if (try_all_type & MTK_PULL_PD_TYPE) {
++		err = mtk_pinconf_bias_set_pd(hw, desc, pullup, arg);
++		if (!err)
++			return err;
++    }
++
+ 	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
+ 		err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
+ 		if (!err)
+@@ -875,6 +905,29 @@ out:
+ 	return err;
+ }
+ 
++static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
++				const struct mtk_pin_desc *desc,
++				u32 *pullup, u32 *enable)
++{
++	int err, pd;
++
++	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
++	if (err)
++		goto out;
++
++	if (pd == 0) {
++		*pullup = 0;
++		*enable = MTK_DISABLE;
++	} else if (pd == 1) {
++		*pullup = 0;
++		*enable = MTK_ENABLE;
++	} else
++		err = -EINVAL;
++
++out:
++	return err;
++}
++
+ static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
+ 				const struct mtk_pin_desc *desc,
+ 				u32 *pullup, u32 *enable)
+@@ -943,6 +996,12 @@ int mtk_pinconf_bias_get_combo(struct mt
+ 		if (!err)
+ 			return err;
+ 	}
++
++	if (try_all_type & MTK_PULL_PD_TYPE) {
++		err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
++		if (!err)
++			return err;
++	}
+ 
+ 	if (try_all_type & MTK_PULL_PU_PD_TYPE) {
+ 		err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
+--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+@@ -24,6 +24,7 @@
+  * turned on/off itself. But it can't be selected pull up/down
+  */
+ #define MTK_PULL_RSEL_TYPE		BIT(3)
++#define MTK_PULL_PD_TYPE        BIT(4)
+ /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
+  * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
+  */

target/linux/mediatek/patches-6.6/400-crypto-add-eip97-inside-secure-support.patch

@@ -0,0 +1,27 @@
+--- a/drivers/crypto/inside-secure/safexcel.c
++++ b/drivers/crypto/inside-secure/safexcel.c
+@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex
+ 		val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
+ 		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
+ 	}
++	/*
++	 * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
++	 */
++	else {
++		val = 0;
++		val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
++		writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
++	}
+ 
+ 	/* Configure wr/rd cache values */
+ 	writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
+--- a/drivers/crypto/inside-secure/safexcel.h
++++ b/drivers/crypto/inside-secure/safexcel.h
+@@ -315,6 +315,7 @@
+ #define EIP197_MST_CTRL_RD_CACHE(n)		(((n) & 0xf) << 0)
+ #define EIP197_MST_CTRL_WD_CACHE(n)		(((n) & 0xf) << 4)
+ #define EIP197_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 20)
++#define EIP97_MST_CTRL_TX_MAX_CMD(n)		(((n) & 0xf) << 4)
+ #define EIP197_MST_CTRL_BYTE_SWAP		BIT(24)
+ #define EIP197_MST_CTRL_NO_BYTE_SWAP		BIT(25)
+ #define EIP197_MST_CTRL_BYTE_SWAP_BITS          GENMASK(25, 24)

target/linux/mediatek/patches-6.6/401-crypto-fix-eip97-cache-incoherent.patch

@@ -0,0 +1,26 @@
+--- a/drivers/crypto/inside-secure/safexcel.h
++++ b/drivers/crypto/inside-secure/safexcel.h
+@@ -737,6 +737,9 @@ enum safexcel_eip_version {
+ /* Priority we use for advertising our algorithms */
+ #define SAFEXCEL_CRA_PRIORITY		300
+ 
++/* System cache line size */
++#define SYSTEM_CACHELINE_SIZE		64
++
+ /* SM3 digest result for zero length message */
+ #define EIP197_SM3_ZEROM_HASH	"\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
+ 				"\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
+--- a/drivers/crypto/inside-secure/safexcel_hash.c
++++ b/drivers/crypto/inside-secure/safexcel_hash.c
+@@ -55,9 +55,9 @@ struct safexcel_ahash_req {
+ 	u8 block_sz;    /* block size, only set once */
+ 	u8 digest_sz;   /* output digest size, only set once */
+ 	__le32 state[SHA3_512_BLOCK_SIZE /
+-		     sizeof(__le32)] __aligned(sizeof(__le32));
++		     sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);
+ 
+-	u64 len;
++	u64 len __aligned(SYSTEM_CACHELINE_SIZE);
+ 	u64 processed;
+ 
+ 	u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));

target/linux/mediatek/patches-6.6/405-v6.2-mt7986-trng-add-rng-support.patch

@@ -0,0 +1,43 @@
+From f1da27b7c4191f78ed81d3dabf64c769f896296c Mon Sep 17 00:00:00 2001
+From: "Mingming.Su" <[email protected]>
+Date: Sat, 8 Oct 2022 18:45:53 +0200
+Subject: [PATCH] hwrng: mtk - add mt7986 support
+
+1. Add trng compatible name for MT7986
+2. Fix mtk_rng_wait_ready() function
+
+Signed-off-by: Mingming.Su <[email protected]>
+Signed-off-by: Frank Wunderlich <[email protected]>
+Signed-off-by: Herbert Xu <[email protected]>
+---
+ drivers/char/hw_random/mtk-rng.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/char/hw_random/mtk-rng.c
++++ b/drivers/char/hw_random/mtk-rng.c
+@@ -22,7 +22,7 @@
+ #define RNG_AUTOSUSPEND_TIMEOUT		100
+ 
+ #define USEC_POLL			2
+-#define TIMEOUT_POLL			20
++#define TIMEOUT_POLL			60
+ 
+ #define RNG_CTRL			0x00
+ #define RNG_EN				BIT(0)
+@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw
+ 		readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
+ 					  ready & RNG_READY, USEC_POLL,
+ 					  TIMEOUT_POLL);
+-	return !!ready;
++	return !!(ready & RNG_READY);
+ }
+ 
+ static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p
+ #endif	/* CONFIG_PM */
+ 
+ static const struct of_device_id mtk_rng_match[] = {
++	{ .compatible = "mediatek,mt7986-rng" },
+ 	{ .compatible = "mediatek,mt7623-rng" },
+ 	{},
+ };

target/linux/mediatek/patches-6.6/410-bt-mtk-serial-fix.patch

@@ -0,0 +1,33 @@
+--- a/drivers/tty/serial/8250/8250.h
++++ b/drivers/tty/serial/8250/8250.h
+@@ -86,6 +86,7 @@ struct serial8250_config {
+ 					 * STOP PARITY EPAR SPAR WLEN5 WLEN6
+ 					 */
+ #define UART_CAP_NOTEMT	BIT(18)	/* UART without interrupt on TEMT available */
++#define UART_CAP_NMOD	BIT(19)	/* UART doesn't do termios */
+ 
+ #define UART_BUG_QUOT	BIT(0)	/* UART has buggy quot LSB */
+ #define UART_BUG_TXEN	BIT(1)	/* UART has buggy TX IIR status */
+--- a/drivers/tty/serial/8250/8250_port.c
++++ b/drivers/tty/serial/8250/8250_port.c
+@@ -287,7 +287,7 @@ static const struct serial8250_config ua
+ 		.tx_loadsz	= 16,
+ 		.fcr		= UART_FCR_ENABLE_FIFO |
+ 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
+-		.flags		= UART_CAP_FIFO,
++		.flags		= UART_CAP_FIFO | UART_CAP_NMOD,
+ 	},
+ 	[PORT_NPCM] = {
+ 		.name		= "Nuvoton 16550",
+@@ -2773,6 +2773,11 @@ serial8250_do_set_termios(struct uart_po
+ 	unsigned long flags;
+ 	unsigned int baud, quot, frac = 0;
+ 
++	if (up->capabilities & UART_CAP_NMOD) {
++		termios->c_cflag = 0;
++		return;
++	}
++
+ 	if (up->capabilities & UART_CAP_MINI) {
+ 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
+ 		if ((termios->c_cflag & CSIZE) == CS5 ||