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@@ -0,0 +1,422 @@
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+From 8eff8eb83fc0ae8b5f76220e2bb8644d836e99ff Mon Sep 17 00:00:00 2001
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+From: Nicolas Frattaroli <[email protected]>
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+Date: Tue, 4 Feb 2025 16:35:50 +0100
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+Subject: [PATCH] hwrng: rockchip - add support for rk3588's standalone TRNG
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+
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+The RK3588 SoC includes several TRNGs, one part of the Crypto IP block,
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+and the other one (referred to as "trngv1") as a standalone new IP.
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+
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+Add support for this new standalone TRNG to the driver by both
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+generalising it to support multiple different rockchip RNGs and then
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+implementing the required functionality for the new hardware.
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+
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+This work was partly based on the downstream vendor driver by Rockchip's
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+Lin Jinhan, which is why they are listed as a Co-author.
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+
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+While the hardware does support notifying the CPU with an IRQ when the
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+random data is ready, I've discovered while implementing the code to use
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+this interrupt that this results in significantly slower throughput of
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+the TRNG even when under heavy CPU load. I assume this is because with
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+only 32 bytes of data per invocation, the overhead of reinitialising a
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+completion, enabling the interrupt, sleeping and then triggering the
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+completion in the IRQ handler is way more expensive than busylooping.
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+
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+Speaking of busylooping, the poll interval for reading the ISTAT is an
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+atomic read with a delay of 0. In my testing, I've found that this gives
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+us the largest throughput, and it appears the random data is ready
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+pretty much the moment we begin polling, as increasing the poll delay
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+leads to a drop in throughput significant enough to not just be due to
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+the poll interval missing the ideal timing by a microsecond or two.
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+
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+According to downstream, the IP should take 1024 clock cycles to
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+generate 56 bits of random data, which at 150MHz should work out to
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+6.8us. I did not test whether the data really does take 256/56*6.8us
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+to arrive, though changing the readl to a __raw_readl makes no
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+difference in throughput, and this data does pass the rngtest FIPS
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+checks, so I'm not entirely sure what's going on but I presume it's got
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+something to do with the AHB bus speed and the memory barriers that
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+mainline's readl/writel functions insert.
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+
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+The only other current SoC that uses this new IP is the Rockchip RV1106,
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+but that SoC does not have mainline support as of the time of writing,
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+so we make no effort to declare it as supported for now.
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+
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+Co-developed-by: Lin Jinhan <[email protected]>
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+Signed-off-by: Lin Jinhan <[email protected]>
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+Signed-off-by: Nicolas Frattaroli <[email protected]>
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+Signed-off-by: Herbert Xu <[email protected]>
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+---
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+ drivers/char/hw_random/Kconfig | 3 +-
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+ drivers/char/hw_random/rockchip-rng.c | 234 +++++++++++++++++++++++---
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+ 2 files changed, 216 insertions(+), 21 deletions(-)
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+
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+--- a/drivers/char/hw_random/Kconfig
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++++ b/drivers/char/hw_random/Kconfig
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+@@ -580,7 +580,8 @@ config HW_RANDOM_ROCKCHIP
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+ default HW_RANDOM
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+ help
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+ This driver provides kernel-side support for the True Random Number
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+- Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
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++ Generator hardware found on some Rockchip SoCs like RK3566, RK3568
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++ or RK3588.
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+
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+ To compile this driver as a module, choose M here: the
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+ module will be called rockchip-rng.
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+--- a/drivers/char/hw_random/rockchip-rng.c
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++++ b/drivers/char/hw_random/rockchip-rng.c
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+@@ -1,12 +1,14 @@
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+ // SPDX-License-Identifier: GPL-2.0
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+ /*
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+- * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC
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++ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs
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+ *
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+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
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+ * Copyright (c) 2022, Aurelien Jarno
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++ * Copyright (c) 2025, Collabora Ltd.
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+ * Authors:
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+ * Lin Jinhan <[email protected]>
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+ * Aurelien Jarno <[email protected]>
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++ * Nicolas Frattaroli <[email protected]>
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+ */
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+ #include <linux/clk.h>
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+ #include <linux/hw_random.h>
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+@@ -32,6 +34,9 @@
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+ */
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+ #define RK_RNG_SAMPLE_CNT 1000
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+
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++/* after how many bytes of output TRNGv1 implementations should be reseeded */
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++#define RK_TRNG_V1_AUTO_RESEED_CNT 16000
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++
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+ /* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
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+ #define TRNG_RST_CTL 0x0004
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+ #define TRNG_RNG_CTL 0x0400
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+@@ -49,25 +54,85 @@
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+ #define TRNG_RNG_SAMPLE_CNT 0x0404
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+ #define TRNG_RNG_DOUT 0x0410
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+
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++/*
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++ * TRNG V1 register definitions
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++ * The TRNG V1 IP is a stand-alone TRNG implementation (not part of a crypto IP)
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++ * and can be found in the Rockchip RK3588 SoC
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++ */
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++#define TRNG_V1_CTRL 0x0000
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++#define TRNG_V1_CTRL_NOP 0x00
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++#define TRNG_V1_CTRL_RAND 0x01
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++#define TRNG_V1_CTRL_SEED 0x02
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++
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++#define TRNG_V1_STAT 0x0004
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++#define TRNG_V1_STAT_SEEDED BIT(9)
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++#define TRNG_V1_STAT_GENERATING BIT(30)
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++#define TRNG_V1_STAT_RESEEDING BIT(31)
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++
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++#define TRNG_V1_MODE 0x0008
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++#define TRNG_V1_MODE_128_BIT (0x00 << 3)
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++#define TRNG_V1_MODE_256_BIT (0x01 << 3)
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++
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++/* Interrupt Enable register; unused because polling is faster */
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++#define TRNG_V1_IE 0x0010
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++#define TRNG_V1_IE_GLBL_EN BIT(31)
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++#define TRNG_V1_IE_SEED_DONE_EN BIT(1)
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++#define TRNG_V1_IE_RAND_RDY_EN BIT(0)
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++
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++#define TRNG_V1_ISTAT 0x0014
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++#define TRNG_V1_ISTAT_RAND_RDY BIT(0)
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++
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++/* RAND0 ~ RAND7 */
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++#define TRNG_V1_RAND0 0x0020
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++#define TRNG_V1_RAND7 0x003C
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++
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++/* Auto Reseed Register */
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++#define TRNG_V1_AUTO_RQSTS 0x0060
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++
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++#define TRNG_V1_VERSION 0x00F0
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++#define TRNG_v1_VERSION_CODE 0x46bc
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++/* end of TRNG_V1 register definitions */
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++
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++/* Before removing this assert, give rk3588_rng_read an upper bound of 32 */
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++static_assert(RK_RNG_MAX_BYTE <= (TRNG_V1_RAND7 + 4 - TRNG_V1_RAND0),
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++ "You raised RK_RNG_MAX_BYTE and broke rk3588-rng, congrats.");
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++
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+ struct rk_rng {
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+ struct hwrng rng;
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+ void __iomem *base;
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+ int clk_num;
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+ struct clk_bulk_data *clk_bulks;
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++ const struct rk_rng_soc_data *soc_data;
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+ struct device *dev;
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+ };
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+
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++struct rk_rng_soc_data {
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++ int (*rk_rng_init)(struct hwrng *rng);
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++ int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
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++ void (*rk_rng_cleanup)(struct hwrng *rng);
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++ unsigned short quality;
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++ bool reset_optional;
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++};
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++
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+ /* The mask in the upper 16 bits determines the bits that are updated */
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+ static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
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+ {
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+ writel((mask << 16) | val, rng->base + TRNG_RNG_CTL);
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+ }
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+
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+-static int rk_rng_init(struct hwrng *rng)
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++static inline void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
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+ {
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+- struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
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+- int ret;
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++ writel(val, rng->base + offset);
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++}
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+
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++static inline u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
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++{
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++ return readl(rng->base + offset);
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++}
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++
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++static int rk_rng_enable_clks(struct rk_rng *rk_rng)
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++{
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++ int ret;
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+ /* start clocks */
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+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
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+ if (ret < 0) {
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+@@ -75,6 +140,18 @@ static int rk_rng_init(struct hwrng *rng
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+ return ret;
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+ }
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+
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++ return 0;
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++}
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++
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++static int rk3568_rng_init(struct hwrng *rng)
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++{
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++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
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++ int ret;
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++
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++ ret = rk_rng_enable_clks(rk_rng);
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++ if (ret < 0)
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++ return ret;
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++
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+ /* set the sample period */
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+ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
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+
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+@@ -87,7 +164,7 @@ static int rk_rng_init(struct hwrng *rng
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+ return 0;
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+ }
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+
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+-static void rk_rng_cleanup(struct hwrng *rng)
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++static void rk3568_rng_cleanup(struct hwrng *rng)
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+ {
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+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
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+
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+@@ -98,7 +175,7 @@ static void rk_rng_cleanup(struct hwrng
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+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
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+ }
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+
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+-static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
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++static int rk3568_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
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+ {
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+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
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+ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE);
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+@@ -128,6 +205,114 @@ out:
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+ return (ret < 0) ? ret : to_read;
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+ }
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+
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++static int rk3588_rng_init(struct hwrng *rng)
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++{
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++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
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++ u32 version, status, mask, istat;
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++ int ret;
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++
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++ ret = rk_rng_enable_clks(rk_rng);
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++ if (ret < 0)
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++ return ret;
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++
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++ version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
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++ if (version != TRNG_v1_VERSION_CODE) {
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++ dev_err(rk_rng->dev,
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++ "wrong trng version, expected = %08x, actual = %08x\n",
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++ TRNG_V1_VERSION, version);
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++ ret = -EFAULT;
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++ goto err_disable_clk;
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++ }
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++
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++ mask = TRNG_V1_STAT_SEEDED | TRNG_V1_STAT_GENERATING |
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++ TRNG_V1_STAT_RESEEDING;
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++ if (readl_poll_timeout(rk_rng->base + TRNG_V1_STAT, status,
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++ (status & mask) == TRNG_V1_STAT_SEEDED,
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++ RK_RNG_POLL_PERIOD_US, RK_RNG_POLL_TIMEOUT_US) < 0) {
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++ dev_err(rk_rng->dev, "timed out waiting for hwrng to reseed\n");
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++ ret = -ETIMEDOUT;
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++ goto err_disable_clk;
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++ }
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++
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++ /*
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++ * clear ISTAT flag, downstream advises to do this to avoid
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++ * auto-reseeding "on power on"
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++ */
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++ istat = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
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++ rk_rng_writel(rk_rng, istat, TRNG_V1_ISTAT);
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++
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++ /* auto reseed after RK_TRNG_V1_AUTO_RESEED_CNT bytes */
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++ rk_rng_writel(rk_rng, RK_TRNG_V1_AUTO_RESEED_CNT / 16, TRNG_V1_AUTO_RQSTS);
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++
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++ return 0;
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++err_disable_clk:
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++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
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++ return ret;
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++}
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++
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++static void rk3588_rng_cleanup(struct hwrng *rng)
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++{
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++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
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++
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++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
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++}
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++
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++static int rk3588_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
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++{
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++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
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++ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE);
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++ int ret = 0;
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++ u32 reg;
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++
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++ ret = pm_runtime_resume_and_get(rk_rng->dev);
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++ if (ret < 0)
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++ return ret;
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++
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++ /* Clear ISTAT, even without interrupts enabled, this will be updated */
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++ reg = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
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++ rk_rng_writel(rk_rng, reg, TRNG_V1_ISTAT);
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++
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++ /* generate 256 bits of random data */
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++ rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
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++ rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
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++
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++ ret = readl_poll_timeout_atomic(rk_rng->base + TRNG_V1_ISTAT, reg,
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++ (reg & TRNG_V1_ISTAT_RAND_RDY), 0,
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++ RK_RNG_POLL_TIMEOUT_US);
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++ if (ret < 0)
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++ goto out;
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++
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++ /* Read random data that's in registers TRNG_V1_RAND0 through RAND7 */
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++ memcpy_fromio(buf, rk_rng->base + TRNG_V1_RAND0, to_read);
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++
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++out:
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++ /* Clear ISTAT */
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++ rk_rng_writel(rk_rng, reg, TRNG_V1_ISTAT);
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++ /* close the TRNG */
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++ rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
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++
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++ pm_runtime_mark_last_busy(rk_rng->dev);
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++ pm_runtime_put_sync_autosuspend(rk_rng->dev);
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++
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++ return (ret < 0) ? ret : to_read;
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++}
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++
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++static const struct rk_rng_soc_data rk3568_soc_data = {
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++ .rk_rng_init = rk3568_rng_init,
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++ .rk_rng_read = rk3568_rng_read,
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++ .rk_rng_cleanup = rk3568_rng_cleanup,
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++ .quality = 900,
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++ .reset_optional = false,
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++};
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++
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++static const struct rk_rng_soc_data rk3588_soc_data = {
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++ .rk_rng_init = rk3588_rng_init,
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++ .rk_rng_read = rk3588_rng_read,
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++ .rk_rng_cleanup = rk3588_rng_cleanup,
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++ .quality = 999, /* as determined by actual testing */
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++ .reset_optional = true,
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++};
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++
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+ static int rk_rng_probe(struct platform_device *pdev)
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+ {
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+ struct device *dev = &pdev->dev;
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+@@ -139,6 +324,7 @@ static int rk_rng_probe(struct platform_
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+ if (!rk_rng)
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+ return -ENOMEM;
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+
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++ rk_rng->soc_data = of_device_get_match_data(dev);
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+ rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(rk_rng->base))
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+ return PTR_ERR(rk_rng->base);
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+@@ -148,24 +334,30 @@ static int rk_rng_probe(struct platform_
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+ return dev_err_probe(dev, rk_rng->clk_num,
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+ "Failed to get clks property\n");
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+
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+- rst = devm_reset_control_array_get_exclusive(dev);
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|
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+- if (IS_ERR(rst))
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+- return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n");
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+-
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+- reset_control_assert(rst);
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+- udelay(2);
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+- reset_control_deassert(rst);
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++ if (rk_rng->soc_data->reset_optional)
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++ rst = devm_reset_control_array_get_optional_exclusive(dev);
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|
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++ else
|
|
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++ rst = devm_reset_control_array_get_exclusive(dev);
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++
|
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++ if (rst) {
|
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++ if (IS_ERR(rst))
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|
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++ return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n");
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|
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++
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++ reset_control_assert(rst);
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++ udelay(2);
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++ reset_control_deassert(rst);
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|
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++ }
|
|
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+
|
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+ platform_set_drvdata(pdev, rk_rng);
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|
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+
|
|
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+ rk_rng->rng.name = dev_driver_string(dev);
|
|
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+ if (!IS_ENABLED(CONFIG_PM)) {
|
|
|
+- rk_rng->rng.init = rk_rng_init;
|
|
|
+- rk_rng->rng.cleanup = rk_rng_cleanup;
|
|
|
++ rk_rng->rng.init = rk_rng->soc_data->rk_rng_init;
|
|
|
++ rk_rng->rng.cleanup = rk_rng->soc_data->rk_rng_cleanup;
|
|
|
+ }
|
|
|
+- rk_rng->rng.read = rk_rng_read;
|
|
|
++ rk_rng->rng.read = rk_rng->soc_data->rk_rng_read;
|
|
|
+ rk_rng->dev = dev;
|
|
|
+- rk_rng->rng.quality = 900;
|
|
|
++ rk_rng->rng.quality = rk_rng->soc_data->quality;
|
|
|
+
|
|
|
+ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
|
|
|
+ pm_runtime_use_autosuspend(dev);
|
|
|
+@@ -184,7 +376,7 @@ static int __maybe_unused rk_rng_runtime
|
|
|
+ {
|
|
|
+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
|
|
+
|
|
|
+- rk_rng_cleanup(&rk_rng->rng);
|
|
|
++ rk_rng->soc_data->rk_rng_cleanup(&rk_rng->rng);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+@@ -193,7 +385,7 @@ static int __maybe_unused rk_rng_runtime
|
|
|
+ {
|
|
|
+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
|
|
+
|
|
|
+- return rk_rng_init(&rk_rng->rng);
|
|
|
++ return rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
|
|
|
+ }
|
|
|
+
|
|
|
+ static const struct dev_pm_ops rk_rng_pm_ops = {
|
|
|
+@@ -204,7 +396,8 @@ static const struct dev_pm_ops rk_rng_pm
|
|
|
+ };
|
|
|
+
|
|
|
+ static const struct of_device_id rk_rng_dt_match[] = {
|
|
|
+- { .compatible = "rockchip,rk3568-rng", },
|
|
|
++ { .compatible = "rockchip,rk3568-rng", .data = (void *)&rk3568_soc_data },
|
|
|
++ { .compatible = "rockchip,rk3588-rng", .data = (void *)&rk3588_soc_data },
|
|
|
+ { /* sentinel */ },
|
|
|
+ };
|
|
|
+
|
|
|
+@@ -221,8 +414,9 @@ static struct platform_driver rk_rng_dri
|
|
|
+
|
|
|
+ module_platform_driver(rk_rng_driver);
|
|
|
+
|
|
|
+-MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver");
|
|
|
++MODULE_DESCRIPTION("Rockchip True Random Number Generator driver");
|
|
|
+ MODULE_AUTHOR("Lin Jinhan <[email protected]>");
|
|
|
+ MODULE_AUTHOR("Aurelien Jarno <[email protected]>");
|
|
|
+ MODULE_AUTHOR("Daniel Golle <[email protected]>");
|
|
|
++MODULE_AUTHOR("Nicolas Frattaroli <[email protected]>");
|
|
|
+ MODULE_LICENSE("GPL");
|
Marty Jones