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@@ -0,0 +1,34 @@
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+[PATCH] MIPS: BCM63XX: fix BCM6345 clock bits shifting
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+
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+BCM6345 has an intermediate 16-bits wide test control register between the
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+peripheral identifier function, and its clock control register is only 16-bits
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+wide contrary to other platforms where it is 32-bits wide. By shifting all
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+clocks bits by 16-bits to the left we ensure they get written to the proper
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+clock control register, without adding specific BCM6345 handling in the clock
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+code.
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+
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+Signed-off-by: Florian Fainelli <[email protected]>
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+---
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+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+@@ -53,13 +53,13 @@
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+ CKCTL_6338_SAR_EN | \
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+ CKCTL_6338_SPI_EN)
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+
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+-#define CKCTL_6345_CPU_EN (1 << 0)
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+-#define CKCTL_6345_BUS_EN (1 << 1)
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+-#define CKCTL_6345_EBI_EN (1 << 2)
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+-#define CKCTL_6345_UART_EN (1 << 3)
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+-#define CKCTL_6345_ADSLPHY_EN (1 << 4)
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+-#define CKCTL_6345_ENET_EN (1 << 7)
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+-#define CKCTL_6345_USBH_EN (1 << 8)
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++#define CKCTL_6345_CPU_EN (1 << 16)
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++#define CKCTL_6345_BUS_EN (1 << 17)
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++#define CKCTL_6345_EBI_EN (1 << 18)
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++#define CKCTL_6345_UART_EN (1 << 19)
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++#define CKCTL_6345_ADSLPHY_EN (1 << 20)
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++#define CKCTL_6345_ENET_EN (1 << 23)
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++#define CKCTL_6345_USBH_EN (1 << 24)
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+
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+ #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
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+ CKCTL_6345_USBH_EN | \
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Florian Fainelli