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@@ -0,0 +1,312 @@
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+Index: madwifi-dfs-r2996/ath_hal/ah_os.h
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+===================================================================
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+--- madwifi-dfs-r2996.orig/ath_hal/ah_os.h 2007-12-01 19:36:04.943396719 +0100
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++++ madwifi-dfs-r2996/ath_hal/ah_os.h 2007-12-01 19:37:06.182886560 +0100
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+@@ -33,7 +33,7 @@
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+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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+ * THE POSSIBILITY OF SUCH DAMAGES.
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+ *
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+- * $Id: ah_os.h 2727 2007-10-05 17:42:53Z mtaylor $
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++ * $Id: ah_os.h 2933 2007-11-23 09:38:18Z proski $
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+ */
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+ #ifndef _ATH_AH_OS_H_
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+ #define _ATH_AH_OS_H_
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+@@ -42,16 +42,16 @@
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+ * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
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+ */
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+
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+-/*
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+-MadWifi safe register operations:
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++/*
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++ MadWifi safe register operations:
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+
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+- When hacking on registers directly we need to use the macros
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+- below, to avoid concurrent PCI access and abort mode errors.
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++ When hacking on registers directly, we need to use the macros below to
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++ avoid concurrent PCI access and abort mode errors.
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+
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+ * ath_reg_read
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+ * ATH_REG_WRITE
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+
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+-HAL-ONLY register operations:
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++ HAL-ONLY register operations:
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+
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+ * _OS_REG_READ
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+ * _OS_REG_WRITE
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+@@ -60,26 +60,27 @@
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+ * ath_hal_reg_read.
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+ * ath_hal_reg_write
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+
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+- When compiled in HAL:
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+- * We do not require locking overhead and function call unless user is debugging.
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+- * All HAL operations are executed in the context of a MadWifi wrapper call which holds
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+- the HAL lock.
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+- * Normally HAL is build with the non-modified version of this file so it doesnt have our
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+- funny macros anyway.
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+-
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+- When compiled in MadWifi:
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+- * The HAL wrapper API takes the HAL lock before invoking the HAL.
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+- * HAL access is already protected, and MadWifi must NOT access the functions listed above.
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+-
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++ When compiled in HAL:
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++ * We don't require locking overhead and function call except for
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++ debugging.
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++ * All HAL operations are executed in the context of a MadWifi wrapper
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++ call that holds the HAL lock.
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++ * Normally HAL is built with the non-modified version of this file, so
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++ it doesn't have our funny macros anyway.
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++
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++ When compiled in MadWifi:
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++ * The HAL wrapper API takes the HAL lock before invoking the HAL.
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++ * HAL access is already protected, and MadWifi must NOT access the
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++ functions listed above.
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+ */
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+
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+ /*
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+- * When building the HAL proper we use no GPL-contaminated include
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+- * files and must define these types ourself. Beware of these being
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+- * mismatched against the contents of <linux/types.h>
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++ * When building the HAL proper, we use no GPL-licensed include files and must
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++ * define Linux types ourselves. Please note that the definitions below don't
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++ * exactly match those in <linux/types.h>
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+ */
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+ #ifndef _LINUX_TYPES_H
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+-/* NB: arm defaults to unsigned so be explicit */
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++/* NB: ARM defaults to unsigned, so be explicit */
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+ typedef signed char int8_t;
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+ typedef short int16_t;
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+ typedef int int32_t;
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+@@ -93,36 +94,33 @@
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+ typedef unsigned int size_t;
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+ typedef unsigned int u_int;
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+ typedef void* va_list;
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+-#endif
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++#endif /* !_LINUX_TYPES_H */
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+
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+ /*
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+ * Linux/BSD gcc compatibility shims.
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+ */
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+-#define __printflike(_a,_b) \
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+- __attribute__ ((__format__ (__printf__, _a, _b)))
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+-#define __va_list va_list
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++#define __va_list va_list
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+ #define OS_INLINE __inline
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+
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+ extern int ath_hal_dma_beacon_response_time;
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+ extern int ath_hal_sw_beacon_response_time;
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+ extern int ath_hal_additional_swba_backoff;
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+
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+-void __ahdecl ath_hal_vprintf(struct ath_hal *ah, const char* fmt,
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+- va_list ap);
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+-void __ahdecl ath_hal_printf(struct ath_hal *ah, const char* fmt, ...);
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+-const char* __ahdecl ath_hal_ether_sprintf(const u_int8_t *mac);
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++void __ahdecl ath_hal_vprintf(struct ath_hal *ah, const char *fmt, va_list ap);
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++void __ahdecl ath_hal_printf(struct ath_hal *ah, const char *fmt, ...);
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++const char *__ahdecl ath_hal_ether_sprintf(const u_int8_t *mac);
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+ int __ahdecl ath_hal_memcmp(const void *a, const void *b, size_t n);
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+-void * __ahdecl ath_hal_malloc(size_t size);
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+-void __ahdecl ath_hal_free(void* p);
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++void *__ahdecl ath_hal_malloc(size_t size);
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++void __ahdecl ath_hal_free(void *p);
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+
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+ /* Delay n microseconds. */
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+-extern void __ahdecl ath_hal_delay(int);
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++extern void __ahdecl ath_hal_delay(int);
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+ #define OS_DELAY(_n) ath_hal_delay(_n)
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+
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+ #define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n))
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+ extern void __ahdecl ath_hal_memzero(void *, size_t);
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+ #define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
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+-extern void * __ahdecl ath_hal_memcpy(void *, const void *, size_t);
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++extern void *__ahdecl ath_hal_memcpy(void *, const void *, size_t);
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+
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+ #ifndef abs
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+ #define abs(_a) __builtin_abs(_a)
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+@@ -133,7 +131,7 @@
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+ #endif
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+
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+ struct ath_hal;
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+-extern u_int32_t __ahdecl ath_hal_getuptime(struct ath_hal *);
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++extern u_int32_t __ahdecl ath_hal_getuptime(struct ath_hal *);
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+ #define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
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+
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+ /* Byte order/swapping support. */
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+@@ -142,9 +140,8 @@
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+
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+ #ifndef AH_BYTE_ORDER
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+ /*
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+- * When the .inc file is not available (e.g. when building
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+- * in a kernel source tree); look for some other way to
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+- * setup the host byte order.
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++ * When the .inc file is not available (e.g. when building in the kernel source
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++ * tree), look for some other way to determine the host byte order.
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+ */
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+ #ifdef __LITTLE_ENDIAN
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+ #define AH_BYTE_ORDER AH_LITTLE_ENDIAN
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+@@ -155,93 +152,98 @@
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+ #ifndef AH_BYTE_ORDER
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+ #error "Do not know host byte order"
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+ #endif
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+-#endif /* AH_BYTE_ORDER */
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++#endif /* AH_BYTE_ORDER */
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+
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+ /*
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+- * Note that register accesses are done using target-specific
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+- * functions when debugging is enabled (AH_DEBUG) or we are
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+- * explicitly configured this way.
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+- *
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+- * The hardware registers are native little-endian byte order.
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+- * Big-endian hosts are handled by enabling hardware byte-swap
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+- * of register reads and writes at reset. But the PCI clock
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+- * domain registers are not byte swapped! Thus, on big-endian
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+- * platforms we have to byte-swap thoese registers specifically.
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+- * Most of this code is collapsed at compile time because the
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+- * register values are constants.
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+- *
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+- * Presumably when talking about hardware byte-swapping, the above
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+- * text is referring to the Atheros chipset, as the registers
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+- * referred to are in the PCI memory address space, and these are
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+- * never byte-swapped by PCI chipsets or bridges, but always
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+- * written directly (i.e. the format defined by the manufacturer).
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++ * Some big-endian architectures don't set CONFIG_GENERIC_IOMAP, but fail to
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++ * implement iowrite32be and ioread32be. Provide compatibility macros when
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++ * it's needed.
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++ *
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++ * As of Linux 2.6.24, only MIPS, PARISC and PowerPC implement iowrite32be and
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++ * ioread32be as functions.
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++ *
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++ * The downside or the replacement macros it that we may be byte-swapping data
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++ * for the second time, so the native implementations should be preferred.
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+ */
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++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)) && \
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++ !defined(CONFIG_GENERIC_IOMAP) && (AH_BYTE_ORDER == AH_BIG_ENDIAN) && \
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++ !defined(__mips__) && !defined(__hppa__) && !defined(__powerpc__)
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++# ifndef iowrite32be
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++# define iowrite32be(_val, _addr) iowrite32(swab32((_val)), (_addr))
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++# endif
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++# ifndef ioread32be
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++# define ioread32be(_addr) swab32(ioread32((_addr)))
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++# endif
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++#endif
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++
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++/*
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++ * The register accesses are done using target-specific functions when
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++ * debugging is enabled (AH_DEBUG) or it's explicitly requested for the target.
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++ *
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++ * The hardware registers use little-endian byte order natively. Big-endian
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++ * systems are configured by HAL to enable hardware byte-swap of register reads
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++ * and writes at reset. This avoid the need to byte-swap the data in software.
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++ * However, the registers in a certain area from 0x4000 to 0x4fff (PCI clock
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++ * domain registers) are not byte swapped!
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++ *
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++ * Since Linux I/O primitives default to little-endian operations, we only
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++ * need to suppress byte-swapping on big-endian systems outside the area used
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++ * by the PCI clock domain registers.
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++ */
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++#if (AH_BYTE_ORDER == AH_BIG_ENDIAN)
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++#define is_reg_le(__reg) ((0x4000 <= (__reg) && (__reg) < 0x5000))
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++#else
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++#define is_reg_le(__reg) 1
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++#endif
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++
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+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)
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+-# if (AH_BYTE_ORDER == AH_BIG_ENDIAN)
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+ #define _OS_REG_WRITE(_ah, _reg, _val) do { \
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+- (0x4000 <= (_reg) && (_reg) < 0x5000) ? \
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++ is_reg_le(_reg) ? \
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+ iowrite32((_val), (_ah)->ah_sh + (_reg)) : \
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+ iowrite32be((_val), (_ah)->ah_sh + (_reg)); \
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+ } while (0)
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+ #define _OS_REG_READ(_ah, _reg) \
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+- ((0x4000 <= (_reg) && (_reg) < 0x5000) ? \
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++ (is_reg_le(_reg) ? \
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+ ioread32((_ah)->ah_sh + (_reg)) : \
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+- ioread32be((_ah)->ah_sh + (_reg)));
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+-# else /* AH_LITTLE_ENDIAN */
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+-#define _OS_REG_WRITE(_ah, _reg, _val) do { \
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+- iowrite32(_val, (_ah)->ah_sh + (_reg)); \
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+- } while (0)
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+-#define _OS_REG_READ(_ah, _reg) \
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+- ioread32((_ah)->ah_sh + (_reg))
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+-
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+-# endif /* AH_BYTE_ORDER */
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++ ioread32be((_ah)->ah_sh + (_reg)))
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+ #else
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+-# if (AH_BYTE_ORDER == AH_BIG_ENDIAN)
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+ #define _OS_REG_WRITE(_ah, _reg, _val) do { \
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+- writel((0x4000 <= (_reg) && (_reg) < 0x5000) ? \
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++ writel(is_reg_le(_reg) ? \
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+ (_val) : cpu_to_le32(_val), \
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+ (_ah)->ah_sh + (_reg)); \
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+ } while (0)
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+ #define _OS_REG_READ(_ah, _reg) \
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+- ((0x4000 <= (_reg) && (_reg) < 0x5000) ? \
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++ (is_reg_le(_reg) ? \
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+ readl((_ah)->ah_sh + (_reg)) : \
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+ cpu_to_le32(readl((_ah)->ah_sh + (_reg))))
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+-# else /* AH_LITTLE_ENDIAN */
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+-#define _OS_REG_WRITE(_ah, _reg, _val) do { \
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+- writel(_val, (_ah)->ah_sh + (_reg)); \
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+- } while (0)
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+-#define _OS_REG_READ(_ah, _reg) \
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+- readl((_ah)->ah_sh + (_reg))
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+-# endif /* AH_BYTE_ORDER */
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+-#endif /* KERNEL_VERSON(2,6,12) */
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+-
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+-/*
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+-The functions in this section are not intended to be invoked by MadWifi driver
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+-code, but by the HAL. They are NOT safe for direct invocation when the
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+-sc->sc_hal_lock is not held. Use ath_reg_read and ATH_REG_WRITE instead!
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++#endif /* KERNEL_VERSION(2,6,12) */
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++
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++/*
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++ * The functions in this section are not intended to be invoked by MadWifi
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++ * driver code, but by the HAL. They are NOT safe to call directly when the
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++ * sc->sc_hal_lock is not held. Use ath_reg_read and ATH_REG_WRITE instead!
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+ */
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+ #if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
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+ #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
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+ #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
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+-extern void __ahdecl ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
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+-extern u_int32_t __ahdecl ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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++extern void __ahdecl ath_hal_reg_write(struct ath_hal *ah, u_int reg,
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++ u_int32_t val);
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++extern u_int32_t __ahdecl ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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+ #else
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+ #define OS_REG_WRITE(_ah, _reg, _val) _OS_REG_WRITE(_ah, _reg, _val)
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+ #define OS_REG_READ(_ah, _reg) _OS_REG_READ(_ah, _reg)
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+-#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
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++#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
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+
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+ extern char *ath_hal_func;
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+ static inline void ath_hal_set_function(const char *name)
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+-#if defined(AH_DEBUG)
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+ {
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++#ifdef AH_DEBUG
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+ ath_hal_func = (char *)name;
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+-}
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+-#else
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+-{ }
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+ #endif
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++}
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+
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+ #ifdef AH_DEBUG_ALQ
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+-extern void __ahdecl OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
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++extern void __ahdecl OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
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+ #else
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+ #define OS_MARK(_ah, _id, _v)
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+ #endif
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+@@ -253,8 +255,9 @@
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+ * compiled with the default calling convention and are not called
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+ * from within the HAL.
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+ */
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+-extern struct ath_hal *_ath_hal_attach(u_int16_t devid, HAL_SOFTC,
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+- HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS*);
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+-extern void _ath_hal_detach(struct ath_hal *);
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++extern struct ath_hal *_ath_hal_attach(u_int16_t devid, HAL_SOFTC,
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++ HAL_BUS_TAG, HAL_BUS_HANDLE,
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++ HAL_STATUS *);
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++extern void _ath_hal_detach(struct ath_hal *);
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+
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+-#endif /* _ATH_AH_OSDEP_H_ */
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++#endif /* _ATH_AH_OSDEP_H_ */
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Felix Fietkau