qualcommbe: ipq95xx: Backport cpufreq patch and enable RPM

Backport CPUFreq patch and enable RPM. This is to enable CPU Frequency
scaling and regulators.

Link: https://github.com/openwrt/openwrt/pull/17725
Signed-off-by: Christian Marangi <[email protected]>

target/linux/qualcommbe/ipq95xx/config-default

@@ -46,3 +46,15 @@ CONFIG_QCOM_PPE=y
 CONFIG_QCOM_IPA=y
 CONFIG_INTERCONNECT_QCOM=y
 CONFIG_INTERCONNECT_QCOM_OSM_L3=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_REGULATOR_QCOM_SMD_RPM=y
+# CONFIG_QCOM_CLK_SMD_RPM is not set
+# CONFIG_QCOM_RPMPD is not set
+# CONFIG_INTERCONNECT_QCOM_MSM8916 is not set
+# CONFIG_INTERCONNECT_QCOM_MSM8939 is not set
+# CONFIG_INTERCONNECT_QCOM_MSM8996 is not set
+# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set
+# CONFIG_INTERCONNECT_QCOM_QCM2290 is not set
+# CONFIG_INTERCONNECT_QCOM_QCS404 is not set
+# CONFIG_INTERCONNECT_QCOM_SDM660 is not set

target/linux/qualcommbe/patches-6.6/013-01-v6.7-cpufreq-qcom-nvmem-Enable-cpufreq-for-ipq53xx.patch

@@ -0,0 +1,68 @@
+From ba5a61a08d83b18b99c461b4ddb9009947a4aa0e Mon Sep 17 00:00:00 2001
+From: Varadarajan Narayanan <[email protected]>
+Date: Tue, 31 Oct 2023 12:41:38 +0530
+Subject: [PATCH 1/2] cpufreq: qcom-nvmem: Enable cpufreq for ipq53xx
+
+IPQ53xx have different OPPs available for the CPU based on
+SoC variant. This can be determined through use of an eFuse
+register present in the silicon.
+
+Added support for ipq53xx on nvmem driver which helps to
+determine OPPs at runtime based on the eFuse register which
+has the CPU frequency limits. opp-supported-hw dt binding
+can be used to indicate the available OPPs for each limit.
+
+nvmem driver also creates the "cpufreq-dt" platform_device after
+passing the version matching data to the OPP framework so that the
+cpufreq-dt handles the actual cpufreq implementation.
+
+Reviewed-by: Dmitry Baryshkov <[email protected]>
+Reviewed-by: Bryan O'Donoghue <[email protected]>
+Signed-off-by: Kathiravan T <[email protected]>
+Signed-off-by: Varadarajan Narayanan <[email protected]>
+[ Viresh: Fixed subject ]
+Signed-off-by: Viresh Kumar <[email protected]>
+---
+ drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
+ drivers/cpufreq/qcom-cpufreq-nvmem.c | 6 ++++++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
+index 07181913448f..53da25589e5f 100644
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -180,6 +180,7 @@ static const struct of_device_id blocklist[] __initconst = {
+ 	{ .compatible = "ti,am62a7", },
+ 	{ .compatible = "ti,am62p5", },
+ 
++	{ .compatible = "qcom,ipq5332", },
+ 	{ .compatible = "qcom,ipq8064", },
+ 	{ .compatible = "qcom,apq8064", },
+ 	{ .compatible = "qcom,msm8974", },
+diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+index 158c0e139185..4f7af70169e0 100644
+--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+@@ -183,6 +183,11 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
+ 	switch (msm_id) {
+ 	case QCOM_ID_MSM8996:
+ 	case QCOM_ID_APQ8096:
++	case QCOM_ID_IPQ5332:
++	case QCOM_ID_IPQ5322:
++	case QCOM_ID_IPQ5312:
++	case QCOM_ID_IPQ5302:
++	case QCOM_ID_IPQ5300:
+ 		drv->versions = 1 << (unsigned int)(*speedbin);
+ 		break;
+ 	case QCOM_ID_MSM8996SG:
+@@ -541,6 +546,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
+ 	{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
+ 	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
+ 	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
++	{ .compatible = "qcom,ipq5332", .data = &match_data_kryo },
+ 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ 	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
+ 	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
+-- 
+2.45.2
+

target/linux/qualcommbe/patches-6.6/013-02-v6.7-v6.8-cpufreq-qcom-nvmem-Introduce-cpufreq-for-ipq95xx.patch

@@ -0,0 +1,64 @@
+From 5b5b5806f22390808b8e8fa180fe35b003a4a74d Mon Sep 17 00:00:00 2001
+From: Varadarajan Narayanan <[email protected]>
+Date: Tue, 31 Oct 2023 12:41:39 +0530
+Subject: [PATCH 2/2] cpufreq: qcom-nvmem: Introduce cpufreq for ipq95xx
+
+IPQ95xx SoCs have different OPPs available for the CPU based on
+the SoC variant. This can be determined from an eFuse register
+present in the silicon.
+
+Added support for ipq95xx on nvmem driver which helps to
+determine OPPs at runtime based on the eFuse register which
+has the CPU frequency limits. opp-supported-hw dt binding
+can be used to indicate the available OPPs for each limit.
+
+Reviewed-by: Dmitry Baryshkov <[email protected]>
+Signed-off-by: Praveenkumar I <[email protected]>
+Signed-off-by: Kathiravan T <[email protected]>
+Signed-off-by: Varadarajan Narayanan <[email protected]>
+[ Viresh: Fixed subject ]
+Signed-off-by: Viresh Kumar <[email protected]>
+---
+ drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
+ drivers/cpufreq/qcom-cpufreq-nvmem.c | 6 ++++++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
+index 53da25589e5f..bd1e1357cef8 100644
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -184,6 +184,7 @@ static const struct of_device_id blocklist[] __initconst = {
+ 
+	{ .compatible = "qcom,ipq5332", },
+ 	{ .compatible = "qcom,ipq8064", },
++	{ .compatible = "qcom,ipq9574", },
+ 	{ .compatible = "qcom,apq8064", },
+ 	{ .compatible = "qcom,msm8974", },
+ 	{ .compatible = "qcom,msm8960", },
+diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+index 4f7af70169e0..6355a39418c5 100644
+--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+@@ -188,6 +188,11 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
+ 	case QCOM_ID_IPQ5312:
+ 	case QCOM_ID_IPQ5302:
+ 	case QCOM_ID_IPQ5300:
++	case QCOM_ID_IPQ9514:
++	case QCOM_ID_IPQ9550:
++	case QCOM_ID_IPQ9554:
++	case QCOM_ID_IPQ9570:
++	case QCOM_ID_IPQ9574:
+ 		drv->versions = 1 << (unsigned int)(*speedbin);
+ 		break;
+ 	case QCOM_ID_MSM8996SG:
+@@ -551,6 +556,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
+ 	{ .compatible = "qcom,ipq5332", .data = &match_data_kryo },
+ 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ 	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
++	{ .compatible = "qcom,ipq9574", .data = &match_data_kryo },
+ 	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
+ 	{ .compatible = "qcom,msm8960", .data = &match_data_krait },
+ 	{},
+-- 
+2.45.2
+

target/linux/qualcommbe/patches-6.6/014-v6.8-arm64-dts-qcom-ipq9574-populate-the-opp-table-based-.patch

@@ -0,0 +1,110 @@
+From b36074357baf2794c825ea1c145de1d22b15380b Mon Sep 17 00:00:00 2001
+From: Varadarajan Narayanan <[email protected]>
+Date: Fri, 20 Oct 2023 11:49:39 +0530
+Subject: [PATCH] arm64: dts: qcom: ipq9574: populate the opp table based on
+ the eFuse
+
+IPQ95xx SoCs have different OPPs available for the CPU based on
+SoC variant. This can be determined from an eFuse register
+present in the silicon.
+
+Add support to read the eFuse and populate the OPPs based on it.
+
+Frequency	1.2GHz	1.8GHz	1.5GHz	No	opp-supported-hw
+					Limit
+------------------------------------------------------------
+936000000	1	1	1	1	0xf
+1104000000	1	1	1	1	0xf
+1200000000	1	1	1	1	0xf
+1416000000	0	1	1	1	0x7
+1488000000	0	1	1	1	0x7
+1800000000	0	1	0	1	0x5
+2208000000	0	0	0	1	0x1
+-----------------------------------------------------------
+
+Reviewed-by: Konrad Dybcio <[email protected]>
+Signed-off-by: Kathiravan T <[email protected]>
+Signed-off-by: Varadarajan Narayanan <[email protected]>
+Link: https://lore.kernel.org/r/14ab08b7cfd904433ca6065fac798d4f221c9d95.1697781921.git.quic_varada@quicinc.com
+Signed-off-by: Bjorn Andersson <[email protected]>
+---
+ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 21 ++++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+index 8a72ad4afd03..d4b7e215fc92 100644
+--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+@@ -106,42 +106,56 @@ memory@40000000 {
+ 	};
+ 
+ 	cpu_opp_table: opp-table-cpu {
+-		compatible = "operating-points-v2";
++		compatible = "operating-points-v2-kryo-cpu";
+ 		opp-shared;
++		nvmem-cells = <&cpu_speed_bin>;
+ 
+ 		opp-936000000 {
+ 			opp-hz = /bits/ 64 <936000000>;
+ 			opp-microvolt = <725000>;
++			opp-supported-hw = <0xf>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1104000000 {
+ 			opp-hz = /bits/ 64 <1104000000>;
+ 			opp-microvolt = <787500>;
++			opp-supported-hw = <0xf>;
++			clock-latency-ns = <200000>;
++		};
++
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <862500>;
++			opp-supported-hw = <0xf>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1416000000 {
+ 			opp-hz = /bits/ 64 <1416000000>;
+ 			opp-microvolt = <862500>;
++			opp-supported-hw = <0x7>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1488000000 {
+ 			opp-hz = /bits/ 64 <1488000000>;
+ 			opp-microvolt = <925000>;
++			opp-supported-hw = <0x7>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-1800000000 {
+ 			opp-hz = /bits/ 64 <1800000000>;
+ 			opp-microvolt = <987500>;
++			opp-supported-hw = <0x5>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 
+ 		opp-2208000000 {
+ 			opp-hz = /bits/ 64 <2208000000>;
+ 			opp-microvolt = <1062500>;
++			opp-supported-hw = <0x1>;
+ 			clock-latency-ns = <200000>;
+ 		};
+ 	};
+@@ -223,6 +237,11 @@ qfprom: efuse@a4000 {
+ 			reg = <0x000a4000 0x5a1>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
++
++			cpu_speed_bin: cpu-speed-bin@15 {
++				reg = <0x15 0x2>;
++				bits = <7 2>;
++			};
+ 		};
+ 
+ 		cryptobam: dma-controller@704000 {
+-- 
+2.45.2
+