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@@ -1,294 +0,0 @@
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-From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
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-From: John Crispin <[email protected]>
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-Date: Thu, 7 Aug 2014 18:15:36 +0200
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-Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
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-
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-Signed-off-by: John Crispin <[email protected]>
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----
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- drivers/net/phy/Kconfig | 5 +
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- drivers/net/phy/Makefile | 1 +
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- drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++
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- 3 files changed, 237 insertions(+)
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- create mode 100644 drivers/net/phy/lantiq.c
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-
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---- a/drivers/net/phy/intel-xway.c
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-+++ b/drivers/net/phy/intel-xway.c
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-@@ -278,6 +278,51 @@ static int xway_gphy_init_leds(struct ph
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- return 0;
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- }
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-
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-+#if IS_ENABLED(CONFIG_OF_MDIO)
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-+static int vr9_gphy_of_reg_init(struct phy_device *phydev)
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-+{
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-+ u32 tmp;
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-+
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-+ /* store the led values if one was passed by the devicetree */
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-+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp))
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-+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp);
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-+
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-+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp))
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-+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp);
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-+
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-+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp))
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-+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp);
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-+
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-+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp))
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-+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp);
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-+
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-+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp))
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-+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp);
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-+
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-+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp))
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-+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp);
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-+
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-+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp))
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-+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, tmp);
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-+
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-+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp))
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-+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp);
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-+
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-+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp))
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-+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp);
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-+
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-+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp))
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-+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);
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-+
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-+ return 0;
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-+}
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-+#else
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-+static int vr9_gphy_of_reg_init(struct phy_device *phydev)
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-+{
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-+ return 0;
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-+}
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-+#endif /* CONFIG_OF_MDIO */
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-+
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- static int xway_gphy_config_init(struct phy_device *phydev)
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- {
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- struct device_node *np = phydev->mdio.dev.of_node;
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-@@ -299,6 +344,7 @@ static int xway_gphy_config_init(struct
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- if (err)
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- return err;
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-
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-+ vr9_gphy_of_reg_init(phydev);
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- return 0;
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- }
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-
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---- /dev/null
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-+++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt
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-@@ -0,0 +1,216 @@
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-+Lanitq PHY binding
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-+============================================
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-+
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-+This devicetree binding controls the lantiq ethernet phys led functionality.
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-+
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-+Example:
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-+ mdio@0 {
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-+ #address-cells = <1>;
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-+ #size-cells = <0>;
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-+ compatible = "lantiq,xrx200-mdio";
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-+ phy5: ethernet-phy@5 {
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-+ reg = <0x1>;
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-+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
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-+ };
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-+ phy11: ethernet-phy@11 {
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-+ reg = <0x11>;
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-+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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-+ lantiq,led2h = <0x00>;
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-+ lantiq,led2l = <0x03>;
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-+ };
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-+ phy12: ethernet-phy@12 {
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-+ reg = <0x12>;
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-+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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-+ lantiq,led1h = <0x00>;
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-+ lantiq,led1l = <0x03>;
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-+ };
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-+ phy13: ethernet-phy@13 {
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-+ reg = <0x13>;
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-+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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-+ lantiq,led2h = <0x00>;
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-+ lantiq,led2l = <0x03>;
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-+ };
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-+ phy14: ethernet-phy@14 {
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-+ reg = <0x14>;
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-+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
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-+ lantiq,led1h = <0x00>;
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-+ lantiq,led1l = <0x03>;
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-+ };
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-+ };
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-+
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-+Register Description
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-+============================================
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-+
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-+LEDCH:
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-+
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-+Name Hardware Reset Value
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-+LEDCH 0x00C5
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-+
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-+| 15 | | | | | | | 8 |
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-+=========================================
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-+| RES |
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-+=========================================
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-+
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-+| 7 | | | | | | | 0 |
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-+=========================================
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-+| FBF | SBF |RES | NACS |
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-+=========================================
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-+
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-+Field Bits Type Description
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-+FBF 7:6 RW Fast Blink Frequency
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-+ ---
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-+ 0x0 (00b) F02HZ 2 Hz blinking frequency
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-+ 0x1 (01b) F04HZ 4 Hz blinking frequency
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-+ 0x2 (10b) F08HZ 8 Hz blinking frequency
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-+ 0x3 (11b) F16HZ 16 Hz blinking frequency
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-+
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-+SBF 5:4 RW Slow Blink Frequency
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-+ ---
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-+ 0x0 (00b) F02HZ 2 Hz blinking frequency
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-+ 0x1 (01b) F04HZ 4 Hz blinking frequency
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-+ 0x2 (10b) F08HZ 8 Hz blinking frequency
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-+ 0x3 (11b) F16HZ 16 Hz blinking frequency
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-+
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-+NACS 2:0 RW Inverse of Scan Function
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-+ ---
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-+ 0x0 (000b) NONE No Function
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-+ 0x1 (001b) LINK Complex function enabled when link is up
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-+ 0x2 (010b) PDOWN Complex function enabled when device is powered-down
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-+ 0x3 (011b) EEE Complex function enabled when device is in EEE mode
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-+ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running
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-+ 0x5 (101b) ABIST Complex function enabled when analog self-test is running
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-+ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running
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-+ 0x7 (111b) TEST Complex function enabled when test mode is running
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-+
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-+LEDCL:
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-+
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-+Name Hardware Reset Value
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-+LEDCL 0x0067
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-+
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-+| 15 | | | | | | | 8 |
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-+=========================================
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-+| RES |
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-+=========================================
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-+
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-+| 7 | | | | | | | 0 |
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-+=========================================
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-+|RES | SCAN |RES | CBLINK |
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-+=========================================
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-+
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-+Field Bits Type Description
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-+SCAN 6:4 RW Complex Scan Configuration
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-+ ---
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-+ 000 B NONE No Function
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-+ 001 B LINK Complex function enabled when link is up
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-+ 010 B PDOWN Complex function enabled when device is powered-down
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-+ 011 B EEE Complex function enabled when device is in EEE mode
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-+ 100 B ANEG Complex function enabled when auto-negotiation is running
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-+ 101 B ABIST Complex function enabled when analog self-test is running
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-+ 110 B CDIAG Complex function enabled when cable diagnostics are running
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-+ 111 B TEST Complex function enabled when test mode is running
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-+
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-+CBLINK 2:0 RW Complex Blinking Configuration
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-+ ---
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-+ 000 B NONE No Function
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-+ 001 B LINK Complex function enabled when link is up
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-+ 010 B PDOWN Complex function enabled when device is powered-down
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-+ 011 B EEE Complex function enabled when device is in EEE mode
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-+ 100 B ANEG Complex function enabled when auto-negotiation is running
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-+ 101 B ABIST Complex function enabled when analog self-test is running
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-+ 110 B CDIAG Complex function enabled when cable diagnostics are running
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-+ 111 B TEST Complex function enabled when test mode is running
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-+
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-+LEDxH:
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-+
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-+Name Hardware Reset Value
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-+LED0H 0x0070
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-+LED1H 0x0020
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-+LED2H 0x0040
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-+LED3H 0x0040
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-+
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-+| 15 | | | | | | | 8 |
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-+=========================================
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-+| RES |
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-+=========================================
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-+
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-+| 7 | | | | | | | 0 |
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-+=========================================
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-+| CON | BLINKF |
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-+=========================================
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-+
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-+Field Bits Type Description
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-+CON 7:4 RW Constant On Configuration
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-+ ---
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-+ 0x0 (0000b) NONE LED does not light up constantly
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-+ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s
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-+ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s
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-+ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s
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-+ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s
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-+ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s
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-+ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s
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-+ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s
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-+ 0x8 (1000b) PDOWN LED is on when device is powered-down
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-+ 0x9 (1001b) EEE LED is on when device is in EEE mode
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-+ 0xA (1010b) ANEG LED is on when auto-negotiation is running
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-+ 0xB (1011b) ABIST LED is on when analog self-test is running
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-+ 0xC (1100b) CDIAG LED is on when cable diagnostics are running
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-+
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-+BLINKF 3:0 RW Fast Blinking Configuration
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-+ ---
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-+ 0x0 (0000b) NONE No Blinking
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-+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
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-+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
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-+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
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-+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
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-+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
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-+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
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-+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
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-+ 0x8 (1000b) PDOWN Blink when device is powered-down
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-+ 0x9 (1001b) EEE Blink when device is in EEE mode
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-+ 0xA (1010b) ANEG Blink when auto-negotiation is running
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-+ 0xB (1011b) ABIST Blink when analog self-test is running
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-+ 0xC (1100b) CDIAG Blink when cable diagnostics are running
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-+
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-+LEDxL:
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-+
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-+Name Hardware Reset Value
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-+LED0L 0x0003
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-+LED1L 0x0000
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-+LED2L 0x0000
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-+LED3L 0x0020
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-+
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-+| 15 | | | | | | | 8 |
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-+=========================================
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-+| RES |
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-+=========================================
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-+
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-+| 7 | | | | | | | 0 |
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-+=========================================
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-+| BLINKS | PULSE |
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-+=========================================
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-+
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-+Field Bits Type Description
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-+BLINKS 7:4 RW Slow Blinkin Configuration
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-+ ---
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-+ 0x0 (0000b) NONE No Blinking
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-+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
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-+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
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-+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
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-+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
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-+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
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-+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
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-+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
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-+ 0x8 (1000b) PDOWN Blink when device is powered-down
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-+ 0x9 (1001b) EEE Blink when device is in EEE mode
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-+ 0xA (1010b) ANEG Blink when auto-negotiation is running
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-+ 0xB (1011b) ABIST Blink when analog self-test is running
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-+ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning
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-+
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-+PULSE 3:0 RW Pulsing Configuration
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-+ The pulse field is a mask field by which certain events can be combined
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-+ ---
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-+ 0x0 (0000b) NONE No pulsing
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-+ 0x1 (0001b) TXACT Transmit activity
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-+ 0x2 (0010b) RXACT Receive activity
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-+ 0x4 (0100b) COL Collision
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-+ 0x8 (1000b) RES Reserved
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