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@@ -1,7 +1,7 @@
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-From a34c288f7214637f214ec17fb2b35dd5d20b0634 Mon Sep 17 00:00:00 2001
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+From b7dcb460c4c441ce52b3c5ce30d65e1ecfbb30ad Mon Sep 17 00:00:00 2001
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From: Ivo van Doorn <[email protected]>
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-Date: Sat, 14 Mar 2009 20:41:58 +0100
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-Subject: [PATCH] rt2x00: Implement support for rt2800pci
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+Date: Sat, 28 Mar 2009 20:46:46 +0100
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+Subject: [PATCH 8/9] rt2x00: Implement support for rt2800pci
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Add support for the rt2800pci chipset.
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@@ -13,18 +13,18 @@ Signed-off-by: Mark Asselstine <[email protected]>
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Signed-off-by: Felix Fietkau <[email protected]>
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Signed-off-by: Ivo van Doorn <[email protected]>
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---
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- drivers/net/wireless/rt2x00/Kconfig | 15 +
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+ drivers/net/wireless/rt2x00/Kconfig | 26 +
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drivers/net/wireless/rt2x00/Makefile | 1 +
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- drivers/net/wireless/rt2x00/rt2800pci.c | 3035 +++++++++++++++++++++++++++++++
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- drivers/net/wireless/rt2x00/rt2800pci.h | 1880 +++++++++++++++++++
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+ drivers/net/wireless/rt2x00/rt2800pci.c | 3244 +++++++++++++++++++++++++++++++
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+ drivers/net/wireless/rt2x00/rt2800pci.h | 1927 ++++++++++++++++++
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drivers/net/wireless/rt2x00/rt2x00.h | 6 +
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- 5 files changed, 4937 insertions(+), 0 deletions(-)
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+ 5 files changed, 5204 insertions(+), 0 deletions(-)
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create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
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create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
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--- a/drivers/net/wireless/rt2x00/Makefile
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+++ b/drivers/net/wireless/rt2x00/Makefile
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-@@ -16,5 +16,6 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
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+@@ -17,5 +17,6 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
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obj-$(CONFIG_RT2400PCI) += rt2400pci.o
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obj-$(CONFIG_RT2500PCI) += rt2500pci.o
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obj-$(CONFIG_RT61PCI) += rt61pci.o
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@@ -33,7 +33,7 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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obj-$(CONFIG_RT73USB) += rt73usb.o
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--- /dev/null
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+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
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-@@ -0,0 +1,3035 @@
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+@@ -0,0 +1,3244 @@
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+/*
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+ Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
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+ <http://rt2x00.serialmonkey.com>
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@@ -72,13 +72,14 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+
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+#include "rt2x00.h"
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+#include "rt2x00pci.h"
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++#include "rt2x00soc.h"
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+#include "rt2800pci.h"
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+
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-+/* FIXME: Make Kconfig dependent */
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-+#ifdef CONFIG_PCI
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++#ifdef CONFIG_RT2800PCI_PCI_MODULE
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+#define CONFIG_RT2800PCI_PCI
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+#endif
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-+#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
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++
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++#ifdef CONFIG_RT2800PCI_WISOC_MODULE
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+#define CONFIG_RT2800PCI_WISOC
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+#endif
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+
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@@ -102,6 +103,8 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ */
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+#define WAIT_FOR_BBP(__dev, __reg) \
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+ rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
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++#define WAIT_FOR_RFCSR(__dev, __reg) \
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++ rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
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+#define WAIT_FOR_RF(__dev, __reg) \
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+ rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
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+#define WAIT_FOR_MCU(__dev, __reg) \
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@@ -165,6 +168,61 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ mutex_unlock(&rt2x00dev->csr_mutex);
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+}
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+
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++static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
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++ const unsigned int word, const u8 value)
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++{
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++ u32 reg;
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++
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++ mutex_lock(&rt2x00dev->csr_mutex);
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++
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++ /*
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++ * Wait until the RFCSR becomes available, afterwards we
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++ * can safely write the new data into the register.
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++ */
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++ if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
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++ reg = 0;
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++ rt2x00_set_field32(®, RF_CSR_CFG_DATA, value);
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++ rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
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++ rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1);
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++ rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
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++
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++ rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
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++ }
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++
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++ mutex_unlock(&rt2x00dev->csr_mutex);
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++}
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++
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++static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
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++ const unsigned int word, u8 *value)
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++{
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++ u32 reg;
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++
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++ mutex_lock(&rt2x00dev->csr_mutex);
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++
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++ /*
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++ * Wait until the RFCSR becomes available, afterwards we
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++ * can safely write the read request into the register.
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++ * After the data has been written, we wait until hardware
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++ * returns the correct value, if at any time the register
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++ * doesn't become available in time, reg will be 0xffffffff
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++ * which means we return 0xff to the caller.
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++ */
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++ if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
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++ reg = 0;
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++ rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
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++ rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0);
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++ rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
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++
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++ rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
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++
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++ WAIT_FOR_RFCSR(rt2x00dev, ®);
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++ }
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++
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++ *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
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++
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++ mutex_unlock(&rt2x00dev->csr_mutex);
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++}
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++
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+static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
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+ const unsigned int word, const u32 value)
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+{
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@@ -196,6 +254,13 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+{
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+ u32 reg;
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+
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++ /*
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++ * RT2880 and RT3052 don't support MCU requests.
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++ */
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++ if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
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++ rt2x00_rt(&rt2x00dev->chip, RT3052))
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++ return;
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++
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+ mutex_lock(&rt2x00dev->csr_mutex);
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+
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+ /*
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@@ -765,13 +830,11 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ rt2x00dev->lna_gain = lna_gain;
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+}
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+
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-+static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
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-+ struct ieee80211_conf *conf,
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-+ struct rf_channel *rf,
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-+ struct channel_info *info)
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++static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
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++ struct ieee80211_conf *conf,
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++ struct rf_channel *rf,
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++ struct channel_info *info)
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+{
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-+ u32 reg;
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-+ unsigned int tx_pin;
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+ u16 eeprom;
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+
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+ rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
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@@ -781,9 +844,8 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ */
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+ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
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+
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-+ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
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++ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
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+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
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-+ }
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+
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+ if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
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+ rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
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@@ -842,6 +904,62 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
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+ rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
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+ rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
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++}
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++
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++static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
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++ struct ieee80211_conf *conf,
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++ struct rf_channel *rf,
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++ struct channel_info *info)
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++{
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++ u8 rfcsr;
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++
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++ rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
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++ rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
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++
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++ rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
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++ rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
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++ rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
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++
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++ rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
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++ rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
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++ TXPOWER_G_TO_DEV(info->tx_power1));
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++ rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
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++
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++ rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
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++ rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
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++ rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
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++
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++ if (conf_is_ht40(conf))
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++ rt2800pci_rfcsr_write(rt2x00dev, 24,
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++ rt2x00dev->calibration_bw40);
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++ else
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++ rt2800pci_rfcsr_write(rt2x00dev, 24,
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++ rt2x00dev->calibration_bw20);
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++
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++ rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
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++ rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
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++ rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
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++}
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++
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++static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
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++ struct ieee80211_conf *conf,
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++ struct rf_channel *rf,
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++ struct channel_info *info)
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++{
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++ u32 reg;
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++ unsigned int tx_pin;
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++ u16 eeprom;
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++ u8 bbp;
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++
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++ /*
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++ * Determine antenna settings from EEPROM
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++ */
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++ rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
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++
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++ if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
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++ rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
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++ else
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++ rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
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+
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+ /*
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+ * Change BBP settings
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@@ -897,6 +1015,26 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+
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+ rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
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+
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++ rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
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++ rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
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++ rt2800pci_bbp_write(rt2x00dev, 4, bbp);
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++
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++ rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
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++ rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
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++ rt2800pci_bbp_write(rt2x00dev, 3, bbp);
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++
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++ if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
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++ if (conf_is_ht40(conf)) {
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++ rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
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++ rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
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++ rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
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++ } else {
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++ rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
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++ rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
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++ rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
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++ }
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++ }
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++
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+ msleep(1);
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+}
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+
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@@ -1301,7 +1439,7 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ entry_priv = rt2x00dev->rx->entries[0].priv_data;
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+ rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
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+ rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
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-+ rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
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++ rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
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+ rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
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+
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+ /*
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@@ -1659,6 +1797,12 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
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+ rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
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+
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++ if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
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++ rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
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++ rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
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++ rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
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++ }
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++
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+ for (i = 0; i < EEPROM_BBP_SIZE; i++) {
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+ rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
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+
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@@ -1672,6 +1816,144 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ return 0;
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+}
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+
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++static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
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++ bool bw40, u8 rfcsr24, u8 filter_target)
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++{
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++ unsigned int i;
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++ u8 bbp;
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++ u8 rfcsr;
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++ u8 passband;
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++ u8 stopband;
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++ u8 overtuned = 0;
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++
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++ rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
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++
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++ rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
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++ rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
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++ rt2800pci_bbp_write(rt2x00dev, 4, bbp);
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++
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++ rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
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++ rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
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++ rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
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++
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++ /*
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++ * Set power & frequency of passband test tone
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++ */
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++ rt2800pci_bbp_write(rt2x00dev, 24, 0);
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++
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++ for (i = 0; i < 100; i++) {
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++ rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
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++ msleep(1);
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++
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++ rt2800pci_bbp_read(rt2x00dev, 55, &passband);
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++ if (passband)
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++ break;
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++ }
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++
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++ /*
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++ * Set power & frequency of stopband test tone
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++ */
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++ rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
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++
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++ for (i = 0; i < 100; i++) {
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|
++ rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
|
|
|
++ msleep(1);
|
|
|
++
|
|
|
++ rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
|
|
|
++
|
|
|
++ if ((passband - stopband) <= filter_target) {
|
|
|
++ rfcsr24++;
|
|
|
++ overtuned += ((passband - stopband) == filter_target);
|
|
|
++ } else
|
|
|
++ break;
|
|
|
++
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
|
|
|
++ }
|
|
|
++
|
|
|
++ rfcsr24 -= !!overtuned;
|
|
|
++
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
|
|
|
++ return rfcsr24;
|
|
|
++}
|
|
|
++
|
|
|
++static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
|
|
|
++{
|
|
|
++ u8 rfcsr;
|
|
|
++ u8 bbp;
|
|
|
++
|
|
|
++ if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
|
|
|
++ !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
|
|
|
++ !rt2x00_rf(&rt2x00dev->chip, RF3022))
|
|
|
++ return 0;
|
|
|
++
|
|
|
++ /*
|
|
|
++ * Init RF calibration.
|
|
|
++ */
|
|
|
++ rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
|
|
|
++ rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
|
|
|
++ msleep(1);
|
|
|
++ rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
|
|
|
++
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
|
|
|
++
|
|
|
++ /*
|
|
|
++ * Set RX Filter calibration for 20MHz and 40MHz
|
|
|
++ */
|
|
|
++ rt2x00dev->calibration_bw20 =
|
|
|
++ rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
|
|
|
++ rt2x00dev->calibration_bw40 =
|
|
|
++ rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
|
|
|
++
|
|
|
++ /*
|
|
|
++ * Set back to initial state
|
|
|
++ */
|
|
|
++ rt2800pci_bbp_write(rt2x00dev, 24, 0);
|
|
|
++
|
|
|
++ rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
|
|
|
++ rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
|
|
|
++ rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
|
|
|
++
|
|
|
++ /*
|
|
|
++ * set BBP back to BW20
|
|
|
++ */
|
|
|
++ rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
|
|
|
++ rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
|
|
|
++ rt2800pci_bbp_write(rt2x00dev, 4, bbp);
|
|
|
++
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
+/*
|
|
|
+ * Device state switch handlers.
|
|
|
+ */
|
|
|
@@ -1754,7 +2036,8 @@ Signed-off-by: Ivo van Doorn <[email protected]>
|
|
|
+ rt2800pci_init_queues(rt2x00dev) ||
|
|
|
+ rt2800pci_init_registers(rt2x00dev) ||
|
|
|
+ rt2800pci_wait_wpdma_ready(rt2x00dev) ||
|
|
|
-+ rt2800pci_init_bbp(rt2x00dev)))
|
|
|
++ rt2800pci_init_bbp(rt2x00dev) ||
|
|
|
++ rt2800pci_init_rfcsr(rt2x00dev)))
|
|
|
+ return -EIO;
|
|
|
+
|
|
|
+ /*
|
|
|
@@ -2150,6 +2433,12 @@ Signed-off-by: Ivo van Doorn <[email protected]>
|
|
|
+ rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
|
|
|
+
|
|
|
+ /*
|
|
|
++ * Set RX IDX in register to inform hardware that we have handled
|
|
|
++ * this entry and it is available for reuse again.
|
|
|
++ */
|
|
|
++ rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
|
|
|
++
|
|
|
++ /*
|
|
|
+ * Remove TXWI descriptor from start of buffer.
|
|
|
+ */
|
|
|
+ skb_pull(entry->skb, RXWI_DESC_SIZE);
|
|
|
@@ -2416,7 +2705,8 @@ Signed-off-by: Ivo van Doorn <[email protected]>
|
|
|
+ !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
|
|
|
+ !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
|
|
|
+ !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
|
|
|
-+ !rt2x00_rf(&rt2x00dev->chip, RF3052)) {
|
|
|
++ !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
|
|
|
++ !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
|
|
|
+ ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
@@ -2496,8 +2786,8 @@ Signed-off-by: Ivo van Doorn <[email protected]>
|
|
|
+ /* 802.11 HyperLan 2 */
|
|
|
+ { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
|
|
|
+ { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
|
|
|
-+ { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
|
|
|
-+ { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
|
|
|
++ { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
|
|
|
++ { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
|
|
|
+ { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
|
|
|
+ { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
|
|
|
+ { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
|
|
|
@@ -2564,7 +2854,8 @@ Signed-off-by: Ivo van Doorn <[email protected]>
|
|
|
+
|
|
|
+ if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
|
|
|
+ rt2x00_rf(&rt2x00dev->chip, RF2720) ||
|
|
|
-+ rt2x00_rf(&rt2x00dev->chip, RF3052)) {
|
|
|
++ rt2x00_rf(&rt2x00dev->chip, RF3021) ||
|
|
|
++ rt2x00_rf(&rt2x00dev->chip, RF3022)) {
|
|
|
+ spec->num_channels = 14;
|
|
|
+ spec->channels = rf_vals;
|
|
|
+ } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
|
|
|
@@ -2660,7 +2951,9 @@ Signed-off-by: Ivo van Doorn <[email protected]>
|
|
|
+ /*
|
|
|
+ * This device requires firmware.
|
|
|
+ */
|
|
|
-+ __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
|
|
|
++ if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
|
|
|
++ !rt2x00_rt(&rt2x00dev->chip, RT3052))
|
|
|
++ __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
|
|
|
+ if (!modparam_nohwcrypt)
|
|
|
+ __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
|
|
|
+
|
|
|
@@ -2898,7 +3191,6 @@ Signed-off-by: Ivo van Doorn <[email protected]>
|
|
|
+/*
|
|
|
+ * RT2800pci module information.
|
|
|
+ */
|
|
|
-+#ifdef CONFIG_RT2800PCI_PCI
|
|
|
+static struct pci_device_id rt2800pci_device_table[] = {
|
|
|
+ { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
|
|
|
+ { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
|
|
|
@@ -2910,126 +3202,34 @@ Signed-off-by: Ivo van Doorn <[email protected]>
|
|
|
+ { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
|
|
|
+ { 0, }
|
|
|
+};
|
|
|
-+MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
|
|
|
-+#endif /* CONFIG_RT2800PCI_PCI */
|
|
|
+
|
|
|
+MODULE_AUTHOR(DRV_PROJECT);
|
|
|
+MODULE_VERSION(DRV_VERSION);
|
|
|
+MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
|
|
|
+MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
|
|
|
++#ifdef CONFIG_RT2800PCI_PCI
|
|
|
+MODULE_FIRMWARE(FIRMWARE_RT2860);
|
|
|
++MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
|
|
|
++#endif /* CONFIG_RT2800PCI_PCI */
|
|
|
+MODULE_LICENSE("GPL");
|
|
|
+
|
|
|
+#ifdef CONFIG_RT2800PCI_WISOC
|
|
|
-+
|
|
|
-+#ifdef CONFIG_RALINK_RT288X
|
|
|
-+#define WSOC_RT_CHIPSET RT2880
|
|
|
-+#endif /* CONFIG_RALINK_RT288X */
|
|
|
-+
|
|
|
-+#ifdef CONFIG_RALINK_RT305X
|
|
|
-+#define WSOC_RT_CHIPSET RT3052
|
|
|
-+#endif /* CONFIG_RALINK_RT305X */
|
|
|
-+
|
|
|
-+static void rt2800soc_free_reg(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ kfree(rt2x00dev->rf);
|
|
|
-+ rt2x00dev->rf = NULL;
|
|
|
-+
|
|
|
-+ kfree(rt2x00dev->eeprom);
|
|
|
-+ rt2x00dev->eeprom = NULL;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800soc_alloc_reg(struct rt2x00_dev *rt2x00dev)
|
|
|
-+{
|
|
|
-+ struct platform_device *pdev = to_platform_device(rt2x00dev->dev);
|
|
|
-+ struct resource *res;
|
|
|
-+
|
|
|
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
-+ if (!res) {
|
|
|
-+ ERROR_PROBE("Failed to get MMIO resource\n");
|
|
|
-+ return -ENODEV;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ rt2x00dev->csr.base = (void __iomem *) KSEG1ADDR(res->start);
|
|
|
-+ rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
|
|
|
-+ if (!rt2x00dev->eeprom)
|
|
|
-+ goto exit;
|
|
|
-+
|
|
|
-+ rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
|
|
|
-+ if (!rt2x00dev->rf)
|
|
|
-+ goto exit;
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+
|
|
|
-+exit:
|
|
|
-+ ERROR_PROBE("Failed to allocate registers.\n");
|
|
|
-+ rt2800soc_free_reg(rt2x00dev);
|
|
|
-+
|
|
|
-+ return -ENOMEM;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800soc_probe(struct platform_device *pdev)
|
|
|
-+{
|
|
|
-+ const struct rt2x00_ops *ops = &rt2800pci_ops;
|
|
|
-+ struct ieee80211_hw *hw;
|
|
|
-+ struct rt2x00_dev *rt2x00dev;
|
|
|
-+ int retval;
|
|
|
-+
|
|
|
-+ hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
|
|
|
-+ if (!hw) {
|
|
|
-+ ERROR_PROBE("Failed to allocate hardware.\n");
|
|
|
-+ return -ENOMEM;
|
|
|
-+ }
|
|
|
-+
|
|
|
-+ platform_set_drvdata(pdev, hw);
|
|
|
-+
|
|
|
-+ rt2x00dev = hw->priv;
|
|
|
-+ rt2x00dev->dev = &pdev->dev;
|
|
|
-+ rt2x00dev->ops = ops;
|
|
|
-+ rt2x00dev->hw = hw;
|
|
|
-+ rt2x00dev->irq = platform_get_irq(pdev, 0);
|
|
|
-+ rt2x00dev->name = pdev->dev.driver->name;
|
|
|
-+
|
|
|
-+ rt2x00_set_chip_rt(rt2x00dev, WSOC_RT_CHIPSET);
|
|
|
-+
|
|
|
-+ retval = rt2800soc_alloc_reg(rt2x00dev);
|
|
|
-+ if (retval)
|
|
|
-+ goto exit_free_device;
|
|
|
-+
|
|
|
-+ retval = rt2x00lib_probe_dev(rt2x00dev);
|
|
|
-+ if (retval)
|
|
|
-+ goto exit_free_reg;
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+
|
|
|
-+exit_free_reg:
|
|
|
-+ rt2800soc_free_reg(rt2x00dev);
|
|
|
-+
|
|
|
-+exit_free_device:
|
|
|
-+ ieee80211_free_hw(hw);
|
|
|
-+
|
|
|
-+ return retval;
|
|
|
-+}
|
|
|
-+
|
|
|
-+static int rt2800soc_remove(struct platform_device *pdev)
|
|
|
-+{
|
|
|
-+ struct ieee80211_hw *hw = platform_get_drvdata(pdev);
|
|
|
-+ struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
-+
|
|
|
-+ /*
|
|
|
-+ * Free all allocated data.
|
|
|
-+ */
|
|
|
-+ rt2x00lib_remove_dev(rt2x00dev);
|
|
|
-+ rt2800soc_free_reg(rt2x00dev);
|
|
|
-+ ieee80211_free_hw(hw);
|
|
|
-+
|
|
|
-+ return 0;
|
|
|
-+}
|
|
|
++#if defined(CONFIG_RALINK_RT288X)
|
|
|
++__rt2x00soc_probe(RT2880, &rt2800pci_ops);
|
|
|
++#elif defined(CONFIG_RALINK_RT305X)
|
|
|
++__rt2x00soc_probe(RT3052, &rt2800pci_ops);
|
|
|
++#endif
|
|
|
+
|
|
|
+static struct platform_driver rt2800soc_driver = {
|
|
|
-+ .driver.name = "rt2800_wmac",
|
|
|
-+ .probe = rt2800soc_probe,
|
|
|
-+ .remove = rt2800soc_remove,
|
|
|
++ .driver = {
|
|
|
++ .name = "rt2800_wmac",
|
|
|
++ .owner = THIS_MODULE,
|
|
|
++ .mod_name = KBUILD_MODNAME,
|
|
|
++ },
|
|
|
++ .probe = __rt2x00soc_probe,
|
|
|
++ .remove = __devexit_p(rt2x00soc_remove),
|
|
|
++ .suspend = rt2x00soc_suspend,
|
|
|
++ .resume = rt2x00soc_resume,
|
|
|
+};
|
|
|
+#endif /* CONFIG_RT2800PCI_WISOC */
|
|
|
+
|
|
|
@@ -3050,10 +3250,19 @@ Signed-off-by: Ivo van Doorn <[email protected]>
|
|
|
+
|
|
|
+#ifdef CONFIG_RT2800PCI_WISOC
|
|
|
+ ret = platform_driver_register(&rt2800soc_driver);
|
|
|
++ if (ret)
|
|
|
++ return ret;
|
|
|
+#endif
|
|
|
+#ifdef CONFIG_RT2800PCI_PCI
|
|
|
+ ret = pci_register_driver(&rt2800pci_driver);
|
|
|
++ if (ret) {
|
|
|
++#ifdef CONFIG_RT2800PCI_WISOC
|
|
|
++ platform_driver_unregister(&rt2800soc_driver);
|
|
|
++#endif
|
|
|
++ return ret;
|
|
|
++ }
|
|
|
+#endif
|
|
|
++
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
@@ -3071,7 +3280,7 @@ Signed-off-by: Ivo van Doorn <[email protected]>
|
|
|
+module_exit(rt2800pci_exit);
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--- /dev/null
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+++ b/drivers/net/wireless/rt2x00/rt2800pci.h
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-@@ -0,0 +1,1880 @@
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+@@ -0,0 +1,1927 @@
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+/*
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+ Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
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+ <http://rt2x00.serialmonkey.com>
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@@ -3110,7 +3319,8 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ * RF2750 2.4G/5G 1T2R
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+ * RF3020 2.4G 1T1R
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+ * RF2020 2.4G B/G
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-+ * RF3052 2.4G 2T2R
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++ * RF3021 2.4G 1T2R
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++ * RF3022 2.4G 2T2R
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+ */
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+#define RF2820 0x0001
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+#define RF2850 0x0002
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@@ -3118,7 +3328,8 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+#define RF2750 0x0004
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+#define RF3020 0x0005
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+#define RF2020 0x0006
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-+#define RF3052 0x0008
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++#define RF3021 0x0007
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++#define RF3022 0x0008
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+
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+/*
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+ * RT2860 version
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@@ -3157,12 +3368,6 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ */
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+
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+/*
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-+ * PCI Configuration Header
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-+ */
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-+#define PCI_CONFIG_HEADER_VENDOR 0x0000
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-+#define PCI_CONFIG_HEADER_DEVICE 0x0002
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-+
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-+/*
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+ * E2PROM_CSR: EEPROM control register.
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+ * RELOAD: Write 1 to reload eeprom content.
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+ * TYPE: 0: 93c46, 1:93c66.
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@@ -3453,6 +3658,15 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+#define PBF_DBG 0x043c
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+
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+/*
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++ * RF registers
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++ */
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++#define RF_CSR_CFG 0x0500
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++#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
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++#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
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++#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
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++#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
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++
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++/*
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+ * MAC Control/Status Registers(CSR).
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+ * Some values are set in TU, whereas 1 TU == 1024 us.
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+ */
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@@ -4545,6 +4759,48 @@ Signed-off-by: Ivo van Doorn <[email protected]>
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+ * BBP 3: RX Antenna
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+ */
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+#define BBP3_RX_ANTENNA FIELD8(0x18)
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++#define BBP3_HT40_PLUS FIELD8(0x20)
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++
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++/*
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++ * BBP 4: Bandwidth
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++ */
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++#define BBP4_TX_BF FIELD8(0x01)
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++#define BBP4_BANDWIDTH FIELD8(0x18)
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++
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++/*
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++ * RFCSR registers
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++ * The wordsize of the RFCSR is 8 bits.
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++ */
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++
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++/*
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++ * RFCSR 6:
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++ */
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++#define RFCSR6_R FIELD8(0x03)
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++
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++/*
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++ * RFCSR 7:
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++ */
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++#define RFCSR7_RF_TUNING FIELD8(0x01)
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++
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++/*
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++ * RFCSR 12:
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++ */
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++#define RFCSR12_TX_POWER FIELD8(0x1f)
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++
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++/*
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++ * RFCSR 22:
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++ */
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++#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
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++
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++/*
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++ * RFCSR 23:
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++ */
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++#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
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++
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++/*
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++ * RFCSR 30:
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++ */
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++#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
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+
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+/*
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+ * RF registers
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