ralink: backport various fixes from linux-mti

Signed-off-by: John Crispin <[email protected]>

SVN-Revision: 39329

target/linux/ramips/patches-3.10/0508-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch

@@ -0,0 +1,49 @@
+From 553ddf4f3f20c28ab03f87ac8c3cde5edf714675 Mon Sep 17 00:00:00 2001
+From: Tony Wu <[email protected]>
+Date: Fri, 21 Jun 2013 10:13:08 +0000
+Subject: [PATCH 022/105] MIPS: GIC: Fix gic_set_affinity infinite loop
+
+There is an infinite loop in gic_set_affinity. When irq_set_affinity
+gets called on gic controller, it blocks forever.
+
+Signed-off-by: Tony Wu <[email protected]>
+Cc: Steven J. Hill <[email protected]>
+Cc: [email protected]
+Patchwork: https://patchwork.linux-mips.org/patch/5537/
+Signed-off-by: Ralf Baechle <[email protected]>
+(cherry picked from commit c214c03512b67e56dea3f4471705f8caae49553a)
+---
+ arch/mips/kernel/irq-gic.c |   15 +++++++--------
+ 1 file changed, 7 insertions(+), 8 deletions(-)
+
+diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
+index c01b307..5b5ddb2 100644
+--- a/arch/mips/kernel/irq-gic.c
++++ b/arch/mips/kernel/irq-gic.c
+@@ -219,16 +219,15 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
+ 
+ 	/* Assumption : cpumask refers to a single CPU */
+ 	spin_lock_irqsave(&gic_lock, flags);
+-	for (;;) {
+-		/* Re-route this IRQ */
+-		GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
+ 
+-		/* Update the pcpu_masks */
+-		for (i = 0; i < NR_CPUS; i++)
+-			clear_bit(irq, pcpu_masks[i].pcpu_mask);
+-		set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
++	/* Re-route this IRQ */
++	GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
++
++	/* Update the pcpu_masks */
++	for (i = 0; i < NR_CPUS; i++)
++		clear_bit(irq, pcpu_masks[i].pcpu_mask);
++	set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
+ 
+-	}
+ 	cpumask_copy(d->affinity, cpumask);
+ 	spin_unlock_irqrestore(&gic_lock, flags);
+ 
+-- 
+1.7.10.4
+

target/linux/ramips/patches-3.10/0509-MIPS-Kconfig-CMP-support-needs-to-select-SMP-as-well.patch

@@ -0,0 +1,57 @@
+From 184edf882ebb7885b49fa231a503205da94e78f0 Mon Sep 17 00:00:00 2001
+From: Markos Chandras <[email protected]>
+Date: Wed, 2 Oct 2013 12:40:26 -0500
+Subject: [PATCH 065/105] MIPS: Kconfig: CMP support needs to select SMP as
+ well
+
+The CMP code is only designed to work with SMP configurations.
+Fixes multiple build problems on certain randconfigs:
+
+In file included from arch/mips/kernel/smp-cmp.c:34:0:
+arch/mips/include/asm/smp.h:28:0:
+error: "raw_smp_processor_id" redefined [-Werror]
+
+In file included from include/linux/sched.h:30:0,
+from arch/mips/kernel/smp-cmp.c:22:
+include/linux/smp.h:135:0: note: this is the location of the
+previous definition
+
+In file included from arch/mips/kernel/smp-cmp.c:34:0:
+arch/mips/include/asm/smp.h:57:20:
+error: redefinition of 'smp_send_reschedule'
+
+In file included from include/linux/sched.h:30:0,
+from arch/mips/kernel/smp-cmp.c:22:
+include/linux/smp.h:179:20: note: previous
+definition of 'smp_send_reschedule' was here
+
+In file included from arch/mips/kernel/smp-cmp.c:34:0:
+arch/mips/include/asm/smp.h: In function 'smp_send_reschedule':
+arch/mips/include/asm/smp.h:61:8:
+error: dereferencing pointer to incomplete type
+[...]
+
+Signed-off-by: Markos Chandras <[email protected]>
+Cc: [email protected]
+Cc: Markos Chandras <[email protected]>
+Patchwork: https://patchwork.linux-mips.org/patch/5812/
+Signed-off-by: Ralf Baechle <[email protected]>
+---
+ arch/mips/Kconfig |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index e82c066..b537fb1 100644
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -2010,6 +2010,7 @@ config MIPS_VPE_APSP_API
+ config MIPS_CMP
+ 	bool "MIPS CMP framework support"
+ 	depends on SYS_SUPPORTS_MIPS_CMP
++	select SMP
+ 	select SYNC_R4K
+ 	select SYS_SUPPORTS_SMP
+ 	select SYS_SUPPORTS_SCHED_SMT if SMP
+-- 
+1.7.10.4
+

target/linux/ramips/patches-3.10/0510-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch

@@ -0,0 +1,57 @@
+From c4d621e75e865fa5374946515ad0c5e060b9c446 Mon Sep 17 00:00:00 2001
+From: Leonid Yegoshin <[email protected]>
+Date: Wed, 11 Sep 2013 14:17:47 -0500
+Subject: [PATCH 056/105] MIPS: Fix SMP core calculations when using MT
+ support.
+
+The TCBIND register is only available if the core has MT support. It
+should not be read otherwise. Secondly, the number of TCs (siblings)
+are calculated differently depending on if the kernel is configured
+as SMVP or SMTC.
+
+Signed-off-by: Leonid Yegoshin <[email protected]>
+Signed-off-by: Steven J. Hill <[email protected]>
+Cc: [email protected]
+Patchwork: https://patchwork.linux-mips.org/patch/5822/
+Signed-off-by: Ralf Baechle <[email protected]>
+(cherry picked from commit 670bac3a8c201fc1f5f92ac6b4a8b42dc8172937)
+---
+ arch/mips/kernel/smp-cmp.c |   13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
+index c2e5d74..5969f1e 100644
+--- a/arch/mips/kernel/smp-cmp.c
++++ b/arch/mips/kernel/smp-cmp.c
+@@ -99,7 +99,9 @@ static void cmp_init_secondary(void)
+ 
+ 	c->core = (read_c0_ebase() >> 1) & 0x1ff;
+ #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
+-	c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
++	if (cpu_has_mipsmt)
++		c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
++			TCBIND_CURVPE;
+ #endif
+ #ifdef CONFIG_MIPS_MT_SMTC
+ 	c->tc_id  = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
+@@ -177,9 +179,16 @@ void __init cmp_smp_setup(void)
+ 	}
+ 
+ 	if (cpu_has_mipsmt) {
+-		unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
++		unsigned int nvpe = 1;
++#ifdef CONFIG_MIPS_MT_SMP
++		unsigned int mvpconf0 = read_c0_mvpconf0();
++
++		nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
++#elif defined(CONFIG_MIPS_MT_SMTC)
++		unsigned int mvpconf0 = read_c0_mvpconf0();
+ 
+ 		nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
++#endif
+ 		smp_num_siblings = nvpe;
+ 	}
+ 	pr_info("Detected %i available secondary CPU(s)\n", ncpu);
+-- 
+1.7.10.4
+

target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch

@@ -0,0 +1,106 @@
+From 43334f8438704001deb258b6e7223699bd336c77 Mon Sep 17 00:00:00 2001
+From: "Steven J. Hill" <[email protected]>
+Date: Wed, 25 Sep 2013 14:58:19 -0500
+Subject: [PATCH 093/105] MIPS: GIC: Send IPIs using the GIC.
+
+If a GIC present, then use it to send IPIs between the cores.
+
+Signed-off-by: Steven J. Hill <[email protected]>
+---
+ arch/mips/kernel/smp-mt.c |   32 ++++++++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
+index 2f8c468..d057c84 100644
+--- a/arch/mips/kernel/smp-mt.c
++++ b/arch/mips/kernel/smp-mt.c
+@@ -71,6 +71,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
+ 
+ 		/* Record this as available CPU */
+ 		set_cpu_possible(tc, true);
++		set_cpu_present(tc, true);
+ 		__cpu_number_map[tc]	= ++ncpu;
+ 		__cpu_logical_map[ncpu] = tc;
+ 	}
+@@ -112,12 +113,35 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
+ 	write_tc_c0_tchalt(TCHALT_H);
+ }
+ 
++static void mp_send_ipi_single(int cpu, unsigned int action)
++{
++	unsigned long flags;
++
++	local_irq_save(flags);
++
++	switch (action) {
++	case SMP_CALL_FUNCTION:
++		gic_send_ipi(plat_ipi_call_int_xlate(cpu));
++		break;
++
++	case SMP_RESCHEDULE_YOURSELF:
++		gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
++		break;
++	}
++
++	local_irq_restore(flags);
++}
++
+ static void vsmp_send_ipi_single(int cpu, unsigned int action)
+ {
+ 	int i;
+ 	unsigned long flags;
+ 	int vpflags;
+ 
++	if (gic_present) {
++		mp_send_ipi_single(cpu, action);
++		return;
++	}
+ 	local_irq_save(flags);
+ 
+ 	vpflags = dvpe();	/* can't access the other CPU's registers whilst MVPE enabled */
+@@ -164,6 +188,8 @@ static void __cpuinit vsmp_init_secondary(void)
+ 
+ static void __cpuinit vsmp_smp_finish(void)
+ {
++	pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id());
++
+ 	/* CDFIXME: remove this? */
+ 	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
+ 
+@@ -178,6 +204,7 @@ static void __cpuinit vsmp_smp_finish(void)
+ 
+ static void vsmp_cpus_done(void)
+ {
++	pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id());
+ }
+ 
+ /*
+@@ -191,6 +218,8 @@ static void vsmp_cpus_done(void)
+ static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
+ {
+ 	struct thread_info *gp = task_thread_info(idle);
++	pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n",
++		smp_processor_id(), cpu);
+ 	dvpe();
+ 	set_c0_mvpcontrol(MVPCONTROL_VPC);
+ 
+@@ -232,6 +261,7 @@ static void __init vsmp_smp_setup(void)
+ 	unsigned int mvpconf0, ntc, tc, ncpu = 0;
+ 	unsigned int nvpe;
+ 
++	pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id());
+ #ifdef CONFIG_MIPS_MT_FPAFF
+ 	/* If we have an FPU, enroll ourselves in the FPU-full mask */
+ 	if (cpu_has_fpu)
+@@ -272,6 +302,8 @@ static void __init vsmp_smp_setup(void)
+ 
+ static void __init vsmp_prepare_cpus(unsigned int max_cpus)
+ {
++	pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n",
++		smp_processor_id(), max_cpus);
+ 	mips_mt_set_cpuoptions();
+ }
+ 
+-- 
+1.7.10.4
+