layerscape: add 64b/32b target for ls1046ardb device

Add support for NXP layerscape ls1046ardb 64b/32b Dev board.

LS1046ARDB Specification:
-------------------------
Memory subsystem:
* 8GByte DDR4 SDRAM (64bit bus)
* 512 Mbyte NAND flash
* Two 64 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
* On-board 4G eMMC
Ethernet:
* Two XFI 10G ports
* Two SGMII ports
* Two RGMII ports
PCIe:
* PCIe1 (SerDes2 Lane0) to miniPCIe slot
* PCIe2 (SerDes2 Lane1) to x2 PCIe slot
* PCIe3 (SerDes2 Lane2) to x4 PCIe slot

* USB 3.0: one super speed USB 3.0 type A port, one Micro-AB port
* UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Yutang Jiang <[email protected]>

package/boot/uboot-layerscape-32b/Makefile

@@ -16,7 +16,7 @@ PKG_SOURCE_PROTO:=git
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
 PKG_SOURCE_URL:=https://github.com/fsl-jyt/uboot-ls-32b.git
-PKG_SOURCE_VERSION:=719f8b606334bc73367f78c204dce69786963b65
+PKG_SOURCE_VERSION:=763de09cc7265e3147e2df2e15f91c73231907f4
 
 PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
 
@@ -35,6 +35,11 @@ define uboot/ls1043ardb
 	CONFIG=ls1043ardb-uboot.bin
 endef
 
+define uboot/ls1046ardb
+	TITLE:=U-Boot binary $(PKG_NAME)-$(PKG_VERSION) for NXP ls1046ardb 32b Dev Board
+	CONFIG=ls1046ardb-uboot.bin
+endef
+
 define uboot/ls1012ardb
 	TITLE:=U-Boot binary $(PKG_NAME)-$(PKG_VERSION) for NXP ls1012ardb 32b Dev Board
 	CONFIG=ls1012ardb-uboot.bin.swap
@@ -42,6 +47,7 @@ endef
 
 UBOOTS := \
 	ls1043ardb \
+	ls1046ardb \
 	ls1012ardb
 
 define Package/uboot/template

package/boot/uboot-layerscape/Makefile

@@ -36,6 +36,11 @@ define uboot/ls1043ardb
 	CONFIG=ls1043ardb
 endef
 
+define uboot/ls1046ardb
+	TITLE:=U-Boot $(PKG_NAME)-$(PKG_VERSION) for NXP ls1046ardb 64b Dev Board
+	CONFIG=ls1046ardb_qspi
+endef
+
 define uboot/ls1012ardb
 	TITLE:=U-Boot $(PKG_NAME)-$(PKG_VERSION) for NXP ls1012ardb 64b Dev Board
 	CONFIG=ls1012ardb_qspi
@@ -44,6 +49,7 @@ endef
 
 UBOOTS := \
 	ls1043ardb \
+	ls1046ardb \
 	ls1012ardb
 
 define Package/uboot/template

package/firmware/fman-ucode/Makefile

@@ -35,8 +35,14 @@ define fman/ls1043ardb
 	CONFIG=fsl_fman_ucode_ls1043_r1.0_108_4_5.bin
 endef
 
+define fman/ls1046ardb
+	TITLE=FMAN UCODE $(PKG_NAME)-$(PKG_VERSION) for NXP ls1046ardb 64b/32b Dev Board
+	CONFIG=fsl_fman_ucode_t2080_r1.1_106_4_18.bin
+endef
+
 FMANS := \
-	ls1043ardb
+	ls1043ardb \
+	ls1046ardb
 
 define Package/fman/template
 define Package/fman-layerscape-$(1)

package/firmware/rcw/Makefile

@@ -16,7 +16,7 @@ PKG_SOURCE_PROTO:=git
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
 PKG_SOURCE_URL:=https://github.com/fsl-jyt/rcw.git
-PKG_SOURCE_VERSION:=e101d1207f402c7b761990a3e6681fdae8f253e3
+PKG_SOURCE_VERSION:=17e09e19bd5cf94e5ebc84916b4607743c29723e
 
 PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
 
@@ -35,6 +35,11 @@ define rcw/ls1043ardb
 	CONFIG=ls1043ardb-rcw.bin
 endef
 
+define rcw/ls1046ardb
+	TITLE=RCW binary $(PKG_NAME)-$(PKG_VERSION) for NXP ls1046ardb 64b/32b Dev Board
+	CONFIG=ls1046ardb-rcw.bin
+endef
+
 define rcw/ls1012ardb
 	TITLE=RCW binary $(PKG_NAME)-$(PKG_VERSION) for NXP ls1012ardb 64b/32b Dev Board
 	CONFIG=ls1012ardb-rcw.bin
@@ -42,6 +47,7 @@ endef
 
 RCWS := \
 	ls1043ardb \
+	ls1046ardb \
 	ls1012ardb
 
 define Package/rcw/template

target/linux/layerscape/64b/profiles/00-default.mk

@@ -10,6 +10,8 @@ endef
 DEFAULT_PACKAGES+= \
 	rcw-layerscape-ls1043ardb uboot-layerscape-$(SUBTARGET)-ls1043ardb \
 	fman-layerscape-ls1043ardb \
+	rcw-layerscape-ls1046ardb uboot-layerscape-$(SUBTARGET)-ls1046ardb \
+	fman-layerscape-ls1046ardb \
 	rcw-layerscape-ls1012ardb uboot-layerscape-$(SUBTARGET)-ls1012ardb \
 	kmod-ppfe ppfe-ls1012ardb
 

target/linux/layerscape/image/Makefile

@@ -62,6 +62,21 @@ endif
 endef
 TARGET_DEVICES += ls1043ardb
 
+define Device/ls1046ardb
+  DEVICE_TITLE := ls1046ardb-$(SUBTARGET)
+  DEVICE_PACKAGES += rcw-layerscape-ls1046ardb uboot-layerscape-$(SUBTARGET)-ls1046ardb fman-layerscape-ls1046ardb
+ifeq ($(SUBTARGET),64b)
+  DEVICE_DTS = freescale/fsl-ls1046a-rdb
+endif
+ifeq ($(SUBTARGET),32b)
+  DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1046a-rdb
+endif
+  IMAGE/firmware.bin = append-ls-rcw $(1) | pad-to 1M | append-ls-uboot $(1) | pad-to 3M | \
+  					append-ls-fman $(1) | pad-to 4M | append-ls-dtb $$(DEVICE_DTS) | pad-to 5M | \
+  					append-kernel | pad-to 10M | append-ls-rootfs-ext4 $(1) 22M | check-size 33554433
+endef
+TARGET_DEVICES += ls1046ardb
+
 define Device/ls1012ardb
   DEVICE_TITLE := ls1012ardb-$(SUBTARGET)
   DEVICE_PACKAGES += rcw-layerscape-ls1012ardb uboot-layerscape-$(SUBTARGET)-ls1012ardb kmod-ppfe ppfe-ls1012ardb

target/linux/layerscape/patches-4.4/0140-config-add-freescale-config-for-amr64.patch

@@ -0,0 +1,148 @@
+From 880b7aa2e2c62e54245fb77d92db502175232d86 Mon Sep 17 00:00:00 2001
+From: Zhao Qiang <[email protected]>
+Date: Wed, 12 Oct 2016 11:01:17 +0800
+Subject: [PATCH 140/141] config: add freescale config for amr64
+
+Signed-off-by: Zhao Qiang <[email protected]>
+---
+ arch/arm64/configs/freescale.config |  134 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 134 insertions(+)
+ create mode 100644 arch/arm64/configs/freescale.config
+
+--- /dev/null
++++ b/arch/arm64/configs/freescale.config
+@@ -0,0 +1,134 @@
++# general options
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_SLAB=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_ARM64_VA_BITS_48=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=262144
++CONFIG_PRINTK_TIME=y
++CONFIG_PID_IN_CONTEXTIDR=y
++CONFIG_IPV6=y
++# iommu
++CONFIG_IOMMU_SUPPORT=y
++CONFIG_ARM_SMMU=y
++# dpaa2
++CONFIG_STAGING=y
++CONFIG_FSL_MC_BUS=y
++CONFIG_FSL_MC_RESTOOL=y
++CONFIG_FSL_MC_DPIO=y
++CONFIG_FSL_DPAA2=y
++CONFIG_NET_NS=y
++CONFIG_FSL_DPAA2_DCE=y
++CONFIG_FSL_DCE_FLOW_LIMIT=65536
++CONFIG_FSL_DCE_API_TIME_TRIAL=m
++CONFIG_LS_SOC_DRIVERS=y
++# mdio
++CONFIG_FSL_XGMAC_MDIO=y
++CONFIG_MDIO_BUS_MUX_MMIOREG=y
++# phy
++CONFIG_AQUANTIA_PHY=y
++CONFIG_VITESSE_PHY=y
++CONFIG_REALTEK_PHY=y
++CONFIG_FIXED_PHY=y
++# reset support
++CONFIG_POWER_RESET_LAYERSCAPE=y
++# pci
++CONFIG_PCI_LAYERSCAPE=y
++CONFIG_PCI_HOST_GENERIC=y
++CONFIG_E1000=y
++CONFIG_E1000E=y
++# clock driver
++CONFIG_CLK_QORIQ=y
++# usb
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_DWC3=y
++CONFIG_DMADEVICES=y
++# ahci/sata
++CONFIG_AHCI_QORIQ=y
++# esdhc
++CONFIG_MMC_SDHCI_OF_ESDHC=y
++# virtualization
++CONFIG_VHOST_NET=y
++CONFIG_KVM_ARM_MAX_VCPUS=8
++# I2C
++CONFIG_I2C=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_MUX_PCA954x=y
++CONFIG_I2C_IMX=y
++# hardware monitor
++CONFIG_SENSORS_LM90=y
++CONFIG_SENSORS_INA2XX=y
++# DPAA 1
++CONFIG_HAS_FSL_QBMAN=y
++CONFIG_CRYPTO_DEV_FSL_CAAM=y
++# network
++CONFIG_BRIDGE=m
++CONFIG_MACVLAN=y
++CONFIG_FSL_SDK_FMAN=y
++CONFIG_FMAN_ARM=y
++CONFIG_FSL_SDK_DPAA_ETH=y
++CONFIG_INET_ESP=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=y
++# vfio
++CONFIG_VFIO=y
++CONFIG_VFIO_PCI=y
++CONFIG_VFIO_FSL_MC=y
++# CPU Frequency scaling
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_COMMON=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_QORIQ_CPUFREQ=y
++#ifc
++CONFIG_MTD_OF_PARTS=y
++CONFIG_MTD_GEN_PROBE=y
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_CFI_ADV_OPTIONS=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_CFI_STAA=y
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_NAND=y
++CONFIG_MTD_NAND_FSL_IFC=y
++#spi
++CONFIG_SPI_FSL_DSPI=y
++CONFIG_MTD_SPI_NOR=y
++CONFIG_MTD_DATAFLASH=y
++CONFIG_MTD_M25P80=y
++CONFIG_MTD_SST25L=y
++#RTC
++CONFIG_RTC_DRV_DS3232=y
++#CryptoAPI
++CONFIG_CRYPTO_SHA256=y
++CONFIG_CRYPTO_SHA512=y
++# ls1046a
++CONFIG_MTD_CFI_BE_BYTE_SWAP=y
++CONFIG_SPI_FSL_QUADSPI=y
++CONFIG_RTC_DRV_PCF2127=y
++CONFIG_WATCHDOG=y
++CONFIG_IMX2_WDT=y
++CONFIG_HWMON=y
++CONFIG_SENSORS_LM90=y
++CONFIG_SENSORS_INA2XX=y
++CONFIG_EEPROM_AT24=y
++# lpuart
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++# ftm
++CONFIG_FTM_ALARM=y
++# qDMA
++CONFIG_FSL_QDMA=y
++CONFIG_DMATEST=y
++#NVMe
++CONFIG_BLK_DEV_NVME=y

target/linux/layerscape/patches-4.4/3131-arm64-ls1046a-add-DTS-for-Freescale-LS1046A-SoC.patch

@@ -0,0 +1,1056 @@
+From 80ca93f1a5590529e39560099a71edb03897050e Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <[email protected]>
+Date: Wed, 11 May 2016 11:29:51 +0800
+Subject: [PATCH 131/141] arm64/ls1046a: add DTS for Freescale LS1046A SoC
+
+LS1046a is an SoC with 4 ARMv8 A72 cores and most other IP blocks
+similar to LS1043a which complies to Chassis 2.1 spec.
+
+Following levels of DTSI/DTS files have been created for the
+LS1046A SoC family:
+
+- fsl-ls1046a.dtsi:
+  DTS-Include file for FSL LS1046A SoC.
+
+Signed-off-by: Gong Qianyu <[email protected]>
+Signed-off-by: Minghuan Lian <[email protected]>
+Signed-off-by: Hou Zhiqiang <[email protected]>
+Signed-off-by: Mihai Bantea <[email protected]>
+Signed-off-by: Mingkai Hu <[email protected]>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1029 ++++++++++++++++++++++++
+ 1 file changed, 1029 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+@@ -0,0 +1,1029 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2016, Freescale Semiconductor
++ *
++ * Mingkai Hu <[email protected]>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/ {
++	compatible = "fsl,ls1046a";
++	interrupt-parent = <&gic>;
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	aliases {
++		ethernet0 = &fm1mac1;
++		ethernet1 = &fm1mac2;
++		ethernet2 = &fm1mac3;
++		ethernet3 = &fm1mac4;
++		ethernet4 = &fm1mac5;
++		ethernet5 = &fm1mac6;
++		ethernet6 = &fm1mac9;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu0: cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a72";
++			reg = <0x0>;
++			clocks = <&clockgen 1 0>;
++			next-level-cache = <&l2>;
++		};
++
++		cpu1: cpu@1 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a72";
++			reg = <0x1>;
++			clocks = <&clockgen 1 0>;
++			next-level-cache = <&l2>;
++		};
++
++		cpu2: cpu@2 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a72";
++			reg = <0x2>;
++			clocks = <&clockgen 1 0>;
++			next-level-cache = <&l2>;
++		};
++
++		cpu3: cpu@3 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a72";
++			reg = <0x3>;
++			clocks = <&clockgen 1 0>;
++			next-level-cache = <&l2>;
++		};
++
++		l2: l2-cache {
++			compatible = "cache";
++		};
++	};
++
++	memory@80000000 {
++		device_type = "memory";
++		reg = <0x0 0x80000000 0 0x80000000>;
++		      /* DRAM space 1, size: 2GiB DRAM */
++	};
++
++	sysclk: sysclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <100000000>;
++		clock-output-names = "sysclk";
++	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts = <1 13 0x1>, /* Physical Secure PPI */
++			     <1 14 0x1>, /* Physical Non-Secure PPI */
++			     <1 11 0x1>, /* Virtual PPI */
++			     <1 10 0x1>; /* Hypervisor PPI */
++		arm,reread-timer;
++	};
++
++	pmu {
++		compatible = "arm,armv8-pmuv3";
++		interrupts = <0 106 0x4>,
++			     <0 107 0x4>,
++			     <0 95 0x4>,
++			     <0 97 0x4>;
++		interrupt-affinity = <&cpu0>,
++				     <&cpu1>,
++				     <&cpu2>,
++				     <&cpu3>;
++	};
++
++	gic: interrupt-controller@1400000 {
++		compatible = "arm,gic-400";
++		#interrupt-cells = <3>;
++		interrupt-controller;
++		reg = <0x0 0x1410000 0 0x10000>, /* GICD */
++		      <0x0 0x1420000 0 0x20000>, /* GICC */
++		      <0x0 0x1440000 0 0x20000>, /* GICH */
++		      <0x0 0x1460000 0 0x20000>; /* GICV */
++		interrupts = <1 9 0xf08>;
++	};
++
++	soc {
++		compatible = "simple-bus";
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		clockgen: clocking@1ee1000 {
++			compatible = "fsl,ls1046a-clockgen";
++			reg = <0x0 0x1ee1000 0x0 0x1000>;
++			#clock-cells = <2>;
++			clocks = <&sysclk>;
++		};
++
++		scfg: scfg@1570000 {
++			compatible = "fsl,ls1046a-scfg", "syscon";
++			reg = <0x0 0x1570000 0x0 0x10000>;
++			big-endian;
++		};
++
++		reset: reset@1ee00b0 {
++			compatible = "fsl,ls-reset";
++			reg = <0x0 0x1ee00b0 0x0 0x4>;
++			big-endian;
++		};
++
++		rcpm: rcpm@1ee2000 {
++			compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1";
++			reg = <0x0 0x1ee2000 0x0 0x10000>;
++		};
++
++		ifc: ifc@1530000 {
++			compatible = "fsl,ifc", "simple-bus";
++			reg = <0x0 0x1530000 0x0 0x10000>;
++			interrupts = <0 43 0x4>;
++		};
++
++		esdhc: esdhc@1560000 {
++			compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
++			reg = <0x0 0x1560000 0x0 0x10000>;
++			interrupts = <0 62 0x4>;
++			clock-frequency = <0>;
++			voltage-ranges = <1800 1800 3300 3300>;
++			sdhci,auto-cmd12;
++			big-endian;
++			bus-width = <4>;
++		};
++
++		qman: qman@1880000 {
++			compatible = "fsl,qman";
++			reg = <0x00 0x1880000 0x0 0x10000>;
++			interrupts = <0 45 0x4>;
++		};
++
++		bman: bman@1890000 {
++			compatible = "fsl,bman";
++			reg = <0x00 0x1890000 0x0 0x10000>;
++			interrupts = <0 45 0x4>;
++		};
++
++		fman0: fman@1a00000 {
++			#address-cells = <1>;
++			#size-cells = <1>;
++			cell-index = <0>;
++			compatible = "fsl,fman", "simple-bus";
++			ranges = <0x0 0x00 0x1a00000 0x100000>;
++			reg = <0x00 0x1a00000 0x0 0x100000>;
++			interrupts = <0 44 0x4>, <0 45 0x4>;
++			clocks = <&clockgen 3 0>;
++			clock-names = "fmanclk";
++
++			cc {
++				compatible = "fsl,fman-cc";
++			};
++
++			muram@0 {
++				compatible = "fsl,fman-muram";
++				reg = <0x0 0x60000>;
++			};
++
++			bmi@80000 {
++				compatible = "fsl,fman-bmi";
++				reg = <0x80000 0x400>;
++			};
++
++			qmi@80400 {
++				compatible = "fsl,fman-qmi";
++				reg = <0x80400 0x400>;
++			};
++
++			fman0_oh1: port@82000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x82000 0x1000>;
++			};
++
++			fman0_oh2: port@83000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x83000 0x1000>;
++			};
++
++			fman0_oh3: port@84000 {
++				cell-index = <2>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x84000 0x1000>;
++			};
++
++			fman0_oh4: port@85000 {
++				cell-index = <3>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x85000 0x1000>;
++			};
++
++			fman0_oh5: port@86000 {
++				cell-index = <4>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x86000 0x1000>;
++			};
++
++			fman0_oh6: port@87000 {
++				cell-index = <5>;
++				compatible = "fsl,fman-port-oh";
++				reg = <0x87000 0x1000>;
++			};
++
++			policer@c0000 {
++				compatible = "fsl,fman-policer";
++				reg = <0xc0000 0x1000>;
++			};
++
++			keygen@c1000 {
++				compatible = "fsl,fman-keygen";
++				reg = <0xc1000 0x1000>;
++			};
++
++			dma@c2000 {
++				compatible = "fsl,fman-dma";
++				reg = <0xc2000 0x1000>;
++			};
++
++			fpm@c3000 {
++				compatible = "fsl,fman-fpm";
++				reg = <0xc3000 0x1000>;
++			};
++
++			parser@c7000 {
++				compatible = "fsl,fman-parser";
++				reg = <0xc7000 0x1000>;
++			};
++
++			vsps@dc000 {
++				compatible = "fsl,fman-vsps";
++				reg = <0xdc000 0x1000>;
++			};
++
++			mdio0: mdio@fc000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xfc000 0x1000>;
++			};
++
++			xmdio0: mdio@fd000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xfd000 0x1000>;
++			};
++
++			fman0_rx0: port@88000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x88000 0x1000>;
++			};
++
++			fman0_tx0: port@a8000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xa8000 0x1000>;
++			};
++
++			fm1mac1: ethernet@e0000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-memac";
++				reg = <0xe0000 0x1000>;
++				fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio@e1000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xe1000 0x1000>;
++			};
++
++			fman0_rx1: port@89000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x89000 0x1000>;
++			};
++
++			fman0_tx1: port@a9000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xa9000 0x1000>;
++			};
++
++			fm1mac2: ethernet@e2000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-memac";
++				reg = <0xe2000 0x1000>;
++				fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio@e3000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xe3000 0x1000>;
++			};
++
++			fman0_rx2: port@8a000 {
++				cell-index = <2>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x8a000 0x1000>;
++			};
++
++			fman0_tx2: port@aa000 {
++				cell-index = <2>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xaa000 0x1000>;
++			};
++
++			fm1mac3: ethernet@e4000 {
++				cell-index = <2>;
++				compatible = "fsl,fman-memac";
++				reg = <0xe4000 0x1000>;
++				fsl,port-handles = <&fman0_rx2 &fman0_tx2>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio@e5000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xe5000 0x1000>;
++			};
++
++			fman0_rx3: port@8b000 {
++				cell-index = <3>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x8b000 0x1000>;
++			};
++
++			fman0_tx3: port@ab000 {
++				cell-index = <3>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xab000 0x1000>;
++			};
++
++			fm1mac4: ethernet@e6000 {
++				cell-index = <3>;
++				compatible = "fsl,fman-memac";
++				reg = <0xe6000 0x1000>;
++				fsl,port-handles = <&fman0_rx3 &fman0_tx3>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio@e7000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xe7000 0x1000>;
++			};
++
++			fman0_rx4: port@8c000 {
++				cell-index = <4>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x8c000 0x1000>;
++			};
++
++			fman0_tx4: port@ac000 {
++				cell-index = <4>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xac000 0x1000>;
++			};
++
++			fm1mac5: ethernet@e8000 {
++				cell-index = <4>;
++				compatible = "fsl,fman-memac";
++				reg = <0xe8000 0x1000>;
++				fsl,port-handles = <&fman0_rx4 &fman0_tx4>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio@e9000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xe9000 0x1000>;
++			};
++
++			fman0_rx5: port@8d000 {
++				cell-index = <5>;
++				compatible = "fsl,fman-port-1g-rx";
++				reg = <0x8d000 0x1000>;
++			};
++
++			fman0_tx5: port@ad000 {
++				cell-index = <5>;
++				compatible = "fsl,fman-port-1g-tx";
++				reg = <0xad000 0x1000>;
++			};
++
++			fm1mac6: ethernet@ea000 {
++				cell-index = <5>;
++				compatible = "fsl,fman-memac";
++				reg = <0xea000 0x1000>;
++				fsl,port-handles = <&fman0_rx5 &fman0_tx5>;
++				ptimer-handle = <&ptp_timer0>;
++			};
++
++			mdio@eb000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xeb000 0x1000>;
++			};
++
++			fman0_10g_rx0: port@90000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-port-10g-rx";
++				reg = <0x90000 0x1000>;
++			};
++
++			fman0_10g_tx0: port@b0000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-port-10g-tx";
++				reg = <0xb0000 0x1000>;
++				fsl,qman-channel-id = <0x800>;
++			};
++
++			fm1mac9: ethernet@f0000 {
++				cell-index = <0>;
++				compatible = "fsl,fman-memac";
++				reg = <0xf0000 0x1000>;
++				fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>;
++			};
++
++			mdio@f1000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xf1000 0x1000>;
++			};
++
++			ptp_timer0: rtc@fe000 {
++				compatible = "fsl,fman-rtc";
++				reg = <0xfe000 0x1000>;
++			};
++		};
++
++		dspi: dspi@2100000 {
++			compatible = "fsl,ls1046a-dspi", "fsl,ls1021a-v1.0-dspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2100000 0x0 0x10000>;
++			interrupts = <0 64 0x4>;
++			clock-names = "dspi";
++			clocks = <&clockgen 4 1>;
++			spi-num-chipselects = <5>;
++			big-endian;
++			status = "disabled";
++		};
++
++		qspi: quadspi@1550000 {
++			compatible = "fsl,ls1046a-qspi", "fsl,ls1021a-qspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x1550000 0x0 0x10000>,
++				<0x0 0x40000000 0x0 0x10000000>;
++			reg-names = "QuadSPI", "QuadSPI-memory";
++			interrupts = <0 99 0x4>;
++			clock-names = "qspi_en", "qspi";
++			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++			big-endian;
++			fsl,qspi-has-second-chip;
++			status = "disabled";
++		};
++
++		i2c0: i2c@2180000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2180000 0x0 0x10000>;
++			interrupts = <0 56 0x4>;
++			clock-names = "i2c";
++			clocks = <&clockgen 4 1>;
++			dmas = <&edma0 1 39>,
++			       <&edma0 1 38>;
++			dma-names = "tx", "rx";
++			status = "disabled";
++		};
++
++		i2c1: i2c@2190000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2190000 0x0 0x10000>;
++			interrupts = <0 57 0x4>;
++			clock-names = "i2c";
++			clocks = <&clockgen 4 1>;
++			status = "disabled";
++		};
++
++		i2c2: i2c@21a0000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x21a0000 0x0 0x10000>;
++			interrupts = <0 58 0x4>;
++			clock-names = "i2c";
++			clocks = <&clockgen 4 1>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@21b0000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x21b0000 0x0 0x10000>;
++			interrupts = <0 59 0x4>;
++			clock-names = "i2c";
++			clocks = <&clockgen 4 1>;
++			status = "disabled";
++		};
++
++		duart0: serial@21c0500 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x00 0x21c0500 0x0 0x100>;
++			interrupts = <0 54 0x4>;
++			clocks = <&clockgen 4 1>;
++		};
++
++		duart1: serial@21c0600 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x00 0x21c0600 0x0 0x100>;
++			interrupts = <0 54 0x4>;
++			clocks = <&clockgen 4 1>;
++		};
++
++		duart2: serial@21d0500 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x0 0x21d0500 0x0 0x100>;
++			interrupts = <0 55 0x4>;
++			clocks = <&clockgen 4 1>;
++		};
++
++		duart3: serial@21d0600 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x0 0x21d0600 0x0 0x100>;
++			interrupts = <0 55 0x4>;
++			clocks = <&clockgen 4 1>;
++		};
++
++		gpio0: gpio@2300000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2300000 0x0 0x10000>;
++			interrupts = <0 66 0x4>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio1: gpio@2310000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2310000 0x0 0x10000>;
++			interrupts = <0 67 0x4>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio2: gpio@2320000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2320000 0x0 0x10000>;
++			interrupts = <0 68 0x4>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio3: gpio@2330000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2330000 0x0 0x10000>;
++			interrupts = <0 134 0x4>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		lpuart0: serial@2950000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2950000 0x0 0x1000>;
++			interrupts = <0 48 0x4>;
++			clocks = <&clockgen 0 0>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart1: serial@2960000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2960000 0x0 0x1000>;
++			interrupts = <0 49 0x4>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart2: serial@2970000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2970000 0x0 0x1000>;
++			interrupts = <0 50 0x4>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart3: serial@2980000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2980000 0x0 0x1000>;
++			interrupts = <0 51 0x4>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart4: serial@2990000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2990000 0x0 0x1000>;
++			interrupts = <0 52 0x4>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart5: serial@29a0000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x29a0000 0x0 0x1000>;
++			interrupts = <0 53 0x4>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		ftm0: ftm0@29d0000 {
++			compatible = "fsl,ftm-alarm";
++			reg = <0x0 0x29d0000 0x0 0x10000>;
++			interrupts = <0 86 0x4>;
++			big-endian;
++			rcpm-wakeup = <&rcpm 0x0 0x20000000>;
++			status = "okay";
++		};
++
++		wdog0: wdog@2ad0000 {
++			compatible = "fsl,ls1046a-wdt", "fsl,imx21-wdt";
++			reg = <0x0 0x2ad0000 0x0 0x10000>;
++			interrupts = <0 83 0x4>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "wdog";
++			big-endian;
++		};
++
++		edma0: edma@2c00000 {
++			#dma-cells = <2>;
++			compatible = "fsl,vf610-edma";
++			reg = <0x0 0x2c00000 0x0 0x10000>,
++			      <0x0 0x2c10000 0x0 0x10000>,
++			      <0x0 0x2c20000 0x0 0x10000>;
++			interrupts = <0 103 0x4>,
++				     <0 103 0x4>;
++			interrupt-names = "edma-tx", "edma-err";
++			dma-channels = <32>;
++			big-endian;
++			clock-names = "dmamux0", "dmamux1";
++			clocks = <&clockgen 4 1>,
++				 <&clockgen 4 1>;
++		};
++
++		usb0: usb3@2f00000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x2f00000 0x0 0x10000>;
++			interrupts = <0 60 0x4>;
++			dr_mode = "host";
++			configure-gfladj;
++			snps,dis_rxdet_inp3_quirk;
++		};
++
++		usb1: usb3@3000000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x3000000 0x0 0x10000>;
++			interrupts = <0 61 0x4>;
++			dr_mode = "host";
++			configure-gfladj;
++			snps,dis_rxdet_inp3_quirk;
++		};
++
++		usb2: usb3@3100000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x3100000 0x0 0x10000>;
++			interrupts = <0 63 0x4>;
++			dr_mode = "host";
++			configure-gfladj;
++			snps,dis_rxdet_inp3_quirk;
++		};
++
++		sata: sata@3200000 {
++			compatible = "fsl,ls1046a-ahci";
++			reg = <0x0 0x3200000 0x0 0x10000>;
++			interrupts = <0 69 0x4>;
++			clocks = <&clockgen 4 1>;
++		};
++
++		qdma: qdma@8380000 {
++			compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
++			reg = <0x0 0x838f000 0x0 0x11000 /* Controller regs */
++			       0x0 0x83a0000 0x0 0x40000>; /* Block regs */
++			interrupts = <0 152 0x4>,
++				     <0 39 0x4>;
++			interrupt-names = "qdma-error", "qdma-queue";
++			channels = <8>;
++			queues = <2>;
++			status-sizes = <64>;
++			queue-sizes = <64 64>;
++			big-endian;
++		};
++
++		msi1: msi-controller@1580000 {
++			compatible = "fsl,1s1046a-msi";
++			reg = <0x0 0x1580000 0x0 0x10000>;
++			msi-controller;
++			interrupts = <0 116 0x4>,
++				     <0 111 0x4>,
++				     <0 112 0x4>,
++				     <0 113 0x4>;
++		};
++
++		msi2: msi-controller@1590000 {
++			compatible = "fsl,1s1046a-msi";
++			reg = <0x0 0x1590000 0x0 0x10000>;
++			msi-controller;
++			interrupts = <0 126 0x4>,
++				     <0 121 0x4>,
++				     <0 122 0x4>,
++				     <0 123 0x4>;
++		};
++
++		msi3: msi-controller@15a0000 {
++			compatible = "fsl,1s1046a-msi";
++			reg = <0x0 0x15a0000 0x0 0x10000>;
++			msi-controller;
++			interrupts = <0 160 0x4>,
++				     <0 155 0x4>,
++				     <0 156 0x4>,
++				     <0 157 0x4>;
++		};
++
++		pcie@3400000 {
++			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
++			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <0 118 0x4>, /* controller interrupt */
++				     <0 117 0x4>; /* PME interrupt */
++			interrupt-names = "intr", "pme";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			num-lanes = <4>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&msi1>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
++					<0000 0 0 2 &gic 0 110 0x4>,
++					<0000 0 0 3 &gic 0 110 0x4>,
++					<0000 0 0 4 &gic 0 110 0x4>;
++		};
++
++		pcie@3500000 {
++			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
++			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <0 128 0x4>,
++				     <0 127 0x4>;
++			interrupt-names = "intr", "pme";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			num-lanes = <2>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&msi2>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
++					<0000 0 0 2 &gic 0 120 0x4>,
++					<0000 0 0 3 &gic 0 120 0x4>,
++					<0000 0 0 4 &gic 0 120 0x4>;
++		};
++
++		pcie@3600000 {
++			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
++			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <0 162 0x4>,
++				     <0 161 0x4>;
++			interrupt-names = "intr", "pme";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			num-lanes = <2>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&msi3>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
++					<0000 0 0 2 &gic 0 154 0x4>,
++					<0000 0 0 3 &gic 0 154 0x4>,
++					<0000 0 0 4 &gic 0 154 0x4>;
++		};
++	};
++
++	fsl,dpaa {
++		compatible = "fsl,ls1046a-dpaa", "simple-bus", "fsl,dpaa";
++		ethernet@0 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac1>;
++		};
++		ethernet@1 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac2>;
++		};
++		ethernet@2 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac3>;
++		};
++		ethernet@3 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac4>;
++		};
++		ethernet@4 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac5>;
++		};
++		ethernet@5 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac6>;
++		};
++		ethernet@8 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac9>;
++		};
++	};
++
++	qportals: qman-portals@500000000 {
++		   ranges = <0x0 0x5 0x00000000 0x8000000>;
++        };
++	bportals: bman-portals@508000000 {
++		   ranges = <0x0 0x5 0x08000000 0x8000000>;
++        };
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		bman_fbpr: bman-fbpr {
++			size = <0 0x1000000>;
++			alignment = <0 0x1000000>;
++		};
++		qman_fqd: qman-fqd {
++			size = <0 0x800000>;
++			alignment = <0 0x800000>;
++		};
++		qman_pfdr: qman-pfdr {
++			size = <0 0x2000000>;
++			alignment = <0 0x2000000>;
++		};
++	};
++};
++
++&fman0 {
++	/* offline - 1 */
++	port@82000 {
++		fsl,qman-channel-id = <0x809>;
++	};
++
++	/* tx - 10g - 2 */
++	port@a8000 {
++		fsl,qman-channel-id = <0x802>;
++	};
++	/* tx - 10g - 3 */
++	port@a9000 {
++		fsl,qman-channel-id = <0x803>;
++	};
++	/* tx - 1g - 2 */
++	port@aa000 {
++		fsl,qman-channel-id = <0x804>;
++	};
++	/* tx - 1g - 3 */
++	port@ab000 {
++		fsl,qman-channel-id = <0x805>;
++	};
++	/* tx - 1g - 4 */
++	port@ac000 {
++		fsl,qman-channel-id = <0x806>;
++	};
++	/* tx - 1g - 5 */
++	port@ad000 {
++		fsl,qman-channel-id = <0x807>;
++	};
++	/* tx - 10g - 0 */
++	port@b0000 {
++		fsl,qman-channel-id = <0x800>;
++	};
++	/* tx - 10g - 1 */
++	port@b1000 {
++		fsl,qman-channel-id = <0x801>;
++	};
++	/* offline - 2 */
++	port@83000 {
++		fsl,qman-channel-id = <0x80a>;
++	};
++	/* offline - 3 */
++	port@84000 {
++		fsl,qman-channel-id = <0x80b>;
++	};
++	/* offline - 4 */
++	port@85000 {
++		fsl,qman-channel-id = <0x80c>;
++	};
++	/* offline - 5 */
++	port@86000 {
++		fsl,qman-channel-id = <0x80d>;
++	};
++	/* offline - 6 */
++	port@87000 {
++		fsl,qman-channel-id = <0x80e>;
++	};
++};
++
++&bman_fbpr {
++	compatible = "fsl,bman-fbpr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++
++&qman_fqd {
++	compatible = "fsl,qman-fqd";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++
++&qman_pfdr {
++	compatible = "fsl,qman-pfdr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++
++/include/ "qoriq-qman1-portals.dtsi"
++/include/ "qoriq-bman1-portals.dtsi"

target/linux/layerscape/patches-4.4/3132-dts-ls1046a-add-LS1046ARDB-board-support.patch

@@ -0,0 +1,557 @@
+From feb12cb699adbac2d4619401c7ff4fcc2fc97b6c Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <[email protected]>
+Date: Mon, 26 Sep 2016 12:33:42 +0800
+Subject: [PATCH 132/141] dts/ls1046a: add LS1046ARDB board support
+
+commit e95a28cfd9a392fe5dc189a9ae097bbaaccd1228
+[context adjustment]
+
+Signed-off-by: Mingkai Hu <[email protected]>
+Integrated-by: Zhao Qiang <[email protected]>
+---
+ arch/arm64/boot/dts/freescale/Makefile            |    1 +
+ arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts |  198 +++++++++++++++++++++
+ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi    |  178 +++++++++++++-----
+ 3 files changed, 328 insertions(+), 49 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
+  
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+@@ -0,0 +1,198 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2016, Freescale Semiconductor
++ *
++ * Mingkai Hu <[email protected]>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "fsl-ls1046a.dtsi"
++
++/ {
++	model = "LS1046A RDB Board";
++	compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
++
++	aliases {
++		ethernet0 = &fm1mac3;
++		ethernet1 = &fm1mac4;
++		ethernet2 = &fm1mac5;
++		ethernet3 = &fm1mac6;
++		ethernet4 = &fm1mac9;
++		ethernet5 = &fm1mac10;
++	};
++};
++
++&i2c0 {
++	status = "okay";
++	ina220@40 {
++		compatible = "ti,ina220";
++		reg = <0x40>;
++		shunt-resistor = <1000>;
++	};
++	adt7461a@4c {
++		compatible = "adi,adt7461";
++		reg = <0x4c>;
++	};
++	eeprom@56 {
++		compatible = "at24,24c512";
++		reg = <0x52>;
++	};
++	eeprom@57 {
++		compatible = "at24,24c512";
++		reg = <0x53>;
++	};
++};
++
++&i2c3 {
++	status = "okay";
++	rtc@51 {
++		compatible = "nxp,pcf2129";
++		reg = <0x51>;
++	};
++};
++
++&ifc {
++	status = "okay";
++	#address-cells = <2>;
++	#size-cells = <1>;
++	/* NAND Flashe and CPLD on board */
++	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
++		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
++
++		nand@0,0 {
++			compatible = "fsl,ifc-nand";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			reg = <0x0 0x0 0x10000>;
++		};
++
++		cpld: board-control@2,0 {
++			compatible = "fsl,ls1046ardb-cpld";
++			reg = <0x2 0x0 0x0000100>;
++		};
++};
++
++&qspi {
++	num-cs = <2>;
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: s25fs128s@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++
++	qflash1: s25fs128s@1 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		reg = <1>;
++	};
++
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&duart1 {
++	status = "okay";
++};
++
++&fman0 {
++	ethernet@e4000 {
++		phy-handle = <&rgmii_phy1>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet@e6000 {
++		phy-handle = <&rgmii_phy2>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet@e8000 {
++		phy-handle = <&sgmii_phy1>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@ea000 {
++		phy-handle = <&sgmii_phy2>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@f0000 { /* 10GEC1 */
++		phy-handle = <&aqr106_phy>;
++		phy-connection-type = "xgmii";
++	};
++
++	ethernet@f2000 { /* 10GEC2 */
++		fixed-link = <0 1 10000 0 0>;
++		phy-connection-type = "xgmii";
++	};
++
++	mdio@fc000 {
++		rgmii_phy1: ethernet-phy@1 {
++			reg = <0x1>;
++		};
++		rgmii_phy2: ethernet-phy@2 {
++			reg = <0x2>;
++		};
++		sgmii_phy1: ethernet-phy@3 {
++			reg = <0x3>;
++		};
++		sgmii_phy2: ethernet-phy@4 {
++			reg = <0x4>;
++		};
++	};
++
++	mdio@fd000 {
++		aqr106_phy: ethernet-phy@1 {
++			compatible = "ethernet-phy-ieee802.3-c45";
++			interrupts = <0 131 4>;
++			reg = <0x0>;
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+@@ -51,13 +51,7 @@
+ 	#size-cells = <2>;
+ 
+ 	aliases {
+-		ethernet0 = &fm1mac1;
+-		ethernet1 = &fm1mac2;
+-		ethernet2 = &fm1mac3;
+-		ethernet3 = &fm1mac4;
+-		ethernet4 = &fm1mac5;
+-		ethernet5 = &fm1mac6;
+-		ethernet6 = &fm1mac9;
++		crypto = &crypto;
+ 	};
+ 
+ 	cpus {
+@@ -70,6 +64,7 @@
+ 			reg = <0x0>;
+ 			clocks = <&clockgen 1 0>;
+ 			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
+ 		};
+ 
+ 		cpu1: cpu@1 {
+@@ -78,6 +73,7 @@
+ 			reg = <0x1>;
+ 			clocks = <&clockgen 1 0>;
+ 			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
+ 		};
+ 
+ 		cpu2: cpu@2 {
+@@ -86,6 +82,7 @@
+ 			reg = <0x2>;
+ 			clocks = <&clockgen 1 0>;
+ 			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
+ 		};
+ 
+ 		cpu3: cpu@3 {
+@@ -94,6 +91,7 @@
+ 			reg = <0x3>;
+ 			clocks = <&clockgen 1 0>;
+ 			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
+ 		};
+ 
+ 		l2: l2-cache {
+@@ -101,6 +99,19 @@
+ 		};
+ 	};
+ 
++	idle-states {
++		entry-method = "arm,psci";
++
++		CPU_PH20: cpu-ph20 {
++			compatible = "arm,idle-state";
++			idle-state-name = "PH20";
++			arm,psci-suspend-param = <0x00010000>;
++			entry-latency-us = <1000>;
++			exit-latency-us = <1000>;
++			min-residency-us = <3000>;
++		};
++	};
++
+ 	memory@80000000 {
+ 		device_type = "memory";
+ 		reg = <0x0 0x80000000 0 0x80000000>;
+@@ -193,6 +204,49 @@
+ 			bus-width = <4>;
+ 		};
+ 
++		crypto: crypto@1700000 {
++			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
++				     "fsl,sec-v4.0";
++			fsl,sec-era = <8>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0x0 0x00 0x1700000 0x100000>;
++			reg = <0x00 0x1700000 0x0 0x100000>;
++			interrupts = <0 75 0x4>;
++
++			sec_jr0: jr@10000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x10000 0x10000>;
++				interrupts = <0 71 0x4>;
++			};
++
++			sec_jr1: jr@20000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x20000 0x10000>;
++				interrupts = <0 72 0x4>;
++			};
++
++			sec_jr2: jr@30000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x30000 0x10000>;
++				interrupts = <0 73 0x4>;
++			};
++
++			sec_jr3: jr@40000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x40000 0x10000>;
++				interrupts = <0 74 0x4>;
++			};
++		};
++
+ 		qman: qman@1880000 {
+ 			compatible = "fsl,qman";
+ 			reg = <0x00 0x1880000 0x0 0x10000>;
+@@ -490,6 +544,19 @@
+ 				fsl,qman-channel-id = <0x800>;
+ 			};
+ 
++			fman0_10g_rx1: port@91000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-port-10g-rx";
++				reg = <0x91000 0x1000>;
++			};
++
++			fman0_10g_tx1: port@b1000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-port-10g-tx";
++				reg = <0xb1000 0x1000>;
++				fsl,qman-channel-id = <0x801>;
++			};
++
+ 			fm1mac9: ethernet@f0000 {
+ 				cell-index = <0>;
+ 				compatible = "fsl,fman-memac";
+@@ -497,6 +564,13 @@
+ 				fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>;
+ 			};
+ 
++			fm1mac10: ethernet@f2000 {
++				cell-index = <1>;
++				compatible = "fsl,fman-memac";
++				reg = <0xf2000 0x1000>;
++				fsl,port-handles = <&fman0_10g_rx1 &fman0_10g_tx1>;
++			};
++
+ 			mdio@f1000 {
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+@@ -504,6 +578,13 @@
+ 				reg = <0xf1000 0x1000>;
+ 			};
+ 
++			mdio@f3000 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,fman-memac-mdio";
++				reg = <0xf3000 0x1000>;
++			};
++
+ 			ptp_timer0: rtc@fe000 {
+ 				compatible = "fsl,fman-rtc";
+ 				reg = <0xfe000 0x1000>;
+@@ -657,7 +738,7 @@
+ 			compatible = "fsl,ls1021a-lpuart";
+ 			reg = <0x0 0x2950000 0x0 0x1000>;
+ 			interrupts = <0 48 0x4>;
+-			clocks = <&clockgen 0 0>;
++			clocks = <&clockgen 4 0>;
+ 			clock-names = "ipg";
+ 			status = "disabled";
+ 		};
+@@ -712,7 +793,7 @@
+ 			reg = <0x0 0x29d0000 0x0 0x10000>;
+ 			interrupts = <0 86 0x4>;
+ 			big-endian;
+-			rcpm-wakeup = <&rcpm 0x0 0x20000000>;
++			rcpm-wakeup = <&rcpm 0x00020000 0x0>;
+ 			status = "okay";
+ 		};
+ 
+@@ -789,34 +870,34 @@
+ 			big-endian;
+ 		};
+ 
+-		msi1: msi-controller@1580000 {
+-			compatible = "fsl,1s1046a-msi";
+-			reg = <0x0 0x1580000 0x0 0x10000>;
++		msi: msi-controller@1580000 {
++			compatible = "fsl,ls1046a-msi";
++			#address-cells = <2>;
++			#size-cells = <2>;
++			ranges;
+ 			msi-controller;
+-			interrupts = <0 116 0x4>,
+-				     <0 111 0x4>,
+-				     <0 112 0x4>,
+-				     <0 113 0x4>;
+-		};
+ 
+-		msi2: msi-controller@1590000 {
+-			compatible = "fsl,1s1046a-msi";
+-			reg = <0x0 0x1590000 0x0 0x10000>;
+-			msi-controller;
+-			interrupts = <0 126 0x4>,
+-				     <0 121 0x4>,
+-				     <0 122 0x4>,
+-				     <0 123 0x4>;
+-		};
+-
+-		msi3: msi-controller@15a0000 {
+-			compatible = "fsl,1s1046a-msi";
+-			reg = <0x0 0x15a0000 0x0 0x10000>;
+-			msi-controller;
+-			interrupts = <0 160 0x4>,
+-				     <0 155 0x4>,
+-				     <0 156 0x4>,
+-				     <0 157 0x4>;
++			msi-bank@1580000 {
++				reg = <0x0 0x1580000 0x0 0x10000>;
++				interrupts = <0 116 0x4>,
++					     <0 111 0x4>,
++					     <0 112 0x4>,
++					     <0 113 0x4>;
++			};
++			msi-bank@1590000 {
++				reg = <0x0 0x1590000 0x0 0x10000>;
++				interrupts = <0 126 0x4>,
++					     <0 121 0x4>,
++					     <0 122 0x4>,
++					     <0 123 0x4>;
++			};
++			msi-bank@15a0000 {
++				reg = <0x0 0x15a0000 0x0 0x10000>;
++				interrupts = <0 160 0x4>,
++					     <0 155 0x4>,
++					     <0 156 0x4>,
++					     <0 157 0x4>;
++			};
+ 		};
+ 
+ 		pcie@3400000 {
+@@ -826,15 +907,16 @@
+ 			reg-names = "regs", "config";
+ 			interrupts = <0 118 0x4>, /* controller interrupt */
+ 				     <0 117 0x4>; /* PME interrupt */
+-			interrupt-names = "intr", "pme";
++			interrupt-names = "aer";
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
++			dma-coherent;
+ 			num-lanes = <4>;
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+ 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&msi1>;
++			msi-parent = <&msi>;
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 7>;
+ 			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
+@@ -850,15 +932,16 @@
+ 			reg-names = "regs", "config";
+ 			interrupts = <0 128 0x4>,
+ 				     <0 127 0x4>;
+-			interrupt-names = "intr", "pme";
++			interrupt-names = "aer";
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
++			dma-coherent;
+ 			num-lanes = <2>;
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
+ 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&msi2>;
++			msi-parent = <&msi>;
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 7>;
+ 			interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
+@@ -874,15 +957,16 @@
+ 			reg-names = "regs", "config";
+ 			interrupts = <0 162 0x4>,
+ 				     <0 161 0x4>;
+-			interrupt-names = "intr", "pme";
++			interrupt-names = "aer";
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
++			dma-coherent;
+ 			num-lanes = <2>;
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
+ 				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&msi3>;
++			msi-parent = <&msi>;
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 7>;
+ 			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
+@@ -894,14 +978,6 @@
+ 
+ 	fsl,dpaa {
+ 		compatible = "fsl,ls1046a-dpaa", "simple-bus", "fsl,dpaa";
+-		ethernet@0 {
+-			compatible = "fsl,dpa-ethernet";
+-			fsl,fman-mac = <&fm1mac1>;
+-		};
+-		ethernet@1 {
+-			compatible = "fsl,dpa-ethernet";
+-			fsl,fman-mac = <&fm1mac2>;
+-		};
+ 		ethernet@2 {
+ 			compatible = "fsl,dpa-ethernet";
+ 			fsl,fman-mac = <&fm1mac3>;
+@@ -922,6 +998,10 @@
+ 			compatible = "fsl,dpa-ethernet";
+ 			fsl,fman-mac = <&fm1mac9>;
+ 		};
++		ethernet@9 {
++			compatible = "fsl,dpa-ethernet";
++			fsl,fman-mac = <&fm1mac10>;
++		};
+ 	};
+ 
+ 	qportals: qman-portals@500000000 {

target/linux/layerscape/patches-4.4/3133-ls1046ardb-add-ITS-file.patch

@@ -0,0 +1,69 @@
+From 1a831d848c88f1bb9e599abc641a201be6b03ef7 Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <[email protected]>
+Date: Mon, 18 Apr 2016 15:38:24 +0800
+Subject: [PATCH 133/141] ls1046ardb: add ITS file
+
+Signed-off-by: Mingkai Hu <[email protected]>
+---
+ kernel-ls1046a-rdb.its |   55 ++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 55 insertions(+)
+ create mode 100644 kernel-ls1046a-rdb.its
+
+--- /dev/null
++++ b/kernel-ls1046a-rdb.its
+@@ -0,0 +1,55 @@
++/*
++ * Copyright (C) 2016, Freescale Semiconductor
++ *
++ * Mingkai Hu <[email protected]>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++/dts-v1/;
++
++/ {
++	description = "Image file for the LS1046A Linux Kernel";
++	#address-cells = <1>;
++
++	images {
++		kernel@1 {
++			description = "ARM64 Linux kernel";
++			data = /incbin/("./arch/arm64/boot/Image.gz");
++			type = "kernel";
++			arch = "arm64";
++			os = "linux";
++			compression = "gzip";
++			load = <0x80080000>;
++			entry = <0x80080000>;
++		};
++		fdt@1 {
++			description = "Flattened Device Tree blob";
++			data = /incbin/("./arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dtb");
++			type = "flat_dt";
++			arch = "arm64";
++			compression = "none";
++			load = <0x90000000>;
++		};
++		ramdisk@1 {
++			description = "LS1046 Ramdisk";
++                        data = /incbin/("./fsl-image-core-ls1046ardb-be.ext2.gz");
++			type = "ramdisk";
++			arch = "arm64";
++			os = "linux";
++			compression = "gzip";
++		};
++	};
++
++	configurations {
++		default = "config@1";
++		config@1 {
++			description = "Boot Linux kernel";
++			kernel = "kernel@1";
++			fdt = "fdt@1";
++			ramdisk = "ramdisk@1";
++		};
++	};
++};

target/linux/layerscape/patches-4.4/3143-armv8-aarch32-Execute-32-bit-Linux-for-ls1046a.patch

@@ -0,0 +1,32 @@
+From 887fd872791ce6e60045f4c6a97926365c6c817c Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <[email protected]>
+Date: Wed, 7 Dec 2016 00:47:35 +0800
+Subject: [PATCH] armv8: aarch32: Execute 32-bit Linux for ls1046a
+
+Signed-off-by: Yutang Jiang <[email protected]>
+---
+ arch/arm/mach-imx/mach-layerscape.c |    4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-imx/mach-layerscape.c b/arch/arm/mach-imx/mach-layerscape.c
+index b87a90a..cbc541e 100644
+--- a/arch/arm/mach-imx/mach-layerscape.c
++++ b/arch/arm/mach-imx/mach-layerscape.c
+@@ -12,11 +12,13 @@
+ #include "common.h"
+ 
+ static const char * const layerscape_dt_compat[] __initconst = {
+-	"fsl,ls1043a",
+ 	"fsl,ls1012a",
++	"fsl,ls1043a",
++	"fsl,ls1046a",
+ 	NULL,
+ };
+ 
+ DT_MACHINE_START(LAYERSCAPE, "Freescale LAYERSCAPE")
++	.smp		= smp_ops(layerscape_smp_ops),
+ 	.dt_compat	= layerscape_dt_compat,
+ MACHINE_END
+-- 
+1.7.9.5
+

target/linux/layerscape/patches-4.4/7126-net-phy-add-driver-for-aquantia-AQR106-107-phy.patch

@@ -0,0 +1,63 @@
+From 637a6e183edf302111b28461c0c98b9634b30437 Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <[email protected]>
+Date: Fri, 1 Apr 2016 17:11:10 +0800
+Subject: [PATCH 126/141] net: phy: add driver for aquantia AQR106/107 phy
+
+Signed-off-by: Mingkai Hu <[email protected]>
+---
+ drivers/net/phy/aquantia.c |   30 ++++++++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/drivers/net/phy/aquantia.c
++++ b/drivers/net/phy/aquantia.c
+@@ -21,6 +21,8 @@
+ #define PHY_ID_AQ1202	0x03a1b445
+ #define PHY_ID_AQ2104	0x03a1b460
+ #define PHY_ID_AQR105	0x03a1b4a2
++#define PHY_ID_AQR106	0x03a1b4d0
++#define PHY_ID_AQR107	0x03a1b4e0
+ #define PHY_ID_AQR405	0x03a1b4b0
+ 
+ #define PHY_AQUANTIA_FEATURES	(SUPPORTED_10000baseT_Full | \
+@@ -157,6 +159,32 @@ static struct phy_driver aquantia_driver
+ 	.driver		= { .owner = THIS_MODULE,},
+ },
+ {
++	.phy_id		= PHY_ID_AQR106,
++	.phy_id_mask	= 0xfffffff0,
++	.name		= "Aquantia AQR106",
++	.features	= PHY_AQUANTIA_FEATURES,
++	.flags		= PHY_HAS_INTERRUPT,
++	.aneg_done	= aquantia_aneg_done,
++	.config_aneg    = aquantia_config_aneg,
++	.config_intr	= aquantia_config_intr,
++	.ack_interrupt	= aquantia_ack_interrupt,
++	.read_status	= aquantia_read_status,
++	.driver		= { .owner = THIS_MODULE,},
++},
++{
++	.phy_id		= PHY_ID_AQR107,
++	.phy_id_mask	= 0xfffffff0,
++	.name		= "Aquantia AQR107",
++	.features	= PHY_AQUANTIA_FEATURES,
++	.flags		= PHY_HAS_INTERRUPT,
++	.aneg_done	= aquantia_aneg_done,
++	.config_aneg    = aquantia_config_aneg,
++	.config_intr	= aquantia_config_intr,
++	.ack_interrupt	= aquantia_ack_interrupt,
++	.read_status	= aquantia_read_status,
++	.driver		= { .owner = THIS_MODULE,},
++},
++{
+ 	.phy_id		= PHY_ID_AQR405,
+ 	.phy_id_mask	= 0xfffffff0,
+ 	.name		= "Aquantia AQR405",
+@@ -177,6 +205,8 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_AQ1202, 0xfffffff0 },
+ 	{ PHY_ID_AQ2104, 0xfffffff0 },
+ 	{ PHY_ID_AQR105, 0xfffffff0 },
++	{ PHY_ID_AQR106, 0xfffffff0 },
++	{ PHY_ID_AQR107, 0xfffffff0 },
+ 	{ PHY_ID_AQR405, 0xfffffff0 },
+ 	{ }
+ };

target/linux/layerscape/patches-4.4/8125-rtc-pcf2127-add-pcf2129-device-id.patch

@@ -0,0 +1,63 @@
+From 228d15f0c525d1d62540539ebb8d311feddb79f5 Mon Sep 17 00:00:00 2001
+From: Akinobu Mita <[email protected]>
+Date: Mon, 26 Sep 2016 11:26:11 +0800
+Subject: [PATCH 125/141] rtc: pcf2127: add pcf2129 device id
+
+commit e8bf83a7f9454ed1026f100139ebd10eace0e280
+[context adjustment]
+
+There are only a few differences between PCF2127 and PCF2129 (PCF2127
+has 512 bytes of general purpose SRAM and count-down timer).
+
+The rtc-pcf2127 driver currently doesn't use the PCF2127 specific
+functionality and Kconfig help text already says this driver supports
+PCF2127/29, so we can simply add pcf2129 to device id list.
+
+Signed-off-by: Akinobu Mita <[email protected]>
+Signed-off-by: Alexandre Belloni <[email protected]>
+Signed-off-by: Shaohui Xie <[email protected]>
+Integrated-by: Zhao Qiang <[email protected]>
+---
+ drivers/rtc/rtc-pcf2127.c |    8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/rtc/rtc-pcf2127.c
++++ b/drivers/rtc/rtc-pcf2127.c
+@@ -1,12 +1,12 @@
+ /*
+- * An I2C driver for the NXP PCF2127 RTC
++ * An I2C and SPI driver for the NXP PCF2127/29 RTC
+  * Copyright 2013 Til-Technologies
+  *
+  * Author: Renaud Cerrato <[email protected]>
+  *
+  * based on the other drivers in this same directory.
+  *
+- * http://www.nxp.com/documents/data_sheet/PCF2127AT.pdf
++ * Datasheet: http://cache.nxp.com/documents/data_sheet/PCF2127.pdf
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License version 2 as
+@@ -216,6 +216,7 @@ static int pcf2127_probe(struct i2c_clie
+ 
+ static const struct i2c_device_id pcf2127_id[] = {
+ 	{ "pcf2127", 0 },
++	{ "pcf2129", 0 },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(i2c, pcf2127_id);
+@@ -223,6 +224,7 @@ MODULE_DEVICE_TABLE(i2c, pcf2127_id);
+ #ifdef CONFIG_OF
+ static const struct of_device_id pcf2127_of_match[] = {
+ 	{ .compatible = "nxp,pcf2127" },
++	{ .compatible = "nxp,pcf2129" },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, pcf2127_of_match);
+@@ -240,5 +242,5 @@ static struct i2c_driver pcf2127_driver
+ module_i2c_driver(pcf2127_driver);
+ 
+ MODULE_AUTHOR("Renaud Cerrato <[email protected]>");
+-MODULE_DESCRIPTION("NXP PCF2127 RTC driver");
++MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver");
+ MODULE_LICENSE("GPL v2");

target/linux/layerscape/patches-4.4/8127-ls1046a-msi-Add-LS1046A-MSI-support.patch

@@ -0,0 +1,25 @@
+From 51ab89c787184d47dbff37c3c69ea2c82cc4749c Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <[email protected]>
+Date: Mon, 26 Sep 2016 12:13:56 +0800
+Subject: [PATCH 127/141] ls1046a/msi: Add LS1046A MSI support
+
+commit 2b5a00d46a8f8762b9f78b727eab6fc0e12f3fd7
+[context adjustment]
+
+Signed-off-by: Mingkai Hu <[email protected]>
+Integated-by: Zhao Qiang <[email protected]>
+Integated-by: Yutang Jiang <[email protected]>
+---
+ drivers/irqchip/irq-ls-scfg-msi.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/irqchip/irq-ls-scfg-msi.c
++++ b/drivers/irqchip/irq-ls-scfg-msi.c
+@@ -222,6 +222,7 @@ static const struct of_device_id ls_scfg
+ 	{ .compatible = "fsl,ls1012a-msi", },
+ 	{ .compatible = "fsl,1s1021a-msi", },
+ 	{ .compatible = "fsl,1s1043a-msi", },
++	{ .compatible = "fsl,ls1046a-msi", },
+ 	{},
+ };
+ 

target/linux/layerscape/patches-4.4/8128-pci-layerscape-add-LS1046A-support.patch

@@ -0,0 +1,38 @@
+From 5a95e58e58da417ca8a8f4ae11347ad9a66803cd Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <[email protected]>
+Date: Mon, 26 Sep 2016 12:17:36 +0800
+Subject: [PATCH 128/141] pci/layerscape: add LS1046A support
+
+commit a52797fe443a79c53d0b63c505c99f65264de8b7
+[context adjustment]
+
+Signed-off-by: Mingkai Hu <[email protected]>
+Integrated-by: Zhao Qiang <[email protected]>
+Integrated-by: Yutang Jiang <[email protected]>
+---
+ drivers/pci/host/pci-layerscape.c |    7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/pci/host/pci-layerscape.c
++++ b/drivers/pci/host/pci-layerscape.c
+@@ -205,6 +205,12 @@ static struct ls_pcie_drvdata ls1043_drv
+ 	.ops = &ls_pcie_host_ops,
+ };
+ 
++static struct ls_pcie_drvdata ls1046_drvdata = {
++	.lut_offset = 0x10000,
++	.ltssm_shift = 24,
++	.ops = &ls_pcie_host_ops,
++};
++
+ static struct ls_pcie_drvdata ls2080_drvdata = {
+ 	.lut_offset = 0x80000,
+ 	.ltssm_shift = 0,
+@@ -215,6 +221,7 @@ static const struct of_device_id ls_pcie
+ 	{ .compatible = "fsl,ls1012a-pcie", .data = &ls1012_drvdata },
+ 	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
+ 	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
++	{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
+ 	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
+ 	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
+ 	{ },

target/linux/layerscape/patches-4.4/8129-clk-qoriq-add-ls1046a-support.patch

@@ -0,0 +1,75 @@
+From 4fe33d4f4dc608fc5013390db58df06723282d01 Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <[email protected]>
+Date: Thu, 2 Jun 2016 11:15:58 +0800
+Subject: [PATCH 129/141] clk: qoriq: add ls1046a support
+
+Signed-off-by: Mingkai Hu <[email protected]>
+Integated-by: Yutang Jiang <[email protected]>
+---
+ drivers/clk/clk-qoriq.c |   41 +++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+--- a/drivers/clk/clk-qoriq.c
++++ b/drivers/clk/clk-qoriq.c
+@@ -275,6 +275,31 @@ static const struct clockgen_muxinfo ls1
+ 	},
+ };
+ 
++static const struct clockgen_muxinfo ls1046a_hwa1 = {
++	{
++		{},
++		{},
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
++		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
++	},
++};
++
++static const struct clockgen_muxinfo ls1046a_hwa2 = {
++	{
++		{},
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
++		{},
++		{},
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++	},
++};
++
+ static const struct clockgen_muxinfo t1023_hwa1 = {
+ 	{
+ 		{},
+@@ -508,6 +533,21 @@ static const struct clockgen_chipinfo ch
+ 		.flags = CG_PLL_8BIT,
+ 	},
+ 	{
++		.compat = "fsl,ls1046a-clockgen",
++		.init_periph = t2080_init_periph,
++		.cmux_groups = {
++			&t1040_cmux
++		},
++		.hwaccel = {
++			&ls1046a_hwa1, &ls1046a_hwa2
++		},
++		.cmux_to_group = {
++			0, -1
++		},
++		.pll_mask = 0x07,
++		.flags = CG_PLL_8BIT,
++	},
++	{
+ 		.compat = "fsl,ls2080a-clockgen",
+ 		.cmux_groups = {
+ 			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
+@@ -1285,6 +1325,7 @@ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qo
+ CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
+ 

target/linux/layerscape/patches-4.4/8130-ls1046a-sata-Add-LS1046A-sata-support.patch

@@ -0,0 +1,53 @@
+From 5cd461cd17c3e27e5501e499d5d865b60ee58257 Mon Sep 17 00:00:00 2001
+From: Gong Qianyu <[email protected]>
+Date: Mon, 26 Sep 2016 12:29:24 +0800
+Subject: [PATCH 130/141] ls1046a/sata: Add LS1046A sata support
+
+Signed-off-by: Gong Qianyu <[email protected]>
+Integrated-by: Zhao Qiang <[email protected]>
+Integated-by: Yutang Jiang <[email protected]>
+---
+ drivers/ata/ahci_qoriq.c |   13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/ata/ahci_qoriq.c
++++ b/drivers/ata/ahci_qoriq.c
+@@ -40,11 +40,16 @@
+ #define AHCI_PORT_PHY_5_CFG	0x192c96a4
+ #define AHCI_PORT_TRANS_CFG	0x08000025
+ 
++/* for ls1046a */
++#define LS1046A_PORT_PHY2	0x28184d1f
++#define LS1046A_PORT_PHY3	0x0e081509
++
+ #define SATA_ECC_DISABLE	0x00020000
+ 
+ enum ahci_qoriq_type {
+ 	AHCI_LS1021A,
+ 	AHCI_LS1043A,
++	AHCI_LS1046A,
+ 	AHCI_LS2080A,
+ };
+ 
+@@ -57,6 +62,7 @@ struct ahci_qoriq_priv {
+ static const struct of_device_id ahci_qoriq_of_match[] = {
+ 	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
+ 	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
++	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
+ 	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
+ 	{},
+ };
+@@ -158,6 +164,13 @@ static int ahci_qoriq_phy_init(struct ah
+ 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+ 		break;
+ 
++	case AHCI_LS1046A:
++		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
++		writel(LS1046A_PORT_PHY2, reg_base + PORT_PHY2);
++		writel(LS1046A_PORT_PHY3, reg_base + PORT_PHY3);
++		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
++		break;
++
+ 	case AHCI_LS1043A:
+ 	case AHCI_LS2080A:
+ 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);

target/linux/layerscape/patches-4.4/8134-pci-layerscape-add-LUT-DBG-reigster-offset-member.patch

@@ -0,0 +1,67 @@
+From 57d147c02fdcbae5e61ba322d51c5734f9511fd7 Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <[email protected]>
+Date: Mon, 26 Sep 2016 14:19:32 +0800
+Subject: [PATCH 134/141] pci/layerscape: add LUT DBG reigster offset member
+
+commit 59ab37d6f46356a5b9755fcec74b23616dfdd62f
+[doesn't apply pm part]
+
+Different chip have different LUT debug register offset,
+so add a member to avoid macro redifinition.
+
+Signed-off-by: Mingkai Hu <[email protected]>
+Integrated-by: Zhao Qiang <[email protected]>
+Integrated-by: Yutang Jiang <[email protected]>
+---
+ drivers/pci/host/pci-layerscape.c |    8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+--- a/drivers/pci/host/pci-layerscape.c
++++ b/drivers/pci/host/pci-layerscape.c
+@@ -41,6 +41,7 @@
+ struct ls_pcie_drvdata {
+ 	u32 lut_offset;
+ 	u32 ltssm_shift;
++	u32 lut_dbg;
+ 	struct pcie_host_ops *ops;
+ };
+ 
+@@ -134,7 +135,7 @@ static int ls_pcie_link_up(struct pcie_p
+ 	struct ls_pcie *pcie = to_ls_pcie(pp);
+ 	u32 state;
+ 
+-	state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
++	state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
+ 		 pcie->drvdata->ltssm_shift) &
+ 		 LTSSM_STATE_MASK;
+ 
+@@ -196,24 +197,28 @@ static struct ls_pcie_drvdata ls1021_drvdata = {
+ static struct ls_pcie_drvdata ls1012_drvdata = {
+ 	.lut_offset = 0xC0000,
+ 	.ltssm_shift = 24,
++	.lut_dbg = 0x7fc,
+ 	.ops = &ls_pcie_host_ops,
+ };
+ 
+ static struct ls_pcie_drvdata ls1043_drvdata = {
+ 	.lut_offset = 0x10000,
+ 	.ltssm_shift = 24,
++	.lut_dbg = 0x7fc,
+ 	.ops = &ls_pcie_host_ops,
+ };
+ 
+ static struct ls_pcie_drvdata ls1046_drvdata = {
+-	.lut_offset = 0x10000,
++	.lut_offset = 0x80000,
+ 	.ltssm_shift = 24,
++	.lut_dbg = 0x407fc,
+ 	.ops = &ls_pcie_host_ops,
+ };
+ 
+ static struct ls_pcie_drvdata ls2080_drvdata = {
+ 	.lut_offset = 0x80000,
+ 	.ltssm_shift = 0,
++	.lut_dbg = 0x7fc,
+ 	.ops = &ls_pcie_host_ops,
+ };
+ 

target/linux/layerscape/patches-4.4/8138-pci-layerscape-add-MSI-interrupt-support.patch

@@ -0,0 +1,259 @@
+From b0e74277164b17bb0d207ffe16056e13e558f6ba Mon Sep 17 00:00:00 2001
+From: Zhao Qiang <[email protected]>
+Date: Tue, 11 Oct 2016 16:25:07 +0800
+Subject: [PATCH 138/141] pci-layerscape: add MSI interrupt support
+
+Signed-off-by: Zhao Qiang <[email protected]>
+---
+ drivers/iommu/amd_iommu.c         |    5 +++--
+ drivers/iommu/arm-smmu.c          |   21 ++++++++++++++++++
+ drivers/iommu/iommu.c             |    8 +++----
+ drivers/pci/host/pci-layerscape.c |   43 +++++++++++++++++++++++++++++++++++++
+ drivers/pci/host/pci-layerscape.h |   17 +++++++++++++++
+ drivers/pci/quirks.c              |   19 +++++++++-------
+ drivers/pci/search.c              |    5 ++---
+ include/linux/pci.h               |    6 +++---
+ 8 files changed, 104 insertions(+), 20 deletions(-)
+ create mode 100644 drivers/pci/host/pci-layerscape.h
+
+--- a/drivers/iommu/amd_iommu.c
++++ b/drivers/iommu/amd_iommu.c
+@@ -222,8 +222,9 @@ static u16 get_alias(struct device *dev)
+ 	 */
+ 	if (pci_alias == devid &&
+ 	    PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
+-		pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
+-		pdev->dma_alias_devfn = ivrs_alias & 0xff;
++		pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID;
++		pdev->dma_alias_devid = PCI_DEVID(pdev->bus->number,
++						  ivrs_alias & 0xff);
+ 		pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
+ 			PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
+ 			dev_name(dev));
+--- a/drivers/iommu/arm-smmu.c
++++ b/drivers/iommu/arm-smmu.c
+@@ -45,6 +45,10 @@
+ 
+ #include <linux/amba/bus.h>
+ 
++#ifdef CONFIG_PCI_LAYERSCAPE
++#include <../drivers/pci/host/pci-layerscape.h>
++#endif
++
+ #include "io-pgtable.h"
+ 
+ /* Maximum number of stream IDs assigned to a single device */
+@@ -1352,6 +1356,23 @@ static int arm_smmu_init_platform_device
+ static int arm_smmu_add_device(struct device *dev)
+ {
+ 	struct iommu_group *group;
++#ifdef CONFIG_PCI_LAYERSCAPE
++	u16 sid;
++	u32 streamid;
++	struct pci_dev *pdev;
++	if (dev_is_pci(dev)) {
++		pdev = to_pci_dev(dev);
++
++		pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid);
++		streamid = set_pcie_streamid_translation(pdev, sid);
++		if (~streamid == 0) {
++			return -ENODEV;
++		}
++
++		pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID;
++		pdev->dma_alias_devid = streamid;
++	}
++#endif
+ 
+ 	group = iommu_group_get_for_dev(dev);
+ 	if (IS_ERR(group))
+--- a/drivers/iommu/iommu.c
++++ b/drivers/iommu/iommu.c
+@@ -686,10 +686,10 @@ static struct iommu_group *get_pci_alias
+ 			continue;
+ 
+ 		/* We alias them or they alias us */
+-		if (((pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVFN) &&
+-		     pdev->dma_alias_devfn == tmp->devfn) ||
+-		    ((tmp->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVFN) &&
+-		     tmp->dma_alias_devfn == pdev->devfn)) {
++		if (((pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVID) &&
++		     (pdev->dma_alias_devid & 0xff) == tmp->devfn) ||
++		    ((tmp->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVID) &&
++		     (tmp->dma_alias_devid & 0xff) == pdev->devfn)) {
+ 
+ 			group = get_pci_alias_group(tmp, devfns);
+ 			if (group) {
+--- a/drivers/pci/host/pci-layerscape.c
++++ b/drivers/pci/host/pci-layerscape.c
+@@ -37,6 +37,11 @@
+ 
+ /* PEX LUT registers */
+ #define PCIE_LUT_DBG		0x7FC /* PEX LUT Debug Register */
++#define PCIE_LUT_UDR(n)		(0x800 + (n) * 8)
++#define PCIE_LUT_LDR(n)		(0x804 + (n) * 8)
++#define PCIE_LUT_MASK_ALL	0xffff
++#define PCIE_LUT_DR_NUM		32
++#define PCIE_LUT_ENABLE		(1 << 31)
+ 
+ struct ls_pcie_drvdata {
+ 	u32 lut_offset;
+@@ -52,10 +57,30 @@ struct ls_pcie {
+ 	struct pcie_port pp;
+ 	const struct ls_pcie_drvdata *drvdata;
+ 	int index;
++	const u32 *avail_streamids;
++	int streamid_index;
+ };
+ 
+ #define to_ls_pcie(x)	container_of(x, struct ls_pcie, pp)
+ 
++u32 set_pcie_streamid_translation(struct pci_dev *pdev, u32 devid)
++{
++	u32 index, streamid;
++	struct pcie_port *pp = pdev->bus->sysdata;
++	struct ls_pcie *pcie = to_ls_pcie(pp);
++
++	if (!pcie->avail_streamids || !pcie->streamid_index)
++		return ~(u32)0;
++
++	index = --pcie->streamid_index;
++	/* mask is set as all zeroes, want to match all bits */
++	iowrite32((devid << 16), pcie->lut + PCIE_LUT_UDR(index));
++	streamid = be32_to_cpup(&pcie->avail_streamids[index]);
++	iowrite32(streamid | PCIE_LUT_ENABLE, pcie->lut + PCIE_LUT_LDR(index));
++
++	return streamid;
++}
++
+ static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
+ {
+ 	u32 header_type;
+@@ -283,10 +308,28 @@ static int __init ls_pcie_probe(struct p
+ 
+ 	pcie->drvdata = match->data;
+ 	pcie->lut = pcie->dbi + pcie->drvdata->lut_offset;
++	/* Disable LDR zero */
++	iowrite32(0, pcie->lut + PCIE_LUT_LDR(0));
+ 
+ 	if (!ls_pcie_is_bridge(pcie))
+ 		return -ENODEV;
+ 
++	if (of_device_is_compatible(pdev->dev.of_node, "fsl,ls2085a-pcie") ||
++	of_device_is_compatible(pdev->dev.of_node, "fsl,ls2080a-pcie") ||
++	of_device_is_compatible(pdev->dev.of_node, "fsl,ls1088a-pcie")) {
++		int len;
++		const u32 *prop;
++		struct device_node *np;
++
++		np = pdev->dev.of_node;
++		prop = (u32 *)of_get_property(np, "available-stream-ids", &len);
++		if (prop) {
++			pcie->avail_streamids = prop;
++			pcie->streamid_index = len/sizeof(u32);
++		} else
++			dev_err(&pdev->dev, "PCIe endpoint partitioning not possible\n");
++	}
++
+ 	ret = ls_add_pcie_port(&pcie->pp, pdev);
+ 	if (ret < 0)
+ 		return ret;
+--- /dev/null
++++ b/drivers/pci/host/pci-layerscape.h
+@@ -0,0 +1,17 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor.
++ *
++ * Author: Varun Sethi <[email protected]>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef _PCI_LAYERSCAPE_H
++#define _PCI_LAYERSCAPE_H
++
++/* function for setting up stream id to device id translation */
++u32 set_pcie_streamid_translation(struct pci_dev *pdev, u32 devid);
++
++#endif /* _PCI_LAYERSCAPE_H */
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -3589,8 +3589,9 @@ int pci_dev_specific_reset(struct pci_de
+ static void quirk_dma_func0_alias(struct pci_dev *dev)
+ {
+ 	if (PCI_FUNC(dev->devfn) != 0) {
+-		dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
+-		dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
++		dev->dma_alias_devid = PCI_DEVID(dev->bus->number,
++				       PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
++		dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID;
+ 	}
+ }
+ 
+@@ -3605,8 +3606,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_R
+ static void quirk_dma_func1_alias(struct pci_dev *dev)
+ {
+ 	if (PCI_FUNC(dev->devfn) != 1) {
+-		dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1);
+-		dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
++		dev->dma_alias_devid = PCI_DEVID(dev->bus->number,
++				       PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
++		dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID;
+ 	}
+ }
+ 
+@@ -3670,11 +3672,12 @@ static void quirk_fixed_dma_alias(struct
+ 
+ 	id = pci_match_id(fixed_dma_alias_tbl, dev);
+ 	if (id) {
+-		dev->dma_alias_devfn = id->driver_data;
+-		dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
++		dev->dma_alias_devid = PCI_DEVID(dev->bus->number,
++						 id->driver_data);
++		dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVID;
+ 		dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
+-			 PCI_SLOT(dev->dma_alias_devfn),
+-			 PCI_FUNC(dev->dma_alias_devfn));
++			 PCI_SLOT(dev->dma_alias_devid),
++			 PCI_FUNC(dev->dma_alias_devid));
+ 	}
+ }
+ 
+--- a/drivers/pci/search.c
++++ b/drivers/pci/search.c
+@@ -40,9 +40,8 @@ int pci_for_each_dma_alias(struct pci_de
+ 	 * If the device is broken and uses an alias requester ID for
+ 	 * DMA, iterate over that too.
+ 	 */
+-	if (unlikely(pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVFN)) {
+-		ret = fn(pdev, PCI_DEVID(pdev->bus->number,
+-					 pdev->dma_alias_devfn), data);
++	if (unlikely(pdev->dev_flags & PCI_DEV_FLAGS_DMA_ALIAS_DEVID)) {
++		ret = fn(pdev, pdev->dma_alias_devid, data);
+ 		if (ret)
+ 			return ret;
+ 	}
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -172,8 +172,8 @@ enum pci_dev_flags {
+ 	PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
+ 	/* Flag for quirk use to store if quirk-specific ACS is enabled */
+ 	PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
+-	/* Flag to indicate the device uses dma_alias_devfn */
+-	PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
++	/* Flag to indicate the device uses dma_alias_devid */
++	PCI_DEV_FLAGS_DMA_ALIAS_DEVID = (__force pci_dev_flags_t) (1 << 4),
+ 	/* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
+ 	PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
+ 	/* Do not use bus resets for device */
+@@ -279,7 +279,7 @@ struct pci_dev {
+ 	u8		rom_base_reg;	/* which config register controls the ROM */
+ 	u8		pin;		/* which interrupt pin this device uses */
+ 	u16		pcie_flags_reg;	/* cached PCIe Capabilities Register */
+-	u8		dma_alias_devfn;/* devfn of DMA alias, if any */
++	u32		dma_alias_devid;/* devid of DMA alias */
+ 
+ 	struct pci_driver *driver;	/* which driver has allocated this device */
+ 	u64		dma_mask;	/* Mask of the bits of bus address this

target/linux/layerscape/patches-4.4/8142-drivers-mmc-Add-compatible-string-for-LS1046A.patch

@@ -0,0 +1,25 @@
+From 81c67bb120106c4fbd9b7191ab057b48e13e3e5e Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <[email protected]>
+Date: Tue, 8 Nov 2016 01:27:50 +0800
+Subject: [PATCH 142/142] drivers/mmc: Add compatible string for LS1046A
+
+Signed-off-by: Yutang Jiang <[email protected]>
+---
+ drivers/mmc/host/sdhci-of-esdhc.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
+index a04ed4e..1116d38 100644
+--- a/drivers/mmc/host/sdhci-of-esdhc.c
++++ b/drivers/mmc/host/sdhci-of-esdhc.c
+@@ -607,6 +607,7 @@ static int sdhci_esdhc_probe(struct platform_device *pdev)
+ 	    of_device_is_compatible(np, "fsl,p4080-esdhc") ||
+ 	    of_device_is_compatible(np, "fsl,p1020-esdhc") ||
+ 	    of_device_is_compatible(np, "fsl,t1040-esdhc") ||
++		of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||
+ 	    of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
+ 		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+ 
+-- 
+1.7.9.5
+