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@@ -47,7 +47,7 @@
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clock-names = "ice_dbg";
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};
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- clk40m: oscillator@0 {
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+ clk40m: oscillator-40m {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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clock-output-names = "clkxtal";
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@@ -132,7 +132,7 @@
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memory-region = <&wmcpu_emi>;
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};
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- infracfg: infracfg@10001000 {
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+ infracfg: clock-controller@10001000 {
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compatible = "mediatek,mt7981-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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@@ -143,7 +143,7 @@
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reg = <0 0x10003000 0 0x10>;
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};
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- topckgen: topckgen@1001b000 {
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+ topckgen: clock-controller@1001b000 {
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compatible = "mediatek,mt7981-topckgen", "syscon";
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reg = <0 0x1001b000 0 0x1000>;
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#clock-cells = <1>;
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@@ -158,7 +158,7 @@
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status = "disabled";
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};
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- apmixedsys: apmixedsys@1001e000 {
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+ apmixedsys: clock-controller@1001e000 {
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compatible = "mediatek,mt7981-apmixedsys", "syscon";
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reg = <0 0x1001e000 0 0x1000>;
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#clock-cells = <1>;
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@@ -577,7 +577,7 @@
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};
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};
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- ethsys: syscon@15000000 {
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+ ethsys: clock-controller@15000000 {
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compatible = "mediatek,mt7981-ethsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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