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@@ -31,7 +31,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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};
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struct bcm2835_clock_data {
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-@@ -1252,7 +1253,7 @@ bcm2835_register_pll_divider(struct bcm2
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+@@ -1256,7 +1257,7 @@ bcm2835_register_pll_divider(struct bcm2
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init.num_parents = 1;
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init.name = divider_name;
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init.ops = &bcm2835_pll_divider_clk_ops;
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@@ -40,7 +40,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
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if (!divider)
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-@@ -1475,7 +1476,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1479,7 +1480,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLA_CORE,
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.load_mask = CM_PLLA_LOADCORE,
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.hold_mask = CM_PLLA_HOLDCORE,
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@@ -50,7 +50,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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[BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
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.name = "plla_per",
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.source_pll = "plla",
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-@@ -1483,7 +1485,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1487,7 +1489,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLA_PER,
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.load_mask = CM_PLLA_LOADPER,
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.hold_mask = CM_PLLA_HOLDPER,
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@@ -60,7 +60,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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[BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
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.name = "plla_dsi0",
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.source_pll = "plla",
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-@@ -1499,7 +1502,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1503,7 +1506,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLA_CCP2,
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.load_mask = CM_PLLA_LOADCCP2,
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.hold_mask = CM_PLLA_HOLDCCP2,
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@@ -70,7 +70,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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/* PLLB is used for the ARM's clock. */
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[BCM2835_PLLB] = REGISTER_PLL(
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-@@ -1523,7 +1527,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1527,7 +1531,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLB_ARM,
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.load_mask = CM_PLLB_LOADARM,
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.hold_mask = CM_PLLB_HOLDARM,
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@@ -80,7 +80,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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/*
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* PLLC is the core PLL, used to drive the core VPU clock.
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-@@ -1552,7 +1557,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1556,7 +1561,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLC_CORE0,
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.load_mask = CM_PLLC_LOADCORE0,
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.hold_mask = CM_PLLC_HOLDCORE0,
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@@ -90,7 +90,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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[BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
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.name = "pllc_core1",
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.source_pll = "pllc",
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-@@ -1560,7 +1566,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1564,7 +1570,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLC_CORE1,
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.load_mask = CM_PLLC_LOADCORE1,
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.hold_mask = CM_PLLC_HOLDCORE1,
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@@ -100,7 +100,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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[BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
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.name = "pllc_core2",
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.source_pll = "pllc",
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-@@ -1568,7 +1575,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1572,7 +1579,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLC_CORE2,
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.load_mask = CM_PLLC_LOADCORE2,
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.hold_mask = CM_PLLC_HOLDCORE2,
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@@ -110,7 +110,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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[BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
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.name = "pllc_per",
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.source_pll = "pllc",
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-@@ -1576,7 +1584,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1580,7 +1588,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLC_PER,
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.load_mask = CM_PLLC_LOADPER,
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.hold_mask = CM_PLLC_HOLDPER,
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@@ -120,7 +120,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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/*
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* PLLD is the display PLL, used to drive DSI display panels.
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-@@ -1605,7 +1614,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1609,7 +1618,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLD_CORE,
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.load_mask = CM_PLLD_LOADCORE,
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.hold_mask = CM_PLLD_HOLDCORE,
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@@ -130,7 +130,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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[BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
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.name = "plld_per",
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.source_pll = "plld",
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-@@ -1613,7 +1623,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1617,7 +1627,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLD_PER,
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.load_mask = CM_PLLD_LOADPER,
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.hold_mask = CM_PLLD_HOLDPER,
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@@ -140,7 +140,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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[BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
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.name = "plld_dsi0",
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.source_pll = "plld",
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-@@ -1658,7 +1669,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1662,7 +1673,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLH_RCAL,
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.load_mask = CM_PLLH_LOADRCAL,
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.hold_mask = 0,
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@@ -150,7 +150,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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[BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
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.name = "pllh_aux",
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.source_pll = "pllh",
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-@@ -1666,7 +1678,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1670,7 +1682,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLH_AUX,
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.load_mask = CM_PLLH_LOADAUX,
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.hold_mask = 0,
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@@ -160,7 +160,7 @@ Signed-off-by: Stephen Boyd <[email protected]>
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[BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
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.name = "pllh_pix",
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.source_pll = "pllh",
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-@@ -1674,7 +1687,8 @@ static const struct bcm2835_clk_desc clk
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+@@ -1678,7 +1691,8 @@ static const struct bcm2835_clk_desc clk
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.a2w_reg = A2W_PLLH_PIX,
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.load_mask = CM_PLLH_LOADPIX,
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.hold_mask = 0,
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