ramips: split mt7621 spi into a separate driver, increase maximum transfer size

Signed-off-by: Felix Fietkau <[email protected]>

SVN-Revision: 43807

target/linux/ramips/mt7620/config-3.14

@@ -164,6 +164,7 @@ CONFIG_SOC_MT7620=y
 # CONFIG_SOC_RT3883 is not set
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MT7621 is not set
 CONFIG_SPI_RT2880=y
 CONFIG_SWCONFIG=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y

target/linux/ramips/mt7621/config-3.14

@@ -177,7 +177,8 @@ CONFIG_SOC_MT7621=y
 # CONFIG_SOC_RT3883 is not set
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
-CONFIG_SPI_RT2880=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
 CONFIG_STOP_MACHINE=y
 CONFIG_SWCONFIG=y
 CONFIG_SYNC_R4K=y

target/linux/ramips/mt7628/config-3.14

@@ -164,7 +164,8 @@ CONFIG_SOC_MT7620=y
 # CONFIG_SOC_RT3883 is not set
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
-CONFIG_SPI_RT2880=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
 CONFIG_SWCONFIG=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_SYS_HAS_CPU_MIPS32_R2=y

target/linux/ramips/patches-3.14/0051-SPI-MIPS-ralink-add-mt7621-support.patch

@@ -1,346 +0,0 @@
-From 27b11d4f1888e1a3d6d75b46d4d5a4d86fc03891 Mon Sep 17 00:00:00 2001
-From: John Crispin <[email protected]>
-Date: Wed, 6 Aug 2014 10:53:40 +0200
-Subject: [PATCH 51/57] SPI: MIPS: ralink: add mt7621 support
-
-Signed-off-by: John Crispin <[email protected]>
----
- drivers/spi/spi-rt2880.c |  218 +++++++++++++++++++++++++++++++++++++++++++---
- 1 file changed, 205 insertions(+), 13 deletions(-)
-
---- a/drivers/spi/spi-rt2880.c
-+++ b/drivers/spi/spi-rt2880.c
-@@ -21,8 +21,13 @@
- #include <linux/io.h>
- #include <linux/reset.h>
- #include <linux/spi/spi.h>
-+#include <linux/of_device.h>
- #include <linux/platform_device.h>
- 
-+#include <ralink_regs.h>
-+
-+#define SPI_BPW_MASK(bits) BIT((bits) - 1)
-+
- #define DRIVER_NAME			"spi-rt2880"
- /* only one slave is supported*/
- #define RALINK_NUM_CHIPSELECTS		1
-@@ -63,6 +68,25 @@
- /* SPIFIFOSTAT register bit field */
- #define SPIFIFOSTAT_TXFULL		BIT(17)
- 
-+#define MT7621_SPI_TRANS	0x00
-+#define SPITRANS_BUSY		BIT(16)
-+#define MT7621_SPI_OPCODE	0x04
-+#define MT7621_SPI_DATA0	0x08
-+#define SPI_CTL_TX_RX_CNT_MASK	0xff
-+#define SPI_CTL_START		BIT(8)
-+#define MT7621_SPI_POLAR	0x38
-+#define MT7621_SPI_MASTER	0x28
-+#define MT7621_SPI_SPACE	0x3c
-+
-+struct rt2880_spi;
-+
-+struct rt2880_spi_ops {
-+	void (*init_hw)(struct rt2880_spi *rs);
-+	void (*set_cs)(struct rt2880_spi *rs, int enable);
-+	int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
-+	unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
-+};
-+
- struct rt2880_spi {
- 	struct spi_master	*master;
- 	void __iomem		*base;
-@@ -70,6 +94,8 @@ struct rt2880_spi {
- 	unsigned int		speed;
- 	struct clk		*clk;
- 	spinlock_t		lock;
-+
-+	struct rt2880_spi_ops	*ops;
- };
- 
- static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
-@@ -149,6 +175,17 @@ static int rt2880_spi_baudrate_set(struc
- 	return 0;
- }
- 
-+static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
-+{
-+/*	u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
-+
-+	// set default clock to hclk/5
-+	master &= ~(0xfff << 16);
-+	master |= 0x3 << 16;
-+*/
-+	return 0;
-+}
-+
- /*
-  * called only when no transfer is active on the bus
-  */
-@@ -164,7 +201,7 @@ rt2880_spi_setup_transfer(struct spi_dev
- 
- 	if (rs->speed != speed) {
- 		dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
--		rc = rt2880_spi_baudrate_set(spi, speed);
-+		rc = rs->ops->baudrate_set(spi, speed);
- 		if (rc)
- 			return rc;
- 	}
-@@ -180,6 +217,17 @@ static void rt2880_spi_set_cs(struct rt2
- 		rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
- }
- 
-+static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
-+{
-+	u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
-+
-+	if (enable)
-+		polar |= 1;
-+	else
-+		polar &= ~1;
-+	rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
-+}
-+
- static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
- {
- 	int i;
-@@ -198,8 +246,26 @@ static inline int rt2880_spi_wait_till_r
- 	return -ETIMEDOUT;
- }
- 
-+static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
-+{
-+	int i;
-+
-+	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
-+		u32 status;
-+
-+		status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
-+		if ((status & SPITRANS_BUSY) == 0) {
-+			return 0;
-+		}
-+		cpu_relax();
-+		udelay(1);
-+	}
-+
-+	return -ETIMEDOUT;
-+}
-+
- static unsigned int
--rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
-+rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
- {
- 	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
- 	unsigned count = 0;
-@@ -239,6 +305,100 @@ out:
- 	return count;
- }
- 
-+static unsigned int
-+mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
-+{
-+	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
-+	struct spi_transfer *next = NULL;
-+	const u8 *tx = xfer->tx_buf;
-+	u8 *rx = NULL;
-+	u32 trans;
-+	int len = xfer->len;
-+
-+	if (!tx)
-+		return 0;
-+
-+	if (!list_is_last(&xfer->transfer_list, list)) {
-+		next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
-+		rx = next->rx_buf;
-+	}
-+
-+	trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
-+	trans &= ~SPI_CTL_TX_RX_CNT_MASK;
-+
-+	if (tx) {
-+		u32 data0 = 0, opcode = 0;
-+
-+		switch (xfer->len) {
-+		case 8:
-+			data0 |= tx[7] << 24;
-+		case 7:
-+			data0 |= tx[6] << 16;
-+		case 6:
-+			data0 |= tx[5] << 8;
-+		case 5:
-+			data0 |= tx[4];
-+		case 4:
-+			opcode |= tx[3] << 8;
-+		case 3:
-+			opcode |= tx[2] << 16;
-+		case 2:
-+			opcode |= tx[1] << 24;
-+		case 1:
-+			opcode |= tx[0];
-+			break;
-+
-+		default:
-+			dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
-+			return -EINVAL;
-+		}
-+
-+		rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
-+		rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
-+		trans |= xfer->len;
-+	}
-+
-+	if (rx)
-+		trans |= (next->len << 4);
-+	rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
-+	trans |= SPI_CTL_START;
-+	rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
-+
-+	mt7621_spi_wait_till_ready(rs);
-+
-+	if (rx) {
-+		u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
-+		u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
-+
-+		switch (next->len) {
-+		case 8:
-+			rx[7] = (opcode >> 24) & 0xff;
-+		case 7:
-+			rx[6] = (opcode >> 16) & 0xff;
-+		case 6:
-+			rx[5] = (opcode >> 8) & 0xff;
-+		case 5:
-+			rx[4] = opcode & 0xff;
-+		case 4:
-+			rx[3] = (data0 >> 24) & 0xff;
-+		case 3:
-+			rx[2] = (data0 >> 16) & 0xff;
-+		case 2:
-+			rx[1] = (data0 >> 8) & 0xff;
-+		case 1:
-+			rx[0] = data0 & 0xff;
-+			break;
-+
-+		default:
-+			dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
-+			return -EINVAL;
-+		}
-+		len += next->len;
-+	}
-+
-+	return len;
-+}
-+
- static int rt2880_spi_transfer_one_message(struct spi_master *master,
- 					   struct spi_message *m)
- {
-@@ -280,25 +440,25 @@ static int rt2880_spi_transfer_one_messa
- 		}
- 
- 		if (!cs_active) {
--			rt2880_spi_set_cs(rs, 1);
-+			rs->ops->set_cs(rs, 1);
- 			cs_active = 1;
- 		}
- 
- 		if (t->len)
--			m->actual_length += rt2880_spi_write_read(spi, t);
-+			m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
- 
- 		if (t->delay_usecs)
- 			udelay(t->delay_usecs);
- 
- 		if (t->cs_change) {
--			rt2880_spi_set_cs(rs, 0);
-+			rs->ops->set_cs(rs, 0);
- 			cs_active = 0;
- 		}
- 	}
- 
- msg_done:
- 	if (cs_active)
--		rt2880_spi_set_cs(rs, 0);
-+		rs->ops->set_cs(rs, 0);
- 
- 	m->status = status;
- 	spi_finalize_current_message(master);
-@@ -334,8 +494,41 @@ static void rt2880_spi_reset(struct rt28
- 	rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
- }
- 
-+static void mt7621_spi_reset(struct rt2880_spi *rs)
-+{
-+	u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
-+
-+	master &= ~(0xfff << 16);
-+	master |= 3 << 16;
-+
-+	master |= 7 << 29;
-+	rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
-+}
-+
-+static struct rt2880_spi_ops spi_ops[] = {
-+	{
-+		.init_hw = rt2880_spi_reset,
-+		.set_cs = rt2880_spi_set_cs,
-+		.baudrate_set = rt2880_spi_baudrate_set,
-+		.write_read = rt2880_spi_write_read,
-+	}, {
-+		.init_hw = mt7621_spi_reset,
-+		.set_cs = mt7621_spi_set_cs,
-+		.baudrate_set = mt7621_spi_baudrate_set,
-+		.write_read = mt7621_spi_write_read,
-+	},
-+};
-+
-+static const struct of_device_id rt2880_spi_match[] = {
-+	{ .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
-+	{ .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, rt2880_spi_match);
-+
- static int rt2880_spi_probe(struct platform_device *pdev)
- {
-+        const struct of_device_id *match;
- 	struct spi_master *master;
- 	struct rt2880_spi *rs;
- 	unsigned long flags;
-@@ -344,6 +537,10 @@ static int rt2880_spi_probe(struct platf
- 	int status = 0;
- 	struct clk *clk;
- 
-+        match = of_match_device(rt2880_spi_match, &pdev->dev);
-+	if (!match)
-+		return -EINVAL;
-+
- 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	base = devm_ioremap_resource(&pdev->dev, r);
- 	if (IS_ERR(base))
-@@ -382,12 +579,13 @@ static int rt2880_spi_probe(struct platf
- 	rs->clk = clk;
- 	rs->master = master;
- 	rs->sys_freq = clk_get_rate(rs->clk);
-+	rs->ops = (struct rt2880_spi_ops *) match->data;
- 	dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
- 	spin_lock_irqsave(&rs->lock, flags);
- 
- 	device_reset(&pdev->dev);
- 
--	rt2880_spi_reset(rs);
-+	rs->ops->init_hw(rs);
- 
- 	return spi_register_master(master);
- }
-@@ -408,12 +606,6 @@ static int rt2880_spi_remove(struct plat
- 
- MODULE_ALIAS("platform:" DRIVER_NAME);
- 
--static const struct of_device_id rt2880_spi_match[] = {
--	{ .compatible = "ralink,rt2880-spi" },
--	{},
--};
--MODULE_DEVICE_TABLE(of, rt2880_spi_match);
--
- static struct platform_driver rt2880_spi_driver = {
- 	.driver = {
- 		.name = DRIVER_NAME,

target/linux/ramips/patches-3.14/0104-rt5350-spi-second-device.patch → target/linux/ramips/patches-3.14/0051-rt5350-spi-second-device.patch

@@ -1,8 +1,27 @@
+From 27b11d4f1888e1a3d6d75b46d4d5a4d86fc03891 Mon Sep 17 00:00:00 2001
+From: John Crispin <[email protected]>
+Date: Wed, 6 Aug 2014 10:53:40 +0200
+Subject: [PATCH 51/57] SPI: MIPS: ralink: add rt5350 dual SPI support
+
+Signed-off-by: John Crispin <[email protected]>
+Signed-off-by: Felix Fietkau <[email protected]>
+---
+ drivers/spi/spi-rt2880.c |  218 +++++++++++++++++++++++++++++++++++++++++++---
+ 1 file changed, 205 insertions(+), 13 deletions(-)
+
 --- a/drivers/spi/spi-rt2880.c
 +++ b/drivers/spi/spi-rt2880.c
-@@ -29,16 +29,17 @@
- #define SPI_BPW_MASK(bits) BIT((bits) - 1)
- 
+@@ -21,19 +21,25 @@
+ #include <linux/io.h>
+ #include <linux/reset.h>
+ #include <linux/spi/spi.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ 
++#include <ralink_regs.h>
++
++#define SPI_BPW_MASK(bits) BIT((bits) - 1)
++
  #define DRIVER_NAME			"spi-rt2880"
 -/* only one slave is supported*/
 -#define RALINK_NUM_CHIPSELECTS		1
@@ -25,7 +44,7 @@
  
  /* SPISTAT register bit field */
  #define SPISTAT_BUSY			BIT(0)
-@@ -68,6 +69,10 @@
+@@ -63,6 +69,19 @@
  /* SPIFIFOSTAT register bit field */
  #define SPIFIFOSTAT_TXFULL		BIT(17)
  
@@ -33,28 +52,28 @@
 +#define SPI1_POR			BIT(1)
 +#define SPI0_POR			BIT(0)
 +
- #define MT7621_SPI_TRANS	0x00
- #define SPITRANS_BUSY		BIT(16)
- #define MT7621_SPI_OPCODE	0x04
-@@ -78,13 +83,16 @@
- #define MT7621_SPI_MASTER	0x28
- #define MT7621_SPI_SPACE	0x3c
- 
 +#define RT2880_SPI_MODE_BITS	(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
 +
- struct rt2880_spi;
- 
- struct rt2880_spi_ops {
- 	void (*init_hw)(struct rt2880_spi *rs);
--	void (*set_cs)(struct rt2880_spi *rs, int enable);
-+	void (*set_cs)(struct spi_device *spi, int enable);
- 	int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
- 	unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
++struct rt2880_spi;
++
++struct rt2880_spi_ops {
++	void (*init_hw)(struct rt2880_spi *rs);
 +	int num_cs;
++};
++
+ struct rt2880_spi {
+ 	struct spi_master	*master;
+ 	void __iomem		*base;
+@@ -70,6 +89,8 @@ struct rt2880_spi {
+ 	unsigned int		speed;
+ 	struct clk		*clk;
+ 	spinlock_t		lock;
++
++	struct rt2880_spi_ops	*ops;
  };
  
- struct rt2880_spi {
-@@ -141,6 +149,7 @@ static inline void rt2880_spi_clrbits(st
+ static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
+@@ -115,6 +136,7 @@ static inline void rt2880_spi_clrbits(st
  
  static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
  {
@@ -62,7 +81,7 @@
  	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
  	u32 rate;
  	u32 prescale;
-@@ -168,9 +177,9 @@ static int rt2880_spi_baudrate_set(struc
+@@ -142,9 +164,9 @@ static int rt2880_spi_baudrate_set(struc
  	prescale = ilog2(rate / 2);
  	dev_dbg(&spi->dev, "prescale:%u\n", prescale);
  
@@ -74,7 +93,7 @@
  	rs->speed = speed;
  	return 0;
  }
-@@ -194,7 +203,8 @@ rt2880_spi_setup_transfer(struct spi_dev
+@@ -157,7 +179,8 @@ rt2880_spi_setup_transfer(struct spi_dev
  {
  	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
  	unsigned int speed = spi->max_speed_hz;
@@ -84,7 +103,7 @@
  
  	if ((t != NULL) && t->speed_hz)
  		speed = t->speed_hz;
-@@ -206,19 +216,61 @@ rt2880_spi_setup_transfer(struct spi_dev
+@@ -169,25 +192,68 @@ rt2880_spi_setup_transfer(struct spi_dev
  			return rc;
  	}
  
@@ -143,17 +162,6 @@
 +		rt2880_spi_setbits(rs, RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);
  }
  
--static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
-+static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
- {
-+	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
- 	u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
- 
- 	if (enable)
-@@ -228,14 +280,16 @@ static void mt7621_spi_set_cs(struct rt2
- 	rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
- }
- 
 -static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
 +static inline int rt2880_spi_wait_till_ready(struct spi_device *spi)
  {
@@ -169,26 +177,19 @@
  		if ((status & SPISTAT_BUSY) == 0)
  			return 0;
  
-@@ -246,8 +300,9 @@ static inline int rt2880_spi_wait_till_r
- 	return -ETIMEDOUT;
+@@ -199,9 +265,10 @@ static inline int rt2880_spi_wait_till_r
  }
  
--static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
-+static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
- {
-+	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
- 	int i;
- 
- 	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
-@@ -268,6 +323,7 @@ static unsigned int
- rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
+ static unsigned int
+-rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
++rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
  {
  	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 +	int cs = spi->chip_select;
  	unsigned count = 0;
  	u8 *rx = xfer->rx_buf;
  	const u8 *tx = xfer->tx_buf;
-@@ -279,9 +335,9 @@ rt2880_spi_write_read(struct spi_device 
+@@ -213,9 +280,9 @@ rt2880_spi_write_read(struct spi_device 
  
  	if (tx) {
  		for (count = 0; count < xfer->len; count++) {
@@ -201,7 +202,7 @@
  			if (err) {
  				dev_err(&spi->dev, "TX failed, err=%d\n", err);
  				goto out;
-@@ -291,13 +347,13 @@ rt2880_spi_write_read(struct spi_device 
+@@ -225,13 +292,13 @@ rt2880_spi_write_read(struct spi_device 
  
  	if (rx) {
  		for (count = 0; count < xfer->len; count++) {
@@ -218,42 +219,37 @@
  		}
  	}
  
-@@ -364,7 +420,7 @@ mt7621_spi_write_read(struct spi_device 
- 	trans |= SPI_CTL_START;
- 	rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
- 
--	mt7621_spi_wait_till_ready(rs);
-+	mt7621_spi_wait_till_ready(spi);
- 
- 	if (rx) {
- 		u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
-@@ -440,7 +496,7 @@ static int rt2880_spi_transfer_one_messa
+@@ -280,25 +347,25 @@ static int rt2880_spi_transfer_one_messa
  		}
  
  		if (!cs_active) {
--			rs->ops->set_cs(rs, 1);
-+			rs->ops->set_cs(spi, 1);
+-			rt2880_spi_set_cs(rs, 1);
++			rt2880_spi_set_cs(spi, 1);
  			cs_active = 1;
  		}
  
-@@ -451,14 +507,14 @@ static int rt2880_spi_transfer_one_messa
+ 		if (t->len)
+-			m->actual_length += rt2880_spi_write_read(spi, t);
++			m->actual_length += rt2880_spi_write_read(spi, &m->transfers, t);
+ 
+ 		if (t->delay_usecs)
  			udelay(t->delay_usecs);
  
  		if (t->cs_change) {
--			rs->ops->set_cs(rs, 0);
-+			rs->ops->set_cs(spi, 0);
+-			rt2880_spi_set_cs(rs, 0);
++			rt2880_spi_set_cs(spi, 0);
  			cs_active = 0;
  		}
  	}
  
  msg_done:
  	if (cs_active)
--		rs->ops->set_cs(rs, 0);
-+		rs->ops->set_cs(spi, 0);
+-		rt2880_spi_set_cs(rs, 0);
++		rt2880_spi_set_cs(spi, 0);
  
  	m->status = status;
  	spi_finalize_current_message(master);
-@@ -471,7 +527,7 @@ static int rt2880_spi_setup(struct spi_d
+@@ -311,7 +378,7 @@ static int rt2880_spi_setup(struct spi_d
  	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
  
  	if ((spi->max_speed_hz == 0) ||
@@ -262,7 +258,7 @@
  		spi->max_speed_hz = (rs->sys_freq / 2);
  
  	if (spi->max_speed_hz < (rs->sys_freq / 128)) {
-@@ -488,10 +544,25 @@ static int rt2880_spi_setup(struct spi_d
+@@ -328,14 +395,47 @@ static int rt2880_spi_setup(struct spi_d
  
  static void rt2880_spi_reset(struct rt2880_spi *rs)
  {
@@ -272,8 +268,8 @@
  			 SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
 -	rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 +	rt2880_spi_write(rs, RAMIPS_SPI_CTL(0), SPICTL_HIZSDO | SPICTL_SPIENA);
-+}
-+
+ }
+ 
 +static void rt5350_spi_reset(struct rt2880_spi *rs)
 +{
 +	int cs;
@@ -287,60 +283,45 @@
 +				 SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
 +		rt2880_spi_write(rs, RAMIPS_SPI_CTL(cs), SPICTL_HIZSDO | SPICTL_SPIENA);
 +	}
- }
- 
- static void mt7621_spi_reset(struct rt2880_spi *rs)
-@@ -511,24 +582,33 @@ static struct rt2880_spi_ops spi_ops[] =
- 		.set_cs = rt2880_spi_set_cs,
- 		.baudrate_set = rt2880_spi_baudrate_set,
- 		.write_read = rt2880_spi_write_read,
++}
++
++static struct rt2880_spi_ops spi_ops[] = {
++	{
++		.init_hw = rt2880_spi_reset,
 +		.num_cs = 1,
 +	}, {
 +		.init_hw = rt5350_spi_reset,
-+		.set_cs = rt2880_spi_set_cs,
-+		.baudrate_set = rt2880_spi_baudrate_set,
-+		.write_read = rt2880_spi_write_read,
 +		.num_cs = 2,
- 	}, {
- 		.init_hw = mt7621_spi_reset,
- 		.set_cs = mt7621_spi_set_cs,
- 		.baudrate_set = mt7621_spi_baudrate_set,
- 		.write_read = mt7621_spi_write_read,
-+		.num_cs = 1,
- 	},
- };
- 
- static const struct of_device_id rt2880_spi_match[] = {
- 	{ .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
--	{ .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
++	},
++};
++
++static const struct of_device_id rt2880_spi_match[] = {
++	{ .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
 +	{ .compatible = "ralink,rt5350-spi", .data = &spi_ops[1]},
-+	{ .compatible = "ralink,mt7621-spi", .data = &spi_ops[2] },
- 	{},
- };
- MODULE_DEVICE_TABLE(of, rt2880_spi_match);
- 
++	{},
++};
++MODULE_DEVICE_TABLE(of, rt2880_spi_match);
++
  static int rt2880_spi_probe(struct platform_device *pdev)
  {
--        const struct of_device_id *match;
 +	const struct of_device_id *match;
  	struct spi_master *master;
  	struct rt2880_spi *rs;
  	unsigned long flags;
-@@ -536,10 +616,12 @@ static int rt2880_spi_probe(struct platf
+@@ -343,6 +443,12 @@ static int rt2880_spi_probe(struct platf
  	struct resource *r;
  	int status = 0;
  	struct clk *clk;
 +	struct rt2880_spi_ops *ops;
- 
--        match = of_match_device(rt2880_spi_match, &pdev->dev);
++
 +	match = of_match_device(rt2880_spi_match, &pdev->dev);
- 	if (!match)
- 		return -EINVAL;
++	if (!match)
++		return -EINVAL;
 +	ops = (struct rt2880_spi_ops *)match->data;
  
  	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  	base = devm_ioremap_resource(&pdev->dev, r);
-@@ -563,14 +645,13 @@ static int rt2880_spi_probe(struct platf
+@@ -366,14 +472,13 @@ static int rt2880_spi_probe(struct platf
  		return -ENOMEM;
  	}
  
@@ -357,12 +338,31 @@
  
  	dev_set_drvdata(&pdev->dev, master);
  
-@@ -579,7 +660,7 @@ static int rt2880_spi_probe(struct platf
+@@ -382,12 +487,13 @@ static int rt2880_spi_probe(struct platf
  	rs->clk = clk;
  	rs->master = master;
  	rs->sys_freq = clk_get_rate(rs->clk);
--	rs->ops = (struct rt2880_spi_ops *) match->data;
 +	rs->ops = ops;
  	dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
  	spin_lock_irqsave(&rs->lock, flags);
  
+ 	device_reset(&pdev->dev);
+ 
+-	rt2880_spi_reset(rs);
++	rs->ops->init_hw(rs);
+ 
+ 	return spi_register_master(master);
+ }
+@@ -408,12 +514,6 @@ static int rt2880_spi_remove(struct plat
+ 
+ MODULE_ALIAS("platform:" DRIVER_NAME);
+ 
+-static const struct of_device_id rt2880_spi_match[] = {
+-	{ .compatible = "ralink,rt2880-spi" },
+-	{},
+-};
+-MODULE_DEVICE_TABLE(of, rt2880_spi_match);
+-
+ static struct platform_driver rt2880_spi_driver = {
+ 	.driver = {
+ 		.name = DRIVER_NAME,

target/linux/ramips/patches-3.14/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch

@@ -0,0 +1,343 @@
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -396,6 +396,12 @@ config SPI_RT2880
+ 	help
+ 	  This selects a driver for the Ralink RT288x/RT305x SPI Controller.
+ 
++config SPI_MT7621
++	tristate "MediaTek MT7621 SPI Controller"
++	depends on RALINK
++	help
++	  This selects a driver for the MediaTek MT7621 SPI Controller.
++
+ config SPI_S3C24XX
+ 	tristate "Samsung S3C24XX series SPI"
+ 	depends on ARCH_S3C24XX
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_LM70_LLP)		+= spi-lm70l
+ obj-$(CONFIG_SPI_MPC512x_PSC)		+= spi-mpc512x-psc.o
+ obj-$(CONFIG_SPI_MPC52xx_PSC)		+= spi-mpc52xx-psc.o
+ obj-$(CONFIG_SPI_MPC52xx)		+= spi-mpc52xx.o
++obj-$(CONFIG_SPI_MT7621)		+= spi-mt7621.o
+ obj-$(CONFIG_SPI_MXS)			+= spi-mxs.o
+ obj-$(CONFIG_SPI_NUC900)		+= spi-nuc900.o
+ obj-$(CONFIG_SPI_OC_TINY)		+= spi-oc-tiny.o
+--- /dev/null
++++ b/drivers/spi/spi-mt7621.c
+@@ -0,0 +1,315 @@
++/*
++ * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
++ *
++ * Copyright (C) 2011 Sergiy <[email protected]>
++ * Copyright (C) 2011-2013 Gabor Juhos <[email protected]>
++ * Copyright (C) 2014-2015 Felix Fietkau <[email protected]>
++ *
++ * Some parts are based on spi-orion.c:
++ *   Author: Shadi Ammouri <[email protected]>
++ *   Copyright (C) 2007-2008 Marvell Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/reset.h>
++#include <linux/spi/spi.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/swab.h>
++
++#include <ralink_regs.h>
++
++#define SPI_BPW_MASK(bits) BIT((bits) - 1)
++
++#define DRIVER_NAME			"spi-mt7621"
++/* in usec */
++#define RALINK_SPI_WAIT_MAX_LOOP	2000
++
++/* SPISTAT register bit field */
++#define SPISTAT_BUSY			BIT(0)
++
++#define MT7621_SPI_TRANS	0x00
++#define SPITRANS_BUSY		BIT(16)
++
++#define MT7621_SPI_OPCODE	0x04
++#define MT7621_SPI_DATA0	0x08
++#define SPI_CTL_TX_RX_CNT_MASK	0xff
++#define SPI_CTL_START		BIT(8)
++
++#define MT7621_SPI_POLAR	0x38
++#define MT7621_SPI_MASTER	0x28
++#define MT7621_SPI_MOREBUF	0x2c
++#define MT7621_SPI_SPACE	0x3c
++
++#define RT2880_SPI_MODE_BITS	(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
++
++struct mt7621_spi;
++
++struct mt7621_spi {
++	struct spi_master	*master;
++	void __iomem		*base;
++	unsigned int		sys_freq;
++	unsigned int		speed;
++	struct clk		*clk;
++	spinlock_t		lock;
++
++	struct mt7621_spi_ops	*ops;
++};
++
++static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
++{
++	return spi_master_get_devdata(spi->master);
++}
++
++static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
++{
++	return ioread32(rs->base + reg);
++}
++
++static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
++{
++	iowrite32(val, rs->base + reg);
++}
++
++static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
++{
++	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
++	u32 polar = mt7621_spi_read(rs, MT7621_SPI_POLAR);
++
++	if (enable)
++		polar |= 1;
++	else
++		polar &= ~1;
++	mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
++}
++
++static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
++{
++	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
++	int i;
++
++	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
++		u32 status;
++
++		status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
++		if ((status & SPITRANS_BUSY) == 0) {
++			return 0;
++		}
++		cpu_relax();
++		udelay(1);
++	}
++
++	return -ETIMEDOUT;
++}
++
++static int mt7621_spi_transfer_one_message(struct spi_master *master,
++					   struct spi_message *m)
++{
++	struct mt7621_spi *rs = spi_master_get_devdata(master);
++	struct spi_device *spi = m->spi;
++	struct spi_transfer *t = NULL;
++	int status = 0;
++	int i, len = 0;
++	int rx_len = 0;
++	u32 data[9] = { 0 };
++	u32 val;
++
++	mt7621_spi_wait_till_ready(spi);
++
++	list_for_each_entry(t, &m->transfers, transfer_list) {
++		const u8 *buf = t->tx_buf;
++
++		if (t->rx_buf)
++			rx_len += t->len;
++
++		if (!buf)
++			continue;
++
++		if (WARN_ON(len + t->len > 36)) {
++			status = -EIO;
++			goto msg_done;
++		}
++
++		for (i = 0; i < t->len; i++, len++)
++			data[len / 4] |= buf[i] << (8 * (len & 3));
++	}
++
++	if (WARN_ON(rx_len > 32)) {
++		status = -EIO;
++		goto msg_done;
++	}
++
++	data[0] = swab32(data[0]);
++	if (len < 4)
++		data[0] >>= (4 - len) * 8;
++
++	for (i = 0; i < len; i += 4)
++		mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
++
++	val = (min_t(int, len, 4) * 8) << 24;
++	if (len > 4)
++		val |= (len - 4) * 8;
++	val |= (rx_len * 8) << 12;
++	mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
++
++	mt7621_spi_set_cs(spi, 1);
++
++	val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
++	val |= SPI_CTL_START;
++	mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
++
++	mt7621_spi_wait_till_ready(spi);
++
++	mt7621_spi_set_cs(spi, 0);
++
++	for (i = 0; i < rx_len; i += 4)
++		data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
++
++	m->actual_length = len + rx_len;
++
++	len = 0;
++	list_for_each_entry(t, &m->transfers, transfer_list) {
++		u8 *buf = t->rx_buf;
++
++		if (!buf)
++			continue;
++
++		for (i = 0; i < t->len; i++, len++)
++			buf[i] = data[len / 4] >> (8 * (len & 3));
++	}
++
++msg_done:
++	m->status = status;
++	spi_finalize_current_message(master);
++
++	return 0;
++}
++
++static int mt7621_spi_setup(struct spi_device *spi)
++{
++	return 0;
++}
++
++static void mt7621_spi_reset(struct mt7621_spi *rs)
++{
++	u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
++
++	master &= ~(0xfff << 16);
++	master |= 13 << 16;
++	master |= 7 << 29;
++	master |= 1 << 2;
++
++	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
++}
++
++static const struct of_device_id mt7621_spi_match[] = {
++	{ .compatible = "ralink,mt7621-spi" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mt7621_spi_match);
++
++static int mt7621_spi_probe(struct platform_device *pdev)
++{
++	const struct of_device_id *match;
++	struct spi_master *master;
++	struct mt7621_spi *rs;
++	unsigned long flags;
++	void __iomem *base;
++	struct resource *r;
++	int status = 0;
++	struct clk *clk;
++	struct mt7621_spi_ops *ops;
++
++	match = of_match_device(mt7621_spi_match, &pdev->dev);
++	if (!match)
++		return -EINVAL;
++	ops = (struct mt7621_spi_ops *)match->data;
++
++	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	base = devm_ioremap_resource(&pdev->dev, r);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	clk = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(clk)) {
++		dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
++			status);
++		return PTR_ERR(clk);
++	}
++
++	status = clk_prepare_enable(clk);
++	if (status)
++		return status;
++
++	master = spi_alloc_master(&pdev->dev, sizeof(*rs));
++	if (master == NULL) {
++		dev_dbg(&pdev->dev, "master allocation failed\n");
++		return -ENOMEM;
++	}
++
++	master->mode_bits = RT2880_SPI_MODE_BITS;
++
++	master->setup = mt7621_spi_setup;
++	master->transfer_one_message = mt7621_spi_transfer_one_message;
++	master->bits_per_word_mask = SPI_BPW_MASK(8);
++	master->dev.of_node = pdev->dev.of_node;
++	master->num_chipselect = 1;
++
++	dev_set_drvdata(&pdev->dev, master);
++
++	rs = spi_master_get_devdata(master);
++	rs->base = base;
++	rs->clk = clk;
++	rs->master = master;
++	rs->sys_freq = clk_get_rate(rs->clk);
++	rs->ops = ops;
++	dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
++	spin_lock_irqsave(&rs->lock, flags);
++
++	device_reset(&pdev->dev);
++
++	mt7621_spi_reset(rs);
++
++	return spi_register_master(master);
++}
++
++static int mt7621_spi_remove(struct platform_device *pdev)
++{
++	struct spi_master *master;
++	struct mt7621_spi *rs;
++
++	master = dev_get_drvdata(&pdev->dev);
++	rs = spi_master_get_devdata(master);
++
++	clk_disable(rs->clk);
++	spi_unregister_master(master);
++
++	return 0;
++}
++
++MODULE_ALIAS("platform:" DRIVER_NAME);
++
++static struct platform_driver mt7621_spi_driver = {
++	.driver = {
++		.name = DRIVER_NAME,
++		.owner = THIS_MODULE,
++		.of_match_table = mt7621_spi_match,
++	},
++	.probe = mt7621_spi_probe,
++	.remove = mt7621_spi_remove,
++};
++
++module_platform_driver(mt7621_spi_driver);
++
++MODULE_DESCRIPTION("MT7621 SPI driver");
++MODULE_AUTHOR("Felix Fietkau <[email protected]>");
++MODULE_LICENSE("GPL");

target/linux/ramips/rt288x/config-3.14

@@ -152,6 +152,7 @@ CONFIG_SOC_RT288X=y
 # CONFIG_SOC_RT3883 is not set
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MT7621 is not set
 CONFIG_SPI_RT2880=y
 CONFIG_SWCONFIG=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y

target/linux/ramips/rt305x/config-3.14

@@ -151,6 +151,7 @@ CONFIG_SOC_RT305X=y
 # CONFIG_SOC_RT3883 is not set
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MT7621 is not set
 CONFIG_SPI_RT2880=y
 CONFIG_SWCONFIG=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y

target/linux/ramips/rt3883/config-3.14

@@ -162,6 +162,7 @@ CONFIG_SLUB=y
 CONFIG_SOC_RT3883=y
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MT7621 is not set
 CONFIG_SPI_RT2880=y
 CONFIG_SWCONFIG=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y