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@@ -0,0 +1,153 @@
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+From 95fa6dbe58f286a8f87cb37b7516232eb678de2d Mon Sep 17 00:00:00 2001
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+From: Sander Vanheule <[email protected]>
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+Date: Sat, 9 Apr 2022 21:55:48 +0200
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+Subject: [PATCH 3/6] gpio: realtek-otto: Support per-cpu interrupts
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+
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+On SoCs with multiple cores, it is possible that the GPIO interrupt
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+controller supports assigning specific pins to one or more cores.
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+
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+IRQ balancing can be performed on a line-by-line basis if the parent
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+interrupt is routed to all available cores, which is the default upon
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+initialisation.
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+
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+Signed-off-by: Sander Vanheule <[email protected]>
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+Signed-off-by: Bartosz Golaszewski <[email protected]>
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+---
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+ drivers/gpio/gpio-realtek-otto.c | 75 +++++++++++++++++++++++++++++++-
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+ 1 file changed, 74 insertions(+), 1 deletion(-)
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+
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+--- a/drivers/gpio/gpio-realtek-otto.c
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++++ b/drivers/gpio/gpio-realtek-otto.c
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+@@ -1,6 +1,7 @@
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+ // SPDX-License-Identifier: GPL-2.0-only
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+
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+ #include <linux/gpio/driver.h>
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++#include <linux/cpumask.h>
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+ #include <linux/irq.h>
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+ #include <linux/minmax.h>
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+ #include <linux/mod_devicetable.h>
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+@@ -55,6 +56,8 @@
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+ struct realtek_gpio_ctrl {
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+ struct gpio_chip gc;
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+ void __iomem *base;
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++ void __iomem *cpumask_base;
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++ struct cpumask cpu_irq_maskable;
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+ raw_spinlock_t lock;
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+ u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK];
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+ u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK];
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+@@ -76,6 +79,11 @@ enum realtek_gpio_flags {
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+ * fields, and [BA, DC] for 2-bit fields.
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+ */
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+ GPIO_PORTS_REVERSED = BIT(1),
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++ /*
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++ * Interrupts can be enabled per cpu. This requires a secondary IO
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++ * range, where the per-cpu enable masks are located.
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++ */
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++ GPIO_INTERRUPTS_PER_CPU = BIT(2),
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+ };
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+
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+ static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)
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+@@ -250,14 +258,61 @@ static void realtek_gpio_irq_handler(str
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+ chained_irq_exit(irq_chip, desc);
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+ }
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+
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++static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl,
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++ unsigned int port, int cpu)
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++{
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++ return ctrl->cpumask_base + ctrl->port_offset_u8(port) +
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++ REALTEK_GPIO_PORTS_PER_BANK * cpu;
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++}
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++
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++static int realtek_gpio_irq_set_affinity(struct irq_data *data,
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++ const struct cpumask *dest, bool force)
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++{
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++ struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);
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++ unsigned int line = irqd_to_hwirq(data);
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++ unsigned int port = line / 8;
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++ unsigned int port_pin = line % 8;
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++ void __iomem *irq_cpu_mask;
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++ unsigned long flags;
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++ int cpu;
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++ u8 v;
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++
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++ if (!ctrl->cpumask_base)
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++ return -ENXIO;
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++
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++ raw_spin_lock_irqsave(&ctrl->lock, flags);
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++
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++ for_each_cpu(cpu, &ctrl->cpu_irq_maskable) {
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++ irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu);
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++ v = ioread8(irq_cpu_mask);
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++
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++ if (cpumask_test_cpu(cpu, dest))
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++ v |= BIT(port_pin);
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++ else
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++ v &= ~BIT(port_pin);
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++
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++ iowrite8(v, irq_cpu_mask);
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++ }
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++
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++ raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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++
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++ irq_data_update_effective_affinity(data, dest);
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++
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++ return 0;
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++}
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++
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+ static int realtek_gpio_irq_init(struct gpio_chip *gc)
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+ {
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+ struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);
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+ unsigned int port;
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++ int cpu;
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+
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+ for (port = 0; (port * 8) < gc->ngpio; port++) {
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+ realtek_gpio_write_imr(ctrl, port, 0, 0);
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+ realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0));
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++
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++ for_each_cpu(cpu, &ctrl->cpu_irq_maskable)
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++ iowrite8(GENMASK(7, 0), realtek_gpio_irq_cpu_mask(ctrl, port, cpu));
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+ }
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+
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+ return 0;
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+@@ -269,6 +324,7 @@ static struct irq_chip realtek_gpio_irq_
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+ .irq_mask = realtek_gpio_irq_mask,
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+ .irq_unmask = realtek_gpio_irq_unmask,
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+ .irq_set_type = realtek_gpio_irq_set_type,
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++ .irq_set_affinity = realtek_gpio_irq_set_affinity,
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+ };
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+
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+ static const struct of_device_id realtek_gpio_of_match[] = {
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+@@ -293,8 +349,10 @@ static int realtek_gpio_probe(struct pla
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+ unsigned int dev_flags;
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+ struct gpio_irq_chip *girq;
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+ struct realtek_gpio_ctrl *ctrl;
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++ struct resource *res;
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+ u32 ngpios;
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+- int err, irq;
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++ unsigned int nr_cpus;
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++ int cpu, err, irq;
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+
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+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
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+ if (!ctrl)
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+@@ -355,6 +413,21 @@ static int realtek_gpio_probe(struct pla
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+ girq->init_hw = realtek_gpio_irq_init;
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+ }
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+
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++ cpumask_clear(&ctrl->cpu_irq_maskable);
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++
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++ if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) {
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++ ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
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++ if (IS_ERR(ctrl->cpumask_base))
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++ return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base),
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++ "missing CPU IRQ mask registers");
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++
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++ nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK;
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++ nr_cpus = min(nr_cpus, num_present_cpus());
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++
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++ for (cpu = 0; cpu < nr_cpus; cpu++)
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++ cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable);
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++ }
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++
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+ return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
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+ }
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+
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Sander Vanheule