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sunxi: drop 6.1 support

Now that 6.6 is the default, remove the 6.1 config and the hack that
was required for the arm32 DTS dir change.

Signed-off-by: Zoltan HERPAI <[email protected]>
Zoltan HERPAI 1 year ago
parent
e8c7b8a388
commit
af87e5e9c1
29 changed files with 0 additions and 2809 deletions
Split View Show Diff Stats
  1. 0 524
      target/linux/sunxi/config-6.1
  2. 0 109
      target/linux/sunxi/cortexa53/config-6.1
  3. 0 26
      target/linux/sunxi/cortexa7/config-6.1
  4. 0 12
      target/linux/sunxi/cortexa8/config-6.1
  5. 0 2
      target/linux/sunxi/image/Makefile
  6. 0 38
      target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch
  7. 0 79
      target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch
  8. 0 188
      target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch
  9. 0 81
      target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch
  10. 0 305
      target/linux/sunxi/patches-6.1/005-v6.6-arm64-dts-allwinner-h616-Split-Orange-Pi-Zero-2-DT.patch
  11. 0 140
      target/linux/sunxi/patches-6.1/006-v6.6-arm64-dts-allwinner-h616-Add-OrangePi-Zero-3-board.patch
  12. 0 57
      target/linux/sunxi/patches-6.1/007-v6.7-arm64-dts-allwinner-h616-update-emac-for-Orange-Pi.patch
  13. 0 31
      target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch
  14. 0 98
      target/linux/sunxi/patches-6.1/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch
  15. 0 47
      target/linux/sunxi/patches-6.1/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch
  16. 0 79
      target/linux/sunxi/patches-6.1/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch
  17. 0 74
      target/linux/sunxi/patches-6.1/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch
  18. 0 126
      target/linux/sunxi/patches-6.1/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch
  19. 0 50
      target/linux/sunxi/patches-6.1/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch
  20. 0 68
      target/linux/sunxi/patches-6.1/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch
  21. 0 138
      target/linux/sunxi/patches-6.1/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch
  22. 0 30
      target/linux/sunxi/patches-6.1/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch
  23. 0 20
      target/linux/sunxi/patches-6.1/301-orangepi_pc2_usb_otg_to_host_key_power.patch
  24. 0 46
      target/linux/sunxi/patches-6.1/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch
  25. 0 292
      target/linux/sunxi/patches-6.1/410-sunxi-add-bananapi-p2-zero.patch
  26. 0 32
      target/linux/sunxi/patches-6.1/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch
  27. 0 35
      target/linux/sunxi/patches-6.1/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch
  28. 0 10
      target/linux/sunxi/patches-6.1/442-arm64-dts-orangepi-one-plus-enable-PWM.patch
  29. 0 72
      target/linux/sunxi/patches-6.1/450-arm64-dts-enable-wifi-on-pine64-boards.patch

+ 0 - 524
target/linux/sunxi/config-6.1
View File 

@@ -1,524 +0,0 @@
 
-# CONFIG_AHCI_SUNXI is not set
 
-CONFIG_ALIGNMENT_TRAP=y
 
-CONFIG_ARCH_32BIT_OFF_T=y
 
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
 
-CONFIG_ARCH_FORCE_MAX_ORDER=11
 
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 
-CONFIG_ARCH_KEEP_MEMBLOCK=y
 
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 
-CONFIG_ARCH_MULTIPLATFORM=y
 
-CONFIG_ARCH_MULTI_V6_V7=y
 
-CONFIG_ARCH_MULTI_V7=y
 
-CONFIG_ARCH_NR_GPIO=416
 
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
 
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
 
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
 
-CONFIG_ARCH_SUNXI=y
 
-CONFIG_ARCH_SUNXI_MC_SMP=y
 
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
-CONFIG_ARM=y
 
-CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
 
-CONFIG_ARM_APPENDED_DTB=y
 
-CONFIG_ARM_ARCH_TIMER=y
 
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
 
-CONFIG_ARM_ATAG_DTB_COMPAT=y
 
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
 
-CONFIG_ARM_CCI=y
 
-CONFIG_ARM_CCI400_COMMON=y
 
-CONFIG_ARM_CCI400_PORT_CTRL=y
 
-CONFIG_ARM_CPU_SUSPEND=y
 
-CONFIG_ARM_CRYPTO=y
 
-CONFIG_ARM_ERRATA_643719=y
 
-CONFIG_ARM_GIC=y
 
-CONFIG_ARM_HAS_SG_CHAIN=y
 
-CONFIG_ARM_HEAVY_MB=y
 
-CONFIG_ARM_L1_CACHE_SHIFT=6
 
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
 
-CONFIG_ARM_LPAE=y
 
-CONFIG_ARM_PATCH_IDIV=y
 
-CONFIG_ARM_PATCH_PHYS_VIRT=y
 
-CONFIG_ARM_PSCI=y
 
-CONFIG_ARM_PSCI_FW=y
 
-CONFIG_ARM_THUMB=y
 
-CONFIG_ARM_UNWIND=y
 
-CONFIG_ARM_VIRT_EXT=y
 
-CONFIG_ATA=y
 
-CONFIG_ATAGS=y
 
-CONFIG_AUTO_ZRELADDR=y
 
-CONFIG_AXP20X_POWER=y
 
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
 
-CONFIG_BACKLIGHT_PWM=y
 
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
 
-CONFIG_BLK_DEV_LOOP=y
 
-CONFIG_BLK_DEV_SD=y
 
-CONFIG_BLK_PM=y
 
-CONFIG_BOUNCE=y
 
-CONFIG_CACHE_L2X0=y
 
-CONFIG_CAN=y
 
-CONFIG_CLKSRC_MMIO=y
 
-CONFIG_CLK_SUNXI=y
 
-CONFIG_CLK_SUNXI_CLOCKS=y
 
-CONFIG_CLK_SUNXI_PRCM_SUN6I=y
 
-CONFIG_CLK_SUNXI_PRCM_SUN8I=y
 
-CONFIG_CLK_SUNXI_PRCM_SUN9I=y
 
-CONFIG_CLONE_BACKWARDS=y
 
-CONFIG_COMMON_CLK=y
 
-CONFIG_COMPAT_32BIT_TIME=y
 
-CONFIG_CONFIGFS_FS=y
 
-CONFIG_CONNECTOR=y
 
-CONFIG_CONSOLE_TRANSLATIONS=y
 
-CONFIG_COREDUMP=y
 
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 
-CONFIG_CPUFREQ_DT=y
 
-CONFIG_CPUFREQ_DT_PLATDEV=y
 
-CONFIG_CPU_32v6K=y
 
-CONFIG_CPU_32v7=y
 
-CONFIG_CPU_ABRT_EV7=y
 
-CONFIG_CPU_CACHE_V7=y
 
-CONFIG_CPU_CACHE_VIPT=y
 
-CONFIG_CPU_COPY_V6=y
 
-CONFIG_CPU_CP15=y
 
-CONFIG_CPU_CP15_MMU=y
 
-CONFIG_CPU_FREQ=y
 
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
 
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
 
-CONFIG_CPU_FREQ_GOV_COMMON=y
 
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
 
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
 
-CONFIG_CPU_FREQ_STAT=y
 
-CONFIG_CPU_HAS_ASID=y
 
-CONFIG_CPU_LITTLE_ENDIAN=y
 
-CONFIG_CPU_PABRT_V7=y
 
-CONFIG_CPU_PM=y
 
-CONFIG_CPU_RMAP=y
 
-CONFIG_CPU_SPECTRE=y
 
-CONFIG_CPU_THERMAL=y
 
-CONFIG_CPU_THUMB_CAPABLE=y
 
-CONFIG_CPU_TLB_V7=y
 
-CONFIG_CPU_V7=y
 
-CONFIG_CRC16=y
 
-CONFIG_CRC_T10DIF=y
 
-CONFIG_CRYPTO_CRC32=y
 
-CONFIG_CRYPTO_CRC32C=y
 
-CONFIG_CRYPTO_CRCT10DIF=y
 
-CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
 
-CONFIG_CRYPTO_DES=y
 
-CONFIG_CRYPTO_DEV_ALLWINNER=y
 
-CONFIG_CRYPTO_DEV_SUN4I_SS=y
 
-# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
 
-CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
 
-# CONFIG_CRYPTO_DEV_SUN8I_CE is not set
 
-# CONFIG_CRYPTO_DEV_SUN8I_SS is not set
 
-CONFIG_CRYPTO_HW=y
 
-CONFIG_CRYPTO_LIB_DES=y
 
-CONFIG_CRYPTO_MD5=y
 
-CONFIG_CRYPTO_RNG=y
 
-CONFIG_CRYPTO_RNG2=y
 
-CONFIG_CRYPTO_SHA1=y
 
-CONFIG_DCACHE_WORD_ACCESS=y
 
-CONFIG_DEBUG_BUGVERBOSE=y
 
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
 
-CONFIG_DEBUG_MEMORY_INIT=y
 
-CONFIG_DMADEVICES=y
 
-CONFIG_DMA_ENGINE=y
 
-CONFIG_DMA_OF=y
 
-CONFIG_DMA_OPS=y
 
-CONFIG_DMA_REMAP=y
 
-CONFIG_DMA_SUN4I=y
 
-CONFIG_DMA_SUN6I=y
 
-CONFIG_DMA_VIRTUAL_CHANNELS=y
 
-CONFIG_DNOTIFY=y
 
-CONFIG_DTC=y
 
-CONFIG_DUMMY_CONSOLE=y
 
-CONFIG_DVB_CORE=y
 
-CONFIG_DWMAC_GENERIC=y
 
-# CONFIG_DWMAC_SUN8I is not set
 
-CONFIG_DWMAC_SUNXI=y
 
-CONFIG_DYNAMIC_DEBUG=y
 
-CONFIG_EDAC_ATOMIC_SCRUB=y
 
-CONFIG_EDAC_SUPPORT=y
 
-CONFIG_ELF_CORE=y
 
-CONFIG_EXT4_FS=y
 
-CONFIG_EXTCON=y
 
-CONFIG_F2FS_FS=y
 
-CONFIG_FAT_FS=y
 
-CONFIG_FB=y
 
-CONFIG_FB_CFB_COPYAREA=y
 
-CONFIG_FB_CFB_FILLRECT=y
 
-CONFIG_FB_CFB_IMAGEBLIT=y
 
-CONFIG_FB_CMDLINE=y
 
-CONFIG_FB_FOREIGN_ENDIAN=y
 
-CONFIG_FB_LITTLE_ENDIAN=y
 
-CONFIG_FB_MODE_HELPERS=y
 
-CONFIG_FB_SIMPLE=y
 
-CONFIG_FB_TILEBLITTING=y
 
-CONFIG_FIXED_PHY=y
 
-CONFIG_FIX_EARLYCON_MEM=y
 
-CONFIG_FONT_8x16=y
 
-CONFIG_FONT_8x8=y
 
-CONFIG_FONT_SUPPORT=y
 
-CONFIG_FRAMEBUFFER_CONSOLE=y
 
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 
-CONFIG_FRAME_WARN=2048
 
-CONFIG_FREEZER=y
 
-CONFIG_FS_IOMAP=y
 
-CONFIG_FS_MBCACHE=y
 
-CONFIG_FS_POSIX_ACL=y
 
-CONFIG_FWNODE_MDIO=y
 
-CONFIG_FW_CACHE=y
 
-CONFIG_FW_LOADER_PAGED_BUF=y
 
-CONFIG_GENERIC_ALLOCATOR=y
 
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
 
-CONFIG_GENERIC_BUG=y
 
-CONFIG_GENERIC_CLOCKEVENTS=y
 
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 
-CONFIG_GENERIC_CPU_AUTOPROBE=y
 
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
 
-CONFIG_GENERIC_EARLY_IOREMAP=y
 
-CONFIG_GENERIC_GETTIMEOFDAY=y
 
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
 
-CONFIG_GENERIC_IRQ_CHIP=y
 
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
 
-CONFIG_GENERIC_IRQ_MIGRATION=y
 
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
 
-CONFIG_GENERIC_IRQ_SHOW=y
 
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
 
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
 
-CONFIG_GENERIC_PCI_IOMAP=y
 
-CONFIG_GENERIC_PHY=y
 
-CONFIG_GENERIC_PINCONF=y
 
-CONFIG_GENERIC_PINCTRL_GROUPS=y
 
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 
-CONFIG_GENERIC_SCHED_CLOCK=y
 
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
 
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
 
-CONFIG_GENERIC_STRNLEN_USER=y
 
-CONFIG_GENERIC_TIME_VSYSCALL=y
 
-CONFIG_GENERIC_VDSO_32=y
 
-CONFIG_GLOB=y
 
-CONFIG_GPIO_CDEV=y
 
-CONFIG_HANDLE_DOMAIN_IRQ=y
 
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
 
-CONFIG_HARDIRQS_SW_RESEND=y
 
-CONFIG_HAS_DMA=y
 
-CONFIG_HAS_IOMEM=y
 
-CONFIG_HAS_IOPORT_MAP=y
 
-CONFIG_HAVE_SMP=y
 
-CONFIG_HIGHMEM=y
 
-CONFIG_HIGHPTE=y
 
-CONFIG_HOTPLUG_CPU=y
 
-CONFIG_HWMON=y
 
-CONFIG_HW_CONSOLE=y
 
-CONFIG_HW_RANDOM=y
 
-CONFIG_HW_RANDOM_TIMERIOMEM=y
 
-CONFIG_HZ_FIXED=0
 
-CONFIG_I2C=y
 
-CONFIG_I2C_BOARDINFO=y
 
-CONFIG_I2C_CHARDEV=y
 
-CONFIG_I2C_COMPAT=y
 
-CONFIG_I2C_HELPER_AUTO=y
 
-CONFIG_I2C_MV64XXX=y
 
-CONFIG_I2C_SUN6I_P2WI=y
 
-CONFIG_IIO=y
 
-CONFIG_INITRAMFS_SOURCE=""
 
-CONFIG_INPUT=y
 
-CONFIG_INPUT_AXP20X_PEK=y
 
-CONFIG_INPUT_KEYBOARD=y
 
-CONFIG_INPUT_MOUSEDEV=y
 
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
 
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 
-CONFIG_INPUT_TOUCHSCREEN=y
 
-CONFIG_IRQCHIP=y
 
-CONFIG_IRQ_DOMAIN=y
 
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
 
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
 
-CONFIG_IRQ_FORCED_THREADING=y
 
-CONFIG_IRQ_WORK=y
 
-CONFIG_JBD2=y
 
-CONFIG_KALLSYMS=y
 
-CONFIG_KEYBOARD_SUN4I_LRADC=y
 
-CONFIG_KMAP_LOCAL=y
 
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
 
-CONFIG_KSM=y
 
-CONFIG_LCD_CLASS_DEVICE=y
 
-CONFIG_LCD_PLATFORM=y
 
-CONFIG_LEDS_GPIO=y
 
-CONFIG_LIBFDT=y
 
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
 
-CONFIG_LOCK_SPIN_ON_OWNER=y
 
-CONFIG_LOGO=y
 
-CONFIG_LOGO_LINUX_CLUT224=y
 
-CONFIG_LOGO_LINUX_MONO=y
 
-CONFIG_LOGO_LINUX_VGA16=y
 
-CONFIG_MACH_SUN4I=y
 
-CONFIG_MACH_SUN5I=y
 
-CONFIG_MACH_SUN6I=y
 
-CONFIG_MACH_SUN7I=y
 
-CONFIG_MACH_SUN8I=y
 
-CONFIG_MACH_SUN9I=y
 
-CONFIG_MAGIC_SYSRQ=y
 
-CONFIG_MDIO_BUS=y
 
-CONFIG_MDIO_DEVICE=y
 
-CONFIG_MDIO_DEVRES=y
 
-CONFIG_MDIO_SUN4I=y
 
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
 
-CONFIG_MEDIA_ATTACH=y
 
-CONFIG_MEDIA_CAMERA_SUPPORT=y
 
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
 
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
 
-CONFIG_MEDIA_RADIO_SUPPORT=y
 
-CONFIG_MEDIA_SDR_SUPPORT=y
 
-CONFIG_MEDIA_SUPPORT=y
 
-CONFIG_MEDIA_TEST_SUPPORT=y
 
-CONFIG_MEDIA_TUNER=y
 
-CONFIG_MEMFD_CREATE=y
 
-CONFIG_MFD_AXP20X=y
 
-CONFIG_MFD_AXP20X_I2C=y
 
-CONFIG_MFD_AXP20X_RSB=y
 
-CONFIG_MFD_CORE=y
 
-CONFIG_MFD_SUN6I_PRCM=y
 
-CONFIG_MFD_SYSCON=y
 
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
 
-CONFIG_MIGRATION=y
 
-CONFIG_MMC=y
 
-CONFIG_MMC_BLOCK=y
 
-CONFIG_MMC_SUNXI=y
 
-CONFIG_MODULES_USE_ELF_REL=y
 
-CONFIG_MTD_JEDECPROBE=y
 
-CONFIG_MTD_SPI_NOR=y
 
-CONFIG_MTD_SPLIT_FIT_FW=y
 
-CONFIG_MUTEX_SPIN_ON_OWNER=y
 
-CONFIG_NEED_DMA_MAP_STATE=y
 
-CONFIG_NEON=y
 
-CONFIG_NET_FLOW_LIMIT=y
 
-CONFIG_NET_PTP_CLASSIFY=y
 
-CONFIG_NET_SELFTESTS=y
 
-CONFIG_NET_VENDOR_ALLWINNER=y
 
-CONFIG_NLS=y
 
-CONFIG_NLS_CODEPAGE_437=y
 
-CONFIG_NLS_ISO8859_1=y
 
-CONFIG_NO_HZ=y
 
-CONFIG_NO_HZ_COMMON=y
 
-CONFIG_NO_HZ_IDLE=y
 
-CONFIG_NR_CPUS=8
 
-CONFIG_NVMEM=y
 
-CONFIG_NVMEM_SUNXI_SID=y
 
-CONFIG_NVMEM_SYSFS=y
 
-CONFIG_OF=y
 
-CONFIG_OF_ADDRESS=y
 
-CONFIG_OF_EARLY_FLATTREE=y
 
-CONFIG_OF_FLATTREE=y
 
-CONFIG_OF_GPIO=y
 
-CONFIG_OF_IRQ=y
 
-CONFIG_OF_KOBJ=y
 
-CONFIG_OF_MDIO=y
 
-CONFIG_OLD_SIGACTION=y
 
-CONFIG_OLD_SIGSUSPEND3=y
 
-CONFIG_OUTER_CACHE=y
 
-CONFIG_OUTER_CACHE_SYNC=y
 
-CONFIG_PADATA=y
 
-CONFIG_PAGE_OFFSET=0xC0000000
 
-CONFIG_PAGE_POOL=y
 
-CONFIG_PCS_XPCS=y
 
-CONFIG_PERF_USE_VMALLOC=y
 
-CONFIG_PGTABLE_LEVELS=3
 
-CONFIG_PHYLIB=y
 
-CONFIG_PHYLINK=y
 
-CONFIG_PHYS_ADDR_T_64BIT=y
 
-CONFIG_PHY_SUN4I_USB=y
 
-# CONFIG_PHY_SUN50I_USB3 is not set
 
-# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
 
-CONFIG_PHY_SUN9I_USB=y
 
-CONFIG_PINCTRL=y
 
-CONFIG_PINCTRL_AXP209=y
 
-# CONFIG_PINCTRL_SUN20I_D1 is not set
 
-CONFIG_PINCTRL_SUN4I_A10=y
 
-# CONFIG_PINCTRL_SUN50I_A100 is not set
 
-# CONFIG_PINCTRL_SUN50I_A100_R is not set
 
-# CONFIG_PINCTRL_SUN50I_A64 is not set
 
-# CONFIG_PINCTRL_SUN50I_A64_R is not set
 
-# CONFIG_PINCTRL_SUN50I_H5 is not set
 
-# CONFIG_PINCTRL_SUN50I_H6 is not set
 
-# CONFIG_PINCTRL_SUN50I_H616 is not set
 
-# CONFIG_PINCTRL_SUN50I_H616_R is not set
 
-# CONFIG_PINCTRL_SUN50I_H6_R is not set
 
-CONFIG_PINCTRL_SUN5I=y
 
-CONFIG_PINCTRL_SUN6I_A31=y
 
-CONFIG_PINCTRL_SUN6I_A31_R=y
 
-CONFIG_PINCTRL_SUN8I_A23=y
 
-CONFIG_PINCTRL_SUN8I_A23_R=y
 
-CONFIG_PINCTRL_SUN8I_A33=y
 
-CONFIG_PINCTRL_SUN8I_A83T=y
 
-CONFIG_PINCTRL_SUN8I_A83T_R=y
 
-CONFIG_PINCTRL_SUN8I_H3=y
 
-CONFIG_PINCTRL_SUN8I_H3_R=y
 
-CONFIG_PINCTRL_SUN8I_V3S=y
 
-CONFIG_PINCTRL_SUN9I_A80=y
 
-CONFIG_PINCTRL_SUN9I_A80_R=y
 
-CONFIG_PINCTRL_SUNXI=y
 
-CONFIG_PM=y
 
-CONFIG_PM_CLK=y
 
-CONFIG_PM_OPP=y
 
-CONFIG_PM_SLEEP=y
 
-CONFIG_PM_SLEEP_SMP=y
 
-CONFIG_POWER_RESET=y
 
-CONFIG_POWER_SUPPLY=y
 
-CONFIG_PPS=y
 
-CONFIG_PRINTK_TIME=y
 
-CONFIG_PROC_EVENTS=y
 
-CONFIG_PROC_PAGE_MONITOR=y
 
-CONFIG_PTP_1588_CLOCK=y
 
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
 
-CONFIG_PWM=y
 
-CONFIG_PWM_SUN4I=y
 
-CONFIG_PWM_SYSFS=y
 
-CONFIG_RATIONAL=y
 
-CONFIG_REALTEK_PHY=y
 
-CONFIG_REGMAP=y
 
-CONFIG_REGMAP_I2C=y
 
-CONFIG_REGMAP_IRQ=y
 
-CONFIG_REGMAP_MMIO=y
 
-CONFIG_REGMAP_SPI=y
 
-CONFIG_REGULATOR=y
 
-CONFIG_REGULATOR_AXP20X=y
 
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
 
-CONFIG_REGULATOR_GPIO=y
 
-CONFIG_REGULATOR_SY8106A=y
 
-CONFIG_RELAY=y
 
-CONFIG_RESET_CONTROLLER=y
 
-CONFIG_RESET_SIMPLE=y
 
-CONFIG_RESET_SUNXI=y
 
-CONFIG_RFS_ACCEL=y
 
-CONFIG_RPS=y
 
-CONFIG_RWSEM_SPIN_ON_OWNER=y
 
-CONFIG_SATA_HOST=y
 
-CONFIG_SATA_PMP=y
 
-CONFIG_SCSI=y
 
-CONFIG_SCSI_COMMON=y
 
-CONFIG_SDIO_UART=y
 
-CONFIG_SECURITYFS=y
 
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
 
-CONFIG_SERIAL_8250_DW=y
 
-CONFIG_SERIAL_8250_DWLIB=y
 
-CONFIG_SERIAL_8250_FSL=y
 
-CONFIG_SERIAL_8250_NR_UARTS=8
 
-CONFIG_SERIAL_8250_RUNTIME_UARTS=8
 
-CONFIG_SERIAL_MCTRL_GPIO=y
 
-CONFIG_SERIAL_OF_PLATFORM=y
 
-CONFIG_SERIO=y
 
-CONFIG_SERIO_SERPORT=y
 
-CONFIG_SG_POOL=y
 
-CONFIG_SMP=y
 
-CONFIG_SMP_ON_UP=y
 
-CONFIG_SND=y
 
-CONFIG_SND_COMPRESS_OFFLOAD=y
 
-CONFIG_SND_JACK=y
 
-CONFIG_SND_JACK_INPUT_DEV=y
 
-CONFIG_SND_PCM=y
 
-CONFIG_SND_SIMPLE_CARD=y
 
-CONFIG_SND_SIMPLE_CARD_UTILS=y
 
-CONFIG_SND_SOC=y
 
-CONFIG_SND_SOC_I2C_AND_SPI=y
 
-# CONFIG_SND_SUN4I_I2S is not set
 
-# CONFIG_SND_SUN4I_SPDIF is not set
 
-# CONFIG_SND_SUN50I_DMIC is not set
 
-# CONFIG_SND_SUN8I_CODEC is not set
 
-# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
 
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
 
-CONFIG_SOUND=y
 
-CONFIG_SOUND_OSS_CORE=y
 
-CONFIG_SPARSE_IRQ=y
 
-CONFIG_SPI=y
 
-CONFIG_SPI_MASTER=y
 
-CONFIG_SPI_MEM=y
 
-CONFIG_SPI_SUN4I=y
 
-CONFIG_SPI_SUN6I=y
 
-CONFIG_SRCU=y
 
-CONFIG_STMMAC_ETH=y
 
-CONFIG_STMMAC_PLATFORM=y
 
-CONFIG_SUN4I_A10_CCU=y
 
-# CONFIG_SUN4I_EMAC is not set
 
-CONFIG_SUN4I_TIMER=y
 
-CONFIG_SUN5I_CCU=y
 
-CONFIG_SUN5I_HSTIMER=y
 
-CONFIG_SUN6I_A31_CCU=y
 
-# CONFIG_SUN6I_RTC_CCU is not set
 
-CONFIG_SUN8I_A23_CCU=y
 
-CONFIG_SUN8I_A33_CCU=y
 
-CONFIG_SUN8I_A83T_CCU=y
 
-CONFIG_SUN8I_DE2_CCU=y
 
-CONFIG_SUN8I_H3_CCU=y
 
-CONFIG_SUN8I_R40_CCU=y
 
-CONFIG_SUN8I_R_CCU=y
 
-CONFIG_SUN8I_THERMAL=y
 
-CONFIG_SUN8I_V3S_CCU=y
 
-CONFIG_SUN9I_A80_CCU=y
 
-CONFIG_SUNXI_CCU=y
 
-CONFIG_SUNXI_MBUS=y
 
-CONFIG_SUNXI_RSB=y
 
-CONFIG_SUNXI_SRAM=y
 
-CONFIG_SUNXI_WATCHDOG=y
 
-CONFIG_SUSPEND=y
 
-CONFIG_SUSPEND_FREEZER=y
 
-CONFIG_SWIOTLB=y
 
-CONFIG_SWPHY=y
 
-CONFIG_SWP_EMULATE=y
 
-CONFIG_SYSFS_SYSCALL=y
 
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 
-CONFIG_THERMAL=y
 
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
 
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
 
-CONFIG_THERMAL_GOV_STEP_WISE=y
 
-CONFIG_THERMAL_HWMON=y
 
-CONFIG_THERMAL_OF=y
 
-CONFIG_TICK_CPU_ACCOUNTING=y
 
-CONFIG_TIMER_OF=y
 
-CONFIG_TIMER_PROBE=y
 
-CONFIG_TMPFS_POSIX_ACL=y
 
-CONFIG_TOUCHSCREEN_SUN4I=y
 
-CONFIG_TREE_RCU=y
 
-CONFIG_TREE_SRCU=y
 
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 
-CONFIG_UNWINDER_ARM=y
 
-CONFIG_USB=y
 
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 
-CONFIG_USB_COMMON=y
 
-CONFIG_USB_DWC2=y
 
-CONFIG_USB_DWC2_HOST=y
 
-CONFIG_USB_EHCI_HCD=y
 
-CONFIG_USB_EHCI_HCD_PLATFORM=y
 
-CONFIG_USB_GADGET=y
 
-CONFIG_USB_NET_DRIVERS=y
 
-CONFIG_USB_OHCI_HCD=y
 
-CONFIG_USB_OHCI_HCD_PLATFORM=y
 
-CONFIG_USB_ROLE_SWITCH=y
 
-CONFIG_USB_STORAGE=y
 
-CONFIG_USB_SUPPORT=y
 
-CONFIG_USERIO=y
 
-CONFIG_USE_OF=y
 
-CONFIG_VFAT_FS=y
 
-CONFIG_VFP=y
 
-CONFIG_VFPv3=y
 
-CONFIG_VHOST=y
 
-CONFIG_VHOST_IOTLB=y
 
-CONFIG_VHOST_NET=y
 
-# CONFIG_VIDEO_SUN4I_CSI is not set
 
-# CONFIG_VIDEO_SUN6I_CSI is not set
 
-CONFIG_VM_EVENT_COUNTERS=y
 
-CONFIG_VT=y
 
-CONFIG_VT_CONSOLE=y
 
-CONFIG_VT_CONSOLE_SLEEP=y
 
-CONFIG_VT_HW_CONSOLE_BINDING=y
 
-CONFIG_WATCHDOG_CORE=y
 
-CONFIG_XPS=y
 
-CONFIG_XXHASH=y
 
-CONFIG_XZ_DEC_ARM=y
 
-CONFIG_XZ_DEC_BCJ=y
 
-CONFIG_ZBOOT_ROM_BSS=0
 
-CONFIG_ZBOOT_ROM_TEXT=0

+ 0 - 109
target/linux/sunxi/cortexa53/config-6.1
View File 

@@ -1,109 +0,0 @@
 
-CONFIG_64BIT=y
 
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
 
-CONFIG_ARCH_MMAP_RND_BITS=18
 
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
 
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
 
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
 
-CONFIG_ARCH_PROC_KCORE_TEXT=y
 
-CONFIG_ARCH_STACKWALK=y
 
-CONFIG_ARCH_WANTS_NO_INSTR=y
 
-CONFIG_ARM64=y
 
-CONFIG_ARM64_4K_PAGES=y
 
-CONFIG_ARM64_CRYPTO=y
 
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
 
-CONFIG_ARM64_ERRATUM_2051678=y
 
-CONFIG_ARM64_ERRATUM_2077057=y
 
-CONFIG_ARM64_ERRATUM_2658417=y
 
-CONFIG_ARM64_ERRATUM_2054223=y
 
-CONFIG_ARM64_ERRATUM_2067961=y
 
-CONFIG_ARM64_PAGE_SHIFT=12
 
-CONFIG_ARM64_PA_BITS=48
 
-CONFIG_ARM64_PA_BITS_48=y
 
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
 
-CONFIG_ARM64_VA_BITS=39
 
-CONFIG_ARM64_VA_BITS_39=y
 
-CONFIG_ARM_AMBA=y
 
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
 
-CONFIG_ARM_GIC_V3=y
 
-CONFIG_ARM_GIC_V3_ITS=y
 
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
 
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
 
-CONFIG_CPU_LITTLE_ENDIAN=y
 
-CONFIG_CRYPTO_AES_ARM64=y
 
-CONFIG_CRYPTO_AES_ARM64_CE=y
 
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
 
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
 
-CONFIG_CRYPTO_BLAKE2S=y
 
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
 
-CONFIG_CRYPTO_CRYPTD=y
 
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
 
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
 
-CONFIG_CRYPTO_SHA1_ARM64_CE=y
 
-CONFIG_CRYPTO_SIMD=y
 
-CONFIG_DMA_DIRECT_REMAP=y
 
-CONFIG_DWMAC_SUN8I=y
 
-CONFIG_EEPROM_AT24=y
 
-CONFIG_FRAME_POINTER=y
 
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
 
-CONFIG_GENERIC_CSUM=y
 
-CONFIG_GENERIC_FIND_FIRST_BIT=y
 
-CONFIG_GENERIC_MSI_IRQ=y
 
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
 
-CONFIG_MDIO_BUS_MUX=y
 
-CONFIG_MICREL_PHY=y
 
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
 
-CONFIG_MODULES_USE_ELF_RELA=y
 
-CONFIG_MOTORCOMM_PHY=y
 
-CONFIG_MUSB_PIO_ONLY=y
 
-CONFIG_NEED_SG_DMA_LENGTH=y
 
-CONFIG_NOP_USB_XCEIV=y
 
-CONFIG_NO_IOPORT_MAP=y
 
-CONFIG_PARTITION_PERCPU=y
 
-CONFIG_PHY_SUN50I_USB3=y
 
-CONFIG_PINCTRL_SUN50I_A100=y
 
-CONFIG_PINCTRL_SUN50I_A100_R=y
 
-CONFIG_PINCTRL_SUN50I_A64=y
 
-CONFIG_PINCTRL_SUN50I_A64_R=y
 
-CONFIG_PINCTRL_SUN50I_H5=y
 
-CONFIG_PINCTRL_SUN50I_H6=y
 
-CONFIG_PINCTRL_SUN50I_H6_R=y
 
-CONFIG_PINCTRL_SUN50I_H616=y
 
-CONFIG_PINCTRL_SUN50I_H616_R=y
 
-# CONFIG_PREEMPT_DYNAMIC is not set
 
-CONFIG_QUEUED_RWLOCKS=y
 
-CONFIG_QUEUED_SPINLOCKS=y
 
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
 
-# CONFIG_SCHED_CLUSTER is not set
 
-# CONFIG_SHADOW_CALL_STACK is not set
 
-# CONFIG_SND_SUN50I_CODEC_ANALOG is not set
 
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
 
-CONFIG_SPARSEMEM=y
 
-CONFIG_SPARSEMEM_EXTREME=y
 
-CONFIG_SPARSEMEM_VMEMMAP=y
 
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
 
-CONFIG_SUN50I_A100_CCU=y
 
-CONFIG_SUN50I_A100_R_CCU=y
 
-CONFIG_SUN50I_A64_CCU=y
 
-CONFIG_SUN50I_DE2_BUS=y
 
-CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
 
-CONFIG_SUN50I_H616_CCU=y
 
-CONFIG_SUN50I_H6_CCU=y
 
-CONFIG_SUN50I_H6_R_CCU=y
 
-# CONFIG_SUN6I_RTC_CCU is not set
 
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
 
-CONFIG_THREAD_INFO_IN_TASK=y
 
-CONFIG_UNMAP_KERNEL_AT_EL0=y
 
-CONFIG_USB_MUSB_DUAL_ROLE=y
 
-CONFIG_USB_MUSB_HDRC=y
 
-CONFIG_USB_MUSB_SUNXI=y
 
-CONFIG_USB_PHY=y
 
-CONFIG_VMAP_STACK=y
 
-CONFIG_ZONE_DMA32=y
 
-CONFIG_SURFACE_PLATFORMS=y
 
-# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
 
-# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
 
-# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
 
-# CONFIG_PAGE_TABLE_CHECK is not set
 
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
 
-# CONFIG_ARCH_NXP is not set

+ 0 - 26
target/linux/sunxi/cortexa7/config-6.1
View File 

@@ -1,26 +0,0 @@
 
-CONFIG_B53=y
 
-CONFIG_B53_MDIO_DRIVER=y
 
-CONFIG_CRYPTO_BLAKE2S_ARM=y
 
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
 
-CONFIG_DWMAC_SUN8I=y
 
-CONFIG_GRO_CELLS=y
 
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
 
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
 
-# CONFIG_MACH_SUN4I is not set
 
-# CONFIG_MACH_SUN5I is not set
 
-CONFIG_MDIO_BUS_MUX=y
 
-CONFIG_MICREL_PHY=y
 
-CONFIG_MUSB_PIO_ONLY=y
 
-CONFIG_NET_DEVLINK=y
 
-CONFIG_NET_DSA=y
 
-CONFIG_NET_DSA_TAG_BRCM=y
 
-CONFIG_NET_DSA_TAG_BRCM_COMMON=y
 
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
 
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
 
-CONFIG_NET_SWITCHDEV=y
 
-CONFIG_NOP_USB_XCEIV=y
 
-CONFIG_RTC_DRV_SUN6I=y
 
-CONFIG_USB_MUSB_DUAL_ROLE=y
 
-CONFIG_USB_MUSB_HDRC=y
 
-CONFIG_USB_MUSB_SUNXI=y
 
-CONFIG_USB_PHY=y

+ 0 - 12
target/linux/sunxi/cortexa8/config-6.1
View File 

@@ -1,12 +0,0 @@
 
-# CONFIG_ARM_LPAE is not set
 
-CONFIG_CRYPTO_BLAKE2S_ARM=y
 
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
 
-# CONFIG_MACH_SUN6I is not set
 
-# CONFIG_MACH_SUN7I is not set
 
-# CONFIG_MACH_SUN8I is not set
 
-# CONFIG_MACH_SUN9I is not set
 
-CONFIG_PGTABLE_LEVELS=2
 
-# CONFIG_PHY_SUN9I_USB is not set
 
-# CONFIG_SPI_SUN6I is not set
 
-# CONFIG_SUN8I_A83T_CCU is not set
 
-# CONFIG_SUN8I_THERMAL is not set

+ 0 - 2
target/linux/sunxi/image/Makefile
View File 

@@ -34,9 +34,7 @@ define Device/Default
 
   KERNEL := kernel-bin | uImage none
 
   IMAGES := sdcard.img.gz
 
   IMAGE/sdcard.img.gz := sunxi-sdcard | append-metadata | gzip
 
-ifdef CONFIG_LINUX_6_6
 
   SUNXI_DTS_DIR :=allwinner/
 
-endif
 
   SUNXI_DTS = $$(SUNXI_DTS_DIR)$$(SOC)-$(lastword $(subst _, ,$(1)))
 
 endef

+ 0 - 38
target/linux/sunxi/patches-6.1/001-v6.2-dt-bindings-usb-Add-H616-compatible-string.patch
View File 

@@ -1,38 +0,0 @@
 
-From 28a1a6474c5053bae01bd29946b4d5ede539176b Mon Sep 17 00:00:00 2001
 
-From: Andre Przywara <[email protected]>
 
-Date: Mon, 31 Oct 2022 11:13:52 +0000
 
-Subject: [PATCH] dt-bindings: usb: Add H616 compatible string
 
-
 
-The Allwinner H616 contains four fully OHCI/EHCI compatible USB host
 
-controllers, so just add their compatible strings to the list of
 
-generic OHCI/EHCI controllers.
 
-
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Acked-by: Krzysztof Kozlowski <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Jernej Skrabec <[email protected]>
 
----
 
- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
 
- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
 
- 2 files changed, 2 insertions(+)
 
-
 
---- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
 
-+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
 
-@@ -30,6 +30,7 @@ properties:
 
-               - allwinner,sun4i-a10-ehci
 
-               - allwinner,sun50i-a64-ehci
 
-               - allwinner,sun50i-h6-ehci
 
-+              - allwinner,sun50i-h616-ehci
 
-               - allwinner,sun5i-a13-ehci
 
-               - allwinner,sun6i-a31-ehci
 
-               - allwinner,sun7i-a20-ehci
 
---- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
 
-+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
 
-@@ -20,6 +20,7 @@ properties:
 
-               - allwinner,sun4i-a10-ohci
 
-               - allwinner,sun50i-a64-ohci
 
-               - allwinner,sun50i-h6-ohci
 
-+              - allwinner,sun50i-h616-ohci
 
-               - allwinner,sun5i-a13-ohci
 
-               - allwinner,sun6i-a31-ohci
 
-               - allwinner,sun7i-a20-ohci

+ 0 - 79
target/linux/sunxi/patches-6.1/002-v6.2-dt-bindings-phy-Add-special-clock-for-Allwinner-H616-PHY.patch
View File 

@@ -1,79 +0,0 @@
 
-From 6964affe65066651eca21e97247d3b7cac5153dc Mon Sep 17 00:00:00 2001
 
-From: Andre Przywara <[email protected]>
 
-Date: Mon, 31 Oct 2022 11:13:53 +0000
 
-Subject: [PATCH] dt-bindings: phy: Add special clock for Allwinner H616 PHY
 
-
 
-The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
 
-some resources from port 2's PHY and HCI IP. In particular the PMU clock
 
-for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
 
-register of port 2. To allow each USB port to be controlled
 
-independently of port 2, we need a handle to that particular PMU clock
 
-in the *PHY* node, as the HCI and PHY part might be handled by separate
 
-drivers.
 
-
 
-Add that clock to the requirements of the H616 PHY binding, so that a
 
-PHY driver can apply the quirk in isolation, without requiring help from
 
-port 2's HCI driver.
 
-
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Reviewed-by: Rob Herring <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Vinod Koul <[email protected]>
 
----
 
- .../phy/allwinner,sun8i-h3-usb-phy.yaml       | 26 +++++++++++++++++++
 
- 1 file changed, 26 insertions(+)
 
-
 
---- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
 
-+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
 
-@@ -36,18 +36,22 @@ properties:
 
-       - const: pmu3
 
- 
-   clocks:
 
-+    minItems: 4
 
-     items:
 
-       - description: USB OTG PHY bus clock
 
-       - description: USB Host 0 PHY bus clock
 
-       - description: USB Host 1 PHY bus clock
 
-       - description: USB Host 2 PHY bus clock
 
-+      - description: PMU clock for host port 2
 
- 
-   clock-names:
 
-+    minItems: 4
 
-     items:
 
-       - const: usb0_phy
 
-       - const: usb1_phy
 
-       - const: usb2_phy
 
-       - const: usb3_phy
 
-+      - const: pmu2_clk
 
- 
-   resets:
 
-     items:
 
-@@ -96,6 +100,28 @@ required:
 
-   - resets
 
-   - reset-names
 
- 
-+allOf:
 
-+  - if:
 
-+      properties:
 
-+        compatible:
 
-+          contains:
 
-+            enum:
 
-+              - allwinner,sun50i-h616-usb-phy
 
-+    then:
 
-+      properties:
 
-+        clocks:
 
-+          minItems: 5
 
-+
 
-+        clock-names:
 
-+          minItems: 5
 
-+    else:
 
-+      properties:
 
-+        clocks:
 
-+          maxItems: 4
 
-+
 
-+        clock-names:
 
-+          maxItems: 4
 
-+
 
- additionalProperties: false
 
- 
- examples:

+ 0 - 188
target/linux/sunxi/patches-6.1/003-v6.2-arm64-dts-allwinner-h616-Add-USB-nodes.patch
View File 

@@ -1,188 +0,0 @@
 
-From f40cf244c3feb4e1a442f8029b691add2c65b3ab Mon Sep 17 00:00:00 2001
 
-From: Andre Przywara <[email protected]>
 
-Date: Mon, 31 Oct 2022 11:13:56 +0000
 
-Subject: [PATCH] arm64: dts: allwinner: h616: Add USB nodes
 
-
 
-Add the nodes for the MUSB and the four USB host controllers to the SoC
 
-.dtsi, along with the PHY node needed to bind all of them together.
 
-
 
-EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
 
-some quirks (handled in the driver).
 
-
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Reviewed-by: Jernej Skrabec <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Jernej Skrabec <[email protected]>
 
----
 
- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
 
- 1 file changed, 160 insertions(+)
 
-
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
 
-@@ -504,6 +504,166 @@
 
- 			};
 
- 		};
 
- 
-+		usbotg: usb@5100000 {
 
-+			compatible = "allwinner,sun50i-h616-musb",
 
-+				     "allwinner,sun8i-h3-musb";
 
-+			reg = <0x05100000 0x0400>;
 
-+			clocks = <&ccu CLK_BUS_OTG>;
 
-+			resets = <&ccu RST_BUS_OTG>;
 
-+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 
-+			interrupt-names = "mc";
 
-+			phys = <&usbphy 0>;
 
-+			phy-names = "usb";
 
-+			extcon = <&usbphy 0>;
 
-+			status = "disabled";
 
-+		};
 
-+
 
-+		usbphy: phy@5100400 {
 
-+			compatible = "allwinner,sun50i-h616-usb-phy";
 
-+			reg = <0x05100400 0x24>,
 
-+			      <0x05101800 0x14>,
 
-+			      <0x05200800 0x14>,
 
-+			      <0x05310800 0x14>,
 
-+			      <0x05311800 0x14>;
 
-+			reg-names = "phy_ctrl",
 
-+				    "pmu0",
 
-+				    "pmu1",
 
-+				    "pmu2",
 
-+				    "pmu3";
 
-+			clocks = <&ccu CLK_USB_PHY0>,
 
-+				 <&ccu CLK_USB_PHY1>,
 
-+				 <&ccu CLK_USB_PHY2>,
 
-+				 <&ccu CLK_USB_PHY3>,
 
-+				 <&ccu CLK_BUS_EHCI2>;
 
-+			clock-names = "usb0_phy",
 
-+				      "usb1_phy",
 
-+				      "usb2_phy",
 
-+				      "usb3_phy",
 
-+				      "pmu2_clk";
 
-+			resets = <&ccu RST_USB_PHY0>,
 
-+				 <&ccu RST_USB_PHY1>,
 
-+				 <&ccu RST_USB_PHY2>,
 
-+				 <&ccu RST_USB_PHY3>;
 
-+			reset-names = "usb0_reset",
 
-+				      "usb1_reset",
 
-+				      "usb2_reset",
 
-+				      "usb3_reset";
 
-+			status = "disabled";
 
-+			#phy-cells = <1>;
 
-+		};
 
-+
 
-+		ehci0: usb@5101000 {
 
-+			compatible = "allwinner,sun50i-h616-ehci",
 
-+				     "generic-ehci";
 
-+			reg = <0x05101000 0x100>;
 
-+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 
-+			clocks = <&ccu CLK_BUS_OHCI0>,
 
-+				 <&ccu CLK_BUS_EHCI0>,
 
-+				 <&ccu CLK_USB_OHCI0>;
 
-+			resets = <&ccu RST_BUS_OHCI0>,
 
-+				 <&ccu RST_BUS_EHCI0>;
 
-+			phys = <&usbphy 0>;
 
-+			phy-names = "usb";
 
-+			status = "disabled";
 
-+		};
 
-+
 
-+		ohci0: usb@5101400 {
 
-+			compatible = "allwinner,sun50i-h616-ohci",
 
-+				     "generic-ohci";
 
-+			reg = <0x05101400 0x100>;
 
-+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 
-+			clocks = <&ccu CLK_BUS_OHCI0>,
 
-+				 <&ccu CLK_USB_OHCI0>;
 
-+			resets = <&ccu RST_BUS_OHCI0>;
 
-+			phys = <&usbphy 0>;
 
-+			phy-names = "usb";
 
-+			status = "disabled";
 
-+		};
 
-+
 
-+		ehci1: usb@5200000 {
 
-+			compatible = "allwinner,sun50i-h616-ehci",
 
-+				     "generic-ehci";
 
-+			reg = <0x05200000 0x100>;
 
-+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 
-+			clocks = <&ccu CLK_BUS_OHCI1>,
 
-+				 <&ccu CLK_BUS_EHCI1>,
 
-+				 <&ccu CLK_USB_OHCI1>;
 
-+			resets = <&ccu RST_BUS_OHCI1>,
 
-+				 <&ccu RST_BUS_EHCI1>;
 
-+			phys = <&usbphy 1>;
 
-+			phy-names = "usb";
 
-+			status = "disabled";
 
-+		};
 
-+
 
-+		ohci1: usb@5200400 {
 
-+			compatible = "allwinner,sun50i-h616-ohci",
 
-+				     "generic-ohci";
 
-+			reg = <0x05200400 0x100>;
 
-+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 
-+			clocks = <&ccu CLK_BUS_OHCI1>,
 
-+				 <&ccu CLK_USB_OHCI1>;
 
-+			resets = <&ccu RST_BUS_OHCI1>;
 
-+			phys = <&usbphy 1>;
 
-+			phy-names = "usb";
 
-+			status = "disabled";
 
-+		};
 
-+
 
-+		ehci2: usb@5310000 {
 
-+			compatible = "allwinner,sun50i-h616-ehci",
 
-+				     "generic-ehci";
 
-+			reg = <0x05310000 0x100>;
 
-+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 
-+			clocks = <&ccu CLK_BUS_OHCI2>,
 
-+				 <&ccu CLK_BUS_EHCI2>,
 
-+				 <&ccu CLK_USB_OHCI2>;
 
-+			resets = <&ccu RST_BUS_OHCI2>,
 
-+				 <&ccu RST_BUS_EHCI2>;
 
-+			phys = <&usbphy 2>;
 
-+			phy-names = "usb";
 
-+			status = "disabled";
 
-+		};
 
-+
 
-+		ohci2: usb@5310400 {
 
-+			compatible = "allwinner,sun50i-h616-ohci",
 
-+				     "generic-ohci";
 
-+			reg = <0x05310400 0x100>;
 
-+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 
-+			clocks = <&ccu CLK_BUS_OHCI2>,
 
-+				 <&ccu CLK_USB_OHCI2>;
 
-+			resets = <&ccu RST_BUS_OHCI2>;
 
-+			phys = <&usbphy 2>;
 
-+			phy-names = "usb";
 
-+			status = "disabled";
 
-+		};
 
-+
 
-+		ehci3: usb@5311000 {
 
-+			compatible = "allwinner,sun50i-h616-ehci",
 
-+				     "generic-ehci";
 
-+			reg = <0x05311000 0x100>;
 
-+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 
-+			clocks = <&ccu CLK_BUS_OHCI3>,
 
-+				 <&ccu CLK_BUS_EHCI3>,
 
-+				 <&ccu CLK_USB_OHCI3>;
 
-+			resets = <&ccu RST_BUS_OHCI3>,
 
-+				 <&ccu RST_BUS_EHCI3>;
 
-+			phys = <&usbphy 3>;
 
-+			phy-names = "usb";
 
-+			status = "disabled";
 
-+		};
 
-+
 
-+		ohci3: usb@5311400 {
 
-+			compatible = "allwinner,sun50i-h616-ohci",
 
-+				     "generic-ohci";
 
-+			reg = <0x05311400 0x100>;
 
-+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 
-+			clocks = <&ccu CLK_BUS_OHCI3>,
 
-+				 <&ccu CLK_USB_OHCI3>;
 
-+			resets = <&ccu RST_BUS_OHCI3>;
 
-+			phys = <&usbphy 3>;
 
-+			phy-names = "usb";
 
-+			status = "disabled";
 
-+		};
 
-+
 
- 		rtc: rtc@7000000 {
 
- 			compatible = "allwinner,sun50i-h616-rtc";
 
- 			reg = <0x07000000 0x400>;

+ 0 - 81
target/linux/sunxi/patches-6.1/004-v6.2-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nodes.patch
View File 

@@ -1,81 +0,0 @@
 
-From db5f028309ede13767e2ba356c1975ac37a4fd6c Mon Sep 17 00:00:00 2001
 
-From: Andre Przywara <[email protected]>
 
-Date: Mon, 31 Oct 2022 11:13:57 +0000
 
-Subject: [PATCH] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
 
-
 
-The OrangePi Zero 2 has one USB-A host port, VBUS is provided by
 
-a GPIO controlled regulator.
 
-The USB-C port is meant to power the board, but is also connected to
 
-the USB 0 port, which we configure as an MUSB peripheral.
 
-
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Reviewed-by: Jernej Skrabec <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Jernej Skrabec <[email protected]>
 
----
 
- .../allwinner/sun50i-h616-orangepi-zero2.dts  | 41 +++++++++++++++++++
 
- 1 file changed, 41 insertions(+)
 
-
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
 
-@@ -49,8 +49,24 @@
 
- 		regulator-max-microvolt = <5000000>;
 
- 		regulator-always-on;
 
- 	};
 
-+
 
-+	reg_usb1_vbus: regulator-usb1-vbus {
 
-+		compatible = "regulator-fixed";
 
-+		regulator-name = "usb1-vbus";
 
-+		regulator-min-microvolt = <5000000>;
 
-+		regulator-max-microvolt = <5000000>;
 
-+		vin-supply = <&reg_vcc5v>;
 
-+		enable-active-high;
 
-+		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
 
-+	};
 
-+};
 
-+
 
-+&ehci1 {
 
-+	status = "okay";
 
- };
 
- 
-+/* USB 2 & 3 are on headers only. */
 
-+
 
- &emac0 {
 
- 	pinctrl-names = "default";
 
- 	pinctrl-0 = <&ext_rgmii_pins>;
 
-@@ -76,6 +92,10 @@
 
- 	status = "okay";
 
- };
 
- 
-+&ohci1 {
 
-+	status = "okay";
 
-+};
 
-+
 
- &r_rsb {
 
- 	status = "okay";
 
- 
-@@ -211,3 +231,24 @@
 
- 	pinctrl-0 = <&uart0_ph_pins>;
 
- 	status = "okay";
 
- };
 
-+
 
-+&usbotg {
 
-+	/*
 
-+	 * PHY0 pins are connected to a USB-C socket, but a role switch
 
-+	 * is not implemented: both CC pins are pulled to GND.
 
-+	 * The VBUS pins power the device, so a fixed peripheral mode
 
-+	 * is the best choice.
 
-+	 * The board can be powered via GPIOs, in this case port0 *can*
 
-+	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
 
-+	 * then provided by the GPIOs. Any user of this setup would
 
-+	 * need to adjust the DT accordingly: dr_mode set to "host",
 
-+	 * enabling OHCI0 and EHCI0.
 
-+	 */
 
-+	dr_mode = "peripheral";
 
-+	status = "okay";
 
-+};
 
-+
 
-+&usbphy {
 
-+	usb1_vbus-supply = <&reg_usb1_vbus>;
 
-+	status = "okay";
 
-+};

+ 0 - 305
target/linux/sunxi/patches-6.1/005-v6.6-arm64-dts-allwinner-h616-Split-Orange-Pi-Zero-2-DT.patch
View File 

@@ -1,305 +0,0 @@
 
-From 322bf103204b8f786547acbeed85569254e7088f Mon Sep 17 00:00:00 2001
 
-From: Andre Przywara <[email protected]>
 
-Date: Fri, 4 Aug 2023 18:08:54 +0100
 
-Subject: [PATCH] arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT
 
-
 
-The Orange Pi Zero 2 got a successor (Zero 3), which shares quite some
 
-DT nodes with the Zero 2, but comes with a different PMIC.
 
-
 
-Move the common parts (except the PMIC) into a new shared file, and
 
-include that from the existing board .dts file.
 
-
 
-No functional change, the generated DTB is the same, except for some
 
-phandle numbering differences.
 
-
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Acked-by: Jernej Skrabec <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Jernej Skrabec <[email protected]>
 
----
 
- .../allwinner/sun50i-h616-orangepi-zero.dtsi  | 134 ++++++++++++++++++
 
- .../allwinner/sun50i-h616-orangepi-zero2.dts  | 119 +---------------
 
- 2 files changed, 135 insertions(+), 118 deletions(-)
 
- create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
 
-
 
---- /dev/null
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
 
-@@ -0,0 +1,134 @@
 
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
 
-+/*
 
-+ * Copyright (C) 2020 Arm Ltd.
 
-+ *
 
-+ * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3.
 
-+ * Excludes PMIC nodes and properties, since they are different between the two.
 
-+ */
 
-+
 
-+#include "sun50i-h616.dtsi"
 
-+
 
-+#include <dt-bindings/gpio/gpio.h>
 
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
-+#include <dt-bindings/leds/common.h>
 
-+
 
-+/ {
 
-+	aliases {
 
-+		ethernet0 = &emac0;
 
-+		serial0 = &uart0;
 
-+	};
 
-+
 
-+	chosen {
 
-+		stdout-path = "serial0:115200n8";
 
-+	};
 
-+
 
-+	leds {
 
-+		compatible = "gpio-leds";
 
-+
 
-+		led-0 {
 
-+			function = LED_FUNCTION_POWER;
 
-+			color = <LED_COLOR_ID_RED>;
 
-+			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
 
-+			default-state = "on";
 
-+		};
 
-+
 
-+		led-1 {
 
-+			function = LED_FUNCTION_STATUS;
 
-+			color = <LED_COLOR_ID_GREEN>;
 
-+			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
 
-+		};
 
-+	};
 
-+
 
-+	reg_vcc5v: vcc5v {
 
-+		/* board wide 5V supply directly from the USB-C socket */
 
-+		compatible = "regulator-fixed";
 
-+		regulator-name = "vcc-5v";
 
-+		regulator-min-microvolt = <5000000>;
 
-+		regulator-max-microvolt = <5000000>;
 
-+		regulator-always-on;
 
-+	};
 
-+
 
-+	reg_usb1_vbus: regulator-usb1-vbus {
 
-+		compatible = "regulator-fixed";
 
-+		regulator-name = "usb1-vbus";
 
-+		regulator-min-microvolt = <5000000>;
 
-+		regulator-max-microvolt = <5000000>;
 
-+		vin-supply = <&reg_vcc5v>;
 
-+		enable-active-high;
 
-+		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
 
-+	};
 
-+};
 
-+
 
-+&ehci1 {
 
-+	status = "okay";
 
-+};
 
-+
 
-+/* USB 2 & 3 are on headers only. */
 
-+
 
-+&emac0 {
 
-+	pinctrl-names = "default";
 
-+	pinctrl-0 = <&ext_rgmii_pins>;
 
-+	phy-mode = "rgmii";
 
-+	phy-handle = <&ext_rgmii_phy>;
 
-+	allwinner,rx-delay-ps = <3100>;
 
-+	allwinner,tx-delay-ps = <700>;
 
-+	status = "okay";
 
-+};
 
-+
 
-+&mdio0 {
 
-+	ext_rgmii_phy: ethernet-phy@1 {
 
-+		compatible = "ethernet-phy-ieee802.3-c22";
 
-+		reg = <1>;
 
-+	};
 
-+};
 
-+
 
-+&mmc0 {
 
-+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
 
-+	bus-width = <4>;
 
-+	status = "okay";
 
-+};
 
-+
 
-+&ohci1 {
 
-+	status = "okay";
 
-+};
 
-+
 
-+&spi0  {
 
-+	status = "okay";
 
-+	pinctrl-names = "default";
 
-+	pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
 
-+
 
-+	flash@0 {
 
-+		#address-cells = <1>;
 
-+		#size-cells = <1>;
 
-+		compatible = "jedec,spi-nor";
 
-+		reg = <0>;
 
-+		spi-max-frequency = <40000000>;
 
-+	};
 
-+};
 
-+
 
-+&uart0 {
 
-+	pinctrl-names = "default";
 
-+	pinctrl-0 = <&uart0_ph_pins>;
 
-+	status = "okay";
 
-+};
 
-+
 
-+&usbotg {
 
-+	/*
 
-+	 * PHY0 pins are connected to a USB-C socket, but a role switch
 
-+	 * is not implemented: both CC pins are pulled to GND.
 
-+	 * The VBUS pins power the device, so a fixed peripheral mode
 
-+	 * is the best choice.
 
-+	 * The board can be powered via GPIOs, in this case port0 *can*
 
-+	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
 
-+	 * then provided by the GPIOs. Any user of this setup would
 
-+	 * need to adjust the DT accordingly: dr_mode set to "host",
 
-+	 * enabling OHCI0 and EHCI0.
 
-+	 */
 
-+	dr_mode = "peripheral";
 
-+	status = "okay";
 
-+};
 
-+
 
-+&usbphy {
 
-+	usb1_vbus-supply = <&reg_usb1_vbus>;
 
-+	status = "okay";
 
-+};
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
 
-@@ -5,95 +5,19 @@
 
- 
- /dts-v1/;
 
- 
--#include "sun50i-h616.dtsi"
 
--
 
--#include <dt-bindings/gpio/gpio.h>
 
--#include <dt-bindings/interrupt-controller/arm-gic.h>
 
--#include <dt-bindings/leds/common.h>
 
-+#include "sun50i-h616-orangepi-zero.dtsi"
 
- 
- / {
 
- 	model = "OrangePi Zero2";
 
- 	compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
 
--
 
--	aliases {
 
--		ethernet0 = &emac0;
 
--		serial0 = &uart0;
 
--	};
 
--
 
--	chosen {
 
--		stdout-path = "serial0:115200n8";
 
--	};
 
--
 
--	leds {
 
--		compatible = "gpio-leds";
 
--
 
--		led-0 {
 
--			function = LED_FUNCTION_POWER;
 
--			color = <LED_COLOR_ID_RED>;
 
--			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
 
--			default-state = "on";
 
--		};
 
--
 
--		led-1 {
 
--			function = LED_FUNCTION_STATUS;
 
--			color = <LED_COLOR_ID_GREEN>;
 
--			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
 
--		};
 
--	};
 
--
 
--	reg_vcc5v: vcc5v {
 
--		/* board wide 5V supply directly from the USB-C socket */
 
--		compatible = "regulator-fixed";
 
--		regulator-name = "vcc-5v";
 
--		regulator-min-microvolt = <5000000>;
 
--		regulator-max-microvolt = <5000000>;
 
--		regulator-always-on;
 
--	};
 
--
 
--	reg_usb1_vbus: regulator-usb1-vbus {
 
--		compatible = "regulator-fixed";
 
--		regulator-name = "usb1-vbus";
 
--		regulator-min-microvolt = <5000000>;
 
--		regulator-max-microvolt = <5000000>;
 
--		vin-supply = <&reg_vcc5v>;
 
--		enable-active-high;
 
--		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
 
--	};
 
--};
 
--
 
--&ehci1 {
 
--	status = "okay";
 
- };
 
- 
--/* USB 2 & 3 are on headers only. */
 
--
 
- &emac0 {
 
--	pinctrl-names = "default";
 
--	pinctrl-0 = <&ext_rgmii_pins>;
 
--	phy-mode = "rgmii";
 
--	phy-handle = <&ext_rgmii_phy>;
 
- 	phy-supply = <&reg_dcdce>;
 
--	allwinner,rx-delay-ps = <3100>;
 
--	allwinner,tx-delay-ps = <700>;
 
--	status = "okay";
 
--};
 
--
 
--&mdio0 {
 
--	ext_rgmii_phy: ethernet-phy@1 {
 
--		compatible = "ethernet-phy-ieee802.3-c22";
 
--		reg = <1>;
 
--	};
 
- };
 
- 
- &mmc0 {
 
- 	vmmc-supply = <&reg_dcdce>;
 
--	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
 
--	bus-width = <4>;
 
--	status = "okay";
 
--};
 
--
 
--&ohci1 {
 
--	status = "okay";
 
- };
 
- 
- &r_rsb {
 
-@@ -211,44 +135,3 @@
 
- 	vcc-ph-supply = <&reg_aldo1>;
 
- 	vcc-pi-supply = <&reg_aldo1>;
 
- };
 
--
 
--&spi0  {
 
--	status = "okay";
 
--	pinctrl-names = "default";
 
--	pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
 
--
 
--	flash@0 {
 
--		#address-cells = <1>;
 
--		#size-cells = <1>;
 
--		compatible = "jedec,spi-nor";
 
--		reg = <0>;
 
--		spi-max-frequency = <40000000>;
 
--	};
 
--};
 
--
 
--&uart0 {
 
--	pinctrl-names = "default";
 
--	pinctrl-0 = <&uart0_ph_pins>;
 
--	status = "okay";
 
--};
 
--
 
--&usbotg {
 
--	/*
 
--	 * PHY0 pins are connected to a USB-C socket, but a role switch
 
--	 * is not implemented: both CC pins are pulled to GND.
 
--	 * The VBUS pins power the device, so a fixed peripheral mode
 
--	 * is the best choice.
 
--	 * The board can be powered via GPIOs, in this case port0 *can*
 
--	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
 
--	 * then provided by the GPIOs. Any user of this setup would
 
--	 * need to adjust the DT accordingly: dr_mode set to "host",
 
--	 * enabling OHCI0 and EHCI0.
 
--	 */
 
--	dr_mode = "peripheral";
 
--	status = "okay";
 
--};
 
--
 
--&usbphy {
 
--	usb1_vbus-supply = <&reg_usb1_vbus>;
 
--	status = "okay";
 
--};

+ 0 - 140
target/linux/sunxi/patches-6.1/006-v6.6-arm64-dts-allwinner-h616-Add-OrangePi-Zero-3-board.patch
View File 

@@ -1,140 +0,0 @@
 
-From f1b3ddb3ecc2eec1f912383e01156c226daacfab Mon Sep 17 00:00:00 2001
 
-From: Andre Przywara <[email protected]>
 
-Date: Fri, 4 Aug 2023 18:08:56 +0100
 
-Subject: [PATCH] arm64: dts: allwinner: h616: Add OrangePi Zero 3 board
 
- support
 
-
 
-The OrangePi Zero 3 is a development board based on the Allwinner H618 SoC,
 
-which seems to be just an H616 with more L2 cache. The board itself is a
 
-slightly updated version of the Orange Pi Zero 2. It features:
 
-- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
 
-- 1/1.5/2/4 GiB LPDDR4 DRAM SKUs (only up to 1GB on the Zero2)
 
-- AXP313a PMIC (more capable AXP305 on the Zero2)
 
-- Raspberry-Pi-1 compatible GPIO header
 
-- extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
 
-- 1 USB 2.0 host port
 
-- 1 USB 2.0 type C port (power supply + OTG)
 
-- MicroSD slot
 
-- on-board 16MiB bootable SPI NOR flash (only 2MB on the Zero2)
 
-- 1Gbps Ethernet port (via Motorcomm YT8531 PHY) (RTL8211 on the Zero2)
 
-- micro-HDMI port
 
-- (yet) unsupported Allwinner WiFi/BT chip
 
-
 
-Add the devicetree file describing the currently supported features,
 
-namely LEDs, SD card, PMIC, SPI flash, USB. Ethernet seems unstable at
 
-the moment, though the basic functionality works.
 
-
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Reviewed-by: Jernej Skrabec <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Jernej Skrabec <[email protected]>
 
----
 
- arch/arm64/boot/dts/allwinner/Makefile        |  1 +
 
- .../allwinner/sun50i-h618-orangepi-zero3.dts  | 94 +++++++++++++++++++
 
- 2 files changed, 95 insertions(+)
 
- create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
 
-
 
---- a/arch/arm64/boot/dts/allwinner/Makefile
 
-+++ b/arch/arm64/boot/dts/allwinner/Makefile
 
-@@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-ta
 
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
 
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
 
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
 
-+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
 
---- /dev/null
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
 
-@@ -0,0 +1,94 @@
 
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
 
-+/*
 
-+ * Copyright (C) 2023 Arm Ltd.
 
-+ */
 
-+
 
-+/dts-v1/;
 
-+
 
-+#include "sun50i-h616-orangepi-zero.dtsi"
 
-+
 
-+/ {
 
-+	model = "OrangePi Zero3";
 
-+	compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
 
-+};
 
-+
 
-+&emac0 {
 
-+	phy-supply = <&reg_dldo1>;
 
-+};
 
-+
 
-+&ext_rgmii_phy {
 
-+	motorcomm,clk-out-frequency-hz = <125000000>;
 
-+};
 
-+
 
-+&mmc0 {
 
-+	/*
 
-+	 * The schematic shows the card detect pin wired up to PF6, via an
 
-+	 * inverter, but it just doesn't work.
 
-+	 */
 
-+	broken-cd;
 
-+	vmmc-supply = <&reg_dldo1>;
 
-+};
 
-+
 
-+&r_i2c {
 
-+	status = "okay";
 
-+
 
-+	axp313: pmic@36 {
 
-+		compatible = "x-powers,axp313a";
 
-+		reg = <0x36>;
 
-+		#interrupt-cells = <1>;
 
-+		interrupt-controller;
 
-+		interrupt-parent = <&pio>;
 
-+		interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9 */
 
-+
 
-+		vin1-supply = <&reg_vcc5v>;
 
-+		vin2-supply = <&reg_vcc5v>;
 
-+		vin3-supply = <&reg_vcc5v>;
 
-+
 
-+		regulators {
 
-+			/* Supplies VCC-PLL, so needs to be always on. */
 
-+			reg_aldo1: aldo1 {
 
-+				regulator-always-on;
 
-+				regulator-min-microvolt = <1800000>;
 
-+				regulator-max-microvolt = <1800000>;
 
-+				regulator-name = "vcc1v8";
 
-+			};
 
-+
 
-+			/* Supplies VCC-IO, so needs to be always on. */
 
-+			reg_dldo1: dldo1 {
 
-+				regulator-always-on;
 
-+				regulator-min-microvolt = <3300000>;
 
-+				regulator-max-microvolt = <3300000>;
 
-+				regulator-name = "vcc3v3";
 
-+			};
 
-+
 
-+			reg_dcdc1: dcdc1 {
 
-+				regulator-always-on;
 
-+				regulator-min-microvolt = <810000>;
 
-+				regulator-max-microvolt = <990000>;
 
-+				regulator-name = "vdd-gpu-sys";
 
-+			};
 
-+
 
-+			reg_dcdc2: dcdc2 {
 
-+				regulator-always-on;
 
-+				regulator-min-microvolt = <810000>;
 
-+				regulator-max-microvolt = <1100000>;
 
-+				regulator-name = "vdd-cpu";
 
-+			};
 
-+
 
-+			reg_dcdc3: dcdc3 {
 
-+				regulator-always-on;
 
-+				regulator-min-microvolt = <1100000>;
 
-+				regulator-max-microvolt = <1100000>;
 
-+				regulator-name = "vdd-dram";
 
-+			};
 
-+		};
 
-+	};
 
-+};
 
-+
 
-+&pio {
 
-+	vcc-pc-supply = <&reg_dldo1>;
 
-+	vcc-pf-supply = <&reg_dldo1>;
 
-+	vcc-pg-supply = <&reg_aldo1>;
 
-+	vcc-ph-supply = <&reg_dldo1>;
 
-+	vcc-pi-supply = <&reg_dldo1>;
 
-+};

+ 0 - 57
target/linux/sunxi/patches-6.1/007-v6.7-arm64-dts-allwinner-h616-update-emac-for-Orange-Pi.patch
View File 

@@ -1,57 +0,0 @@
 
-From b9622937d95809ef89904583191571a9fa326402 Mon Sep 17 00:00:00 2001
 
-From: Chukun Pan <[email protected]>
 
-Date: Sun, 29 Oct 2023 15:40:09 +0800
 
-Subject: [PATCH] arm64: dts: allwinner: h616: update emac for Orange Pi Zero 3
 
-
 
-The current emac setting is not suitable for Orange Pi Zero 3,
 
-move it back to Orange Pi Zero 2 DT. Also update phy mode and
 
-delay values for emac on Orange Pi Zero 3.
 
-With these changes, Ethernet now looks stable.
 
-
 
-Fixes: 322bf103204b ("arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT")
 
-Signed-off-by: Chukun Pan <[email protected]>
 
-Reviewed-by: Jernej Skrabec <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Jernej Skrabec <[email protected]>
 
----
 
- arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 3 ---
 
- arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 3 +++
 
- arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 2 ++
 
- 3 files changed, 5 insertions(+), 3 deletions(-)
 
-
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
 
-@@ -68,10 +68,7 @@
 
- &emac0 {
 
- 	pinctrl-names = "default";
 
- 	pinctrl-0 = <&ext_rgmii_pins>;
 
--	phy-mode = "rgmii";
 
- 	phy-handle = <&ext_rgmii_phy>;
 
--	allwinner,rx-delay-ps = <3100>;
 
--	allwinner,tx-delay-ps = <700>;
 
- 	status = "okay";
 
- };
 
- 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
 
-@@ -13,6 +13,9 @@
 
- };
 
- 
- &emac0 {
 
-+	allwinner,rx-delay-ps = <3100>;
 
-+	allwinner,tx-delay-ps = <700>;
 
-+	phy-mode = "rgmii";
 
- 	phy-supply = <&reg_dcdce>;
 
- };
 
- 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
 
-@@ -13,6 +13,8 @@
 
- };
 
- 
- &emac0 {
 
-+	allwinner,tx-delay-ps = <700>;
 
-+	phy-mode = "rgmii-rxid";
 
- 	phy-supply = <&reg_dldo1>;
 
- };
 
-

+ 0 - 31
target/linux/sunxi/patches-6.1/008-v6.7-arm64-dts-allwinner-h616-Add-SID-controller-node.patch
View File 

@@ -1,31 +0,0 @@
 
-From 951992797378a2177946400438f4d23c9fceae5b Mon Sep 17 00:00:00 2001
 
-From: Martin Botka <[email protected]>
 
-Date: Tue, 12 Sep 2023 14:25:13 +0200
 
-Subject: [PATCH] arm64: dts: allwinner: h616: Add SID controller node
 
-
 
-Add node for the H616 SID controller
 
-
 
-Signed-off-by: Martin Botka <[email protected]>
 
-Acked-by: Jernej Skrabec <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Jernej Skrabec <[email protected]>
 
----
 
- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 7 +++++++
 
- 1 file changed, 7 insertions(+)
 
-
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
 
-@@ -133,6 +133,13 @@
 
- 			#reset-cells = <1>;
 
- 		};
 
- 
-+		sid: efuse@3006000 {
 
-+			compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
 
-+			reg = <0x03006000 0x1000>;
 
-+			#address-cells = <1>;
 
-+			#size-cells = <1>;
 
-+		};
 
-+
 
- 		watchdog: watchdog@30090a0 {
 
- 			compatible = "allwinner,sun50i-h616-wdt",
 
- 				     "allwinner,sun6i-a31-wdt";

+ 0 - 98
target/linux/sunxi/patches-6.1/009-v6.9-soc-sunxi-sram-export-register-0-for-THS-on-H616.patch
View File 

@@ -1,98 +0,0 @@
 
-From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001
 
-From: Andre Przywara <[email protected]>
 
-Date: Mon, 19 Feb 2024 15:36:33 +0000
 
-Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616
 
-
 
-The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
 
-in the SRAM control block. If bit 16 is set (the reset value), the
 
-temperature readings of the THS are way off, leading to reports about
 
-200C, at normal ambient temperatures. Clearing this bits brings the
 
-reported values down to the expected values.
 
-The BSP code clears this bit in firmware (U-Boot), and has an explicit
 
-comment about this, but offers no real explanation.
 
-
 
-Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
 
-visibility: all tested bit settings still allow full read and write
 
-access by the CPU to the whole of SRAM C. Only bit 24 of the register at
 
-offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
 
-the THS switch functionality as an SRAM region would not reflect reality.
 
-
 
-Since we should not rely on firmware settings, allow other code (the THS
 
-driver) to access this register, by exporting it through the already
 
-existing regmap. This mimics what we already do for the LDO control and
 
-the EMAC register.
 
-
 
-To avoid concurrent accesses to the same register at the same time, by
 
-the SRAM switch code and the regmap code, use the same lock to protect
 
-the access. The regmap subsystem allows to use an existing lock, so we
 
-just need to hook in there.
 
-
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Reviewed-by: Jernej Skrabec <[email protected]>
 
-Signed-off-by: Daniel Lezcano <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
----
 
- drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++
 
- 1 file changed, 22 insertions(+)
 
-
 
---- a/drivers/soc/sunxi/sunxi_sram.c
 
-+++ b/drivers/soc/sunxi/sunxi_sram.c
 
-@@ -284,6 +284,7 @@ EXPORT_SYMBOL(sunxi_sram_release);
 
- struct sunxi_sramc_variant {
 
- 	int num_emac_clocks;
 
- 	bool has_ldo_ctrl;
 
-+	bool has_ths_offset;
 
- };
 
- 
- static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
 
-@@ -305,8 +306,10 @@ static const struct sunxi_sramc_variant
 
- 
- static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
 
- 	.num_emac_clocks = 2,
 
-+	.has_ths_offset = true,
 
- };
 
- 
-+#define SUNXI_SRAM_THS_OFFSET_REG	0x0
 
- #define SUNXI_SRAM_EMAC_CLOCK_REG	0x30
 
- #define SUNXI_SYS_LDO_CTRL_REG		0x150
 
- 
-@@ -315,6 +318,8 @@ static bool sunxi_sram_regmap_accessible
 
- {
 
- 	const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
 
- 
-+	if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset)
 
-+		return true;
 
- 	if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
 
- 	    reg <  SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
 
- 		return true;
 
-@@ -324,6 +329,20 @@ static bool sunxi_sram_regmap_accessible
 
- 	return false;
 
- }
 
- 
-+static void sunxi_sram_lock(void *_lock)
 
-+{
 
-+	spinlock_t *lock = _lock;
 
-+
 
-+	spin_lock(lock);
 
-+}
 
-+
 
-+static void sunxi_sram_unlock(void *_lock)
 
-+{
 
-+	spinlock_t *lock = _lock;
 
-+
 
-+	spin_unlock(lock);
 
-+}
 
-+
 
- static struct regmap_config sunxi_sram_regmap_config = {
 
- 	.reg_bits       = 32,
 
- 	.val_bits       = 32,
 
-@@ -333,6 +352,9 @@ static struct regmap_config sunxi_sram_r
 
- 	/* other devices have no business accessing other registers */
 
- 	.readable_reg	= sunxi_sram_regmap_accessible_reg,
 
- 	.writeable_reg	= sunxi_sram_regmap_accessible_reg,
 
-+	.lock		= sunxi_sram_lock,
 
-+	.unlock		= sunxi_sram_unlock,
 
-+	.lock_arg	= &sram_lock,
 
- };
 
- 
- static int __init sunxi_sram_probe(struct platform_device *pdev)

+ 0 - 47
target/linux/sunxi/patches-6.1/010-v6.8-thermal-drivers-sun8i-Add-D1-T113s-THS-controller-support.patch
View File 

@@ -1,47 +0,0 @@
 
-From ebbf19e36d021f253425344b4d4b987f3b7d9be5 Mon Sep 17 00:00:00 2001
 
-From: Maxim Kiselev <[email protected]>
 
-Date: Mon, 18 Dec 2023 00:06:23 +0300
 
-Subject: [PATCH] thermal/drivers/sun8i: Add D1/T113s THS controller support
 
-
 
-This patch adds a thermal sensor controller support for the D1/T113s,
 
-which is similar to the one on H6, but with only one sensor and
 
-different scale and offset values.
 
-
 
-Signed-off-by: Maxim Kiselev <[email protected]>
 
-Acked-by: Jernej Skrabec <[email protected]>
 
-Reviewed-by: Andre Przywara <[email protected]>
 
-Signed-off-by: Daniel Lezcano <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
----
 
- drivers/thermal/sun8i_thermal.c | 13 +++++++++++++
 
- 1 file changed, 13 insertions(+)
 
-
 
---- a/drivers/thermal/sun8i_thermal.c
 
-+++ b/drivers/thermal/sun8i_thermal.c
 
-@@ -610,6 +610,18 @@ static const struct ths_thermal_chip sun
 
- 	.calc_temp = sun8i_ths_calc_temp,
 
- };
 
- 
-+static const struct ths_thermal_chip sun20i_d1_ths = {
 
-+	.sensor_num = 1,
 
-+	.has_bus_clk_reset = true,
 
-+	.offset = 188552,
 
-+	.scale = 673,
 
-+	.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
 
-+	.calibrate = sun50i_h6_ths_calibrate,
 
-+	.init = sun50i_h6_thermal_init,
 
-+	.irq_ack = sun50i_h6_irq_ack,
 
-+	.calc_temp = sun8i_ths_calc_temp,
 
-+};
 
-+
 
- static const struct of_device_id of_ths_match[] = {
 
- 	{ .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
 
- 	{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
 
-@@ -618,6 +630,7 @@ static const struct of_device_id of_ths_
 
- 	{ .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
 
- 	{ .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
 
- 	{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
 
-+	{ .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
 
- 	{ /* sentinel */ },
 
- };
 
- MODULE_DEVICE_TABLE(of, of_ths_match);

+ 0 - 79
target/linux/sunxi/patches-6.1/011-v6.9-thermal-drivers-sun8i-Explain-unknown-H6-register-value.patch
View File 

@@ -1,79 +0,0 @@
 
-From 14f118aa50fe7c7c7330f56d007ecacca487cea8 Mon Sep 17 00:00:00 2001
 
-From: Andre Przywara <[email protected]>
 
-Date: Mon, 19 Feb 2024 15:36:35 +0000
 
-Subject: [PATCH] thermal/drivers/sun8i: Explain unknown H6 register value
 
-
 
-So far we were ORing in some "unknown" value into the THS control
 
-register on the Allwinner H6. This part of the register is not explained
 
-in the H6 manual, but the H616 manual details those bits, and on closer
 
-inspection the THS IP blocks in both SoCs seem very close:
 
-- The BSP code for both SoCs writes the same values into THS_CTRL.
 
-- The reset values of at least the first three registers are the same.
 
-
 
-Replace the "unknown" value with its proper meaning: "acquire time",
 
-most probably the sample part of the sample & hold circuit of the ADC,
 
-according to its explanation in the H616 manual.
 
-
 
-No functional change, just a macro rename and adjustment.
 
-
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Reviewed-by: Jernej Skrabec <[email protected]>
 
-Acked-by: Vasily Khoruzhick <[email protected]>
 
-Signed-off-by: Daniel Lezcano <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
----
 
- drivers/thermal/sun8i_thermal.c | 29 ++++++++++++++++-------------
 
- 1 file changed, 16 insertions(+), 13 deletions(-)
 
-
 
---- a/drivers/thermal/sun8i_thermal.c
 
-+++ b/drivers/thermal/sun8i_thermal.c
 
-@@ -50,7 +50,8 @@
 
- #define SUN8I_THS_CTRL2_T_ACQ1(x)		((GENMASK(15, 0) & (x)) << 16)
 
- #define SUN8I_THS_DATA_IRQ_STS(x)		BIT(x + 8)
 
- 
--#define SUN50I_THS_CTRL0_T_ACQ(x)		((GENMASK(15, 0) & (x)) << 16)
 
-+#define SUN50I_THS_CTRL0_T_ACQ(x)		(GENMASK(15, 0) & ((x) - 1))
 
-+#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x)	((GENMASK(15, 0) & ((x) - 1)) << 16)
 
- #define SUN50I_THS_FILTER_EN			BIT(2)
 
- #define SUN50I_THS_FILTER_TYPE(x)		(GENMASK(1, 0) & (x))
 
- #define SUN50I_H6_THS_PC_TEMP_PERIOD(x)		((GENMASK(19, 0) & (x)) << 12)
 
-@@ -410,25 +411,27 @@ static int sun8i_h3_thermal_init(struct
 
- 	return 0;
 
- }
 
- 
--/*
 
-- * Without this undocumented value, the returned temperatures would
 
-- * be higher than real ones by about 20C.
 
-- */
 
--#define SUN50I_H6_CTRL0_UNK 0x0000002f
 
--
 
- static int sun50i_h6_thermal_init(struct ths_device *tmdev)
 
- {
 
- 	int val;
 
- 
- 	/*
 
--	 * T_acq = 20us
 
--	 * clkin = 24MHz
 
--	 *
 
--	 * x = T_acq * clkin - 1
 
--	 *   = 479
 
-+	 * The manual recommends an overall sample frequency of 50 KHz (20us,
 
-+	 * 480 cycles at 24 MHz), which provides plenty of time for both the
 
-+	 * acquisition time (>24 cycles) and the actual conversion time
 
-+	 * (>14 cycles).
 
-+	 * The lower half of the CTRL register holds the "acquire time", in
 
-+	 * clock cycles, which the manual recommends to be 2us:
 
-+	 * 24MHz * 2us = 48 cycles.
 
-+	 * The high half of THS_CTRL encodes the sample frequency, in clock
 
-+	 * cycles: 24MHz * 20us = 480 cycles.
 
-+	 * This is explained in the H616 manual, but apparently wrongly
 
-+	 * described in the H6 manual, although the BSP code does the same
 
-+	 * for both SoCs.
 
- 	 */
 
- 	regmap_write(tmdev->regmap, SUN50I_THS_CTRL0,
 
--		     SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479));
 
-+		     SUN50I_THS_CTRL0_T_ACQ(48) |
 
-+		     SUN50I_THS_CTRL0_T_SAMPLE_PER(480));
 
- 	/* average over 4 samples */
 
- 	regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC,
 
- 		     SUN50I_THS_FILTER_EN |

+ 0 - 74
target/linux/sunxi/patches-6.1/012-v6.9-thermal-drivers-sun8i-Extend-H6-calibration-to-support-4.patch
View File 

@@ -1,74 +0,0 @@
 
-From 6c04a419a4c5fb18edefc44dd676fb95c7f6c55d Mon Sep 17 00:00:00 2001
 
-From: Maksim Kiselev <[email protected]>
 
-Date: Mon, 19 Feb 2024 15:36:36 +0000
 
-Subject: [PATCH] thermal/drivers/sun8i: Extend H6 calibration to support 4
 
- sensors
 
-
 
-The H616 SoC resembles the H6 thermal sensor controller, with a few
 
-changes like four sensors.
 
-
 
-Extend sun50i_h6_ths_calibrate() function to support calibration of
 
-these sensors.
 
-
 
-Co-developed-by: Martin Botka <[email protected]>
 
-Signed-off-by: Martin Botka <[email protected]>
 
-Signed-off-by: Maksim Kiselev <[email protected]>
 
-Reviewed-by: Andre Przywara <[email protected]>
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Reviewed-by: Jernej Skrabec <[email protected]>
 
-Acked-by: Vasily Khoruzhick <[email protected]>
 
-Signed-off-by: Daniel Lezcano <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
----
 
- drivers/thermal/sun8i_thermal.c | 28 ++++++++++++++++++++--------
 
- 1 file changed, 20 insertions(+), 8 deletions(-)
 
-
 
---- a/drivers/thermal/sun8i_thermal.c
 
-+++ b/drivers/thermal/sun8i_thermal.c
 
-@@ -224,16 +224,21 @@ static int sun50i_h6_ths_calibrate(struc
 
- 	struct device *dev = tmdev->dev;
 
- 	int i, ft_temp;
 
- 
--	if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num)
 
-+	if (!caldata[0])
 
- 		return -EINVAL;
 
- 
- 	/*
 
- 	 * efuse layout:
 
- 	 *
 
--	 *	0   11  16	 32
 
--	 *	+-------+-------+-------+
 
--	 *	|temp|  |sensor0|sensor1|
 
--	 *	+-------+-------+-------+
 
-+	 * 0      11  16     27   32     43   48    57
 
-+	 * +----------+-----------+-----------+-----------+
 
-+	 * |  temp |  |sensor0|   |sensor1|   |sensor2|   |
 
-+	 * +----------+-----------+-----------+-----------+
 
-+	 *                      ^           ^           ^
 
-+	 *                      |           |           |
 
-+	 *                      |           |           sensor3[11:8]
 
-+	 *                      |           sensor3[7:4]
 
-+	 *                      sensor3[3:0]
 
- 	 *
 
- 	 * The calibration data on the H6 is the ambient temperature and
 
- 	 * sensor values that are filled during the factory test stage.
 
-@@ -246,9 +251,16 @@ static int sun50i_h6_ths_calibrate(struc
 
- 	ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
 
- 
- 	for (i = 0; i < tmdev->chip->sensor_num; i++) {
 
--		int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
 
--		int cdata, offset;
 
--		int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
 
-+		int sensor_reg, sensor_temp, cdata, offset;
 
-+
 
-+		if (i == 3)
 
-+			sensor_reg = (caldata[1] >> 12)
 
-+				     | ((caldata[2] >> 12) << 4)
 
-+				     | ((caldata[3] >> 12) << 8);
 
-+		else
 
-+			sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
 
-+
 
-+		sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
 
- 
- 		/*
 
- 		 * Calibration data is CALIBRATE_DEFAULT - (calculated

+ 0 - 126
target/linux/sunxi/patches-6.1/013-v6.9-thermal-drivers-sun8i-Add-SRAM-register-access-code.patch
View File 

@@ -1,126 +0,0 @@
 
-From f8b54d1120b81ed57bed96cc8e814ba08886d1e5 Mon Sep 17 00:00:00 2001
 
-From: Andre Przywara <[email protected]>
 
-Date: Mon, 19 Feb 2024 15:36:37 +0000
 
-Subject: [PATCH] thermal/drivers/sun8i: Add SRAM register access code
 
-
 
-The Allwinner H616 SoC needs to clear a bit in one register in the SRAM
 
-controller, to report reasonable temperature values. On reset, bit 16 in
 
-register 0x3000000 is set, which leads to the driver reporting
 
-temperatures around 200C. Clearing this bit brings the values down to the
 
-expected range. The BSP code does a one-time write in U-Boot, with a
 
-comment just mentioning the effect on the THS, but offering no further
 
-explanation.
 
-
 
-To not rely on firmware to set things up for us, add code that queries
 
-the SRAM controller device via a DT phandle link, then clear just this
 
-single bit.
 
-
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Acked-by: Vasily Khoruzhick <[email protected]>
 
-Signed-off-by: Daniel Lezcano <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
----
 
- drivers/thermal/sun8i_thermal.c | 51 +++++++++++++++++++++++++++++++++
 
- 1 file changed, 51 insertions(+)
 
-
 
---- a/drivers/thermal/sun8i_thermal.c
 
-+++ b/drivers/thermal/sun8i_thermal.c
 
-@@ -15,6 +15,7 @@
 
- #include <linux/module.h>
 
- #include <linux/nvmem-consumer.h>
 
- #include <linux/of_device.h>
 
-+#include <linux/of_platform.h>
 
- #include <linux/platform_device.h>
 
- #include <linux/regmap.h>
 
- #include <linux/reset.h>
 
-@@ -68,6 +69,7 @@ struct tsensor {
 
- struct ths_thermal_chip {
 
- 	bool            has_mod_clk;
 
- 	bool            has_bus_clk_reset;
 
-+	bool		needs_sram;
 
- 	int		sensor_num;
 
- 	int		offset;
 
- 	int		scale;
 
-@@ -85,12 +87,16 @@ struct ths_device {
 
- 	const struct ths_thermal_chip		*chip;
 
- 	struct device				*dev;
 
- 	struct regmap				*regmap;
 
-+	struct regmap_field			*sram_regmap_field;
 
- 	struct reset_control			*reset;
 
- 	struct clk				*bus_clk;
 
- 	struct clk                              *mod_clk;
 
- 	struct tsensor				sensor[MAX_SENSOR_NUM];
 
- };
 
- 
-+/* The H616 needs to have a bit 16 in the SRAM control register cleared. */
 
-+static const struct reg_field sun8i_ths_sram_reg_field = REG_FIELD(0x0, 16, 16);
 
-+
 
- /* Temp Unit: millidegree Celsius */
 
- static int sun8i_ths_calc_temp(struct ths_device *tmdev,
 
- 			       int id, int reg)
 
-@@ -337,6 +343,34 @@ static void sun8i_ths_reset_control_asse
 
- 	reset_control_assert(data);
 
- }
 
- 
-+static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node)
 
-+{
 
-+	struct device_node *sram_node;
 
-+	struct platform_device *sram_pdev;
 
-+	struct regmap *regmap = NULL;
 
-+
 
-+	sram_node = of_parse_phandle(node, "allwinner,sram", 0);
 
-+	if (!sram_node)
 
-+		return ERR_PTR(-ENODEV);
 
-+
 
-+	sram_pdev = of_find_device_by_node(sram_node);
 
-+	if (!sram_pdev) {
 
-+		/* platform device might not be probed yet */
 
-+		regmap = ERR_PTR(-EPROBE_DEFER);
 
-+		goto out_put_node;
 
-+	}
 
-+
 
-+	/* If no regmap is found then the other device driver is at fault */
 
-+	regmap = dev_get_regmap(&sram_pdev->dev, NULL);
 
-+	if (!regmap)
 
-+		regmap = ERR_PTR(-EINVAL);
 
-+
 
-+	platform_device_put(sram_pdev);
 
-+out_put_node:
 
-+	of_node_put(sram_node);
 
-+	return regmap;
 
-+}
 
-+
 
- static int sun8i_ths_resource_init(struct ths_device *tmdev)
 
- {
 
- 	struct device *dev = tmdev->dev;
 
-@@ -381,6 +415,19 @@ static int sun8i_ths_resource_init(struc
 
- 	if (ret)
 
- 		return ret;
 
- 
-+	if (tmdev->chip->needs_sram) {
 
-+		struct regmap *regmap;
 
-+
 
-+		regmap = sun8i_ths_get_sram_regmap(dev->of_node);
 
-+		if (IS_ERR(regmap))
 
-+			return PTR_ERR(regmap);
 
-+		tmdev->sram_regmap_field = devm_regmap_field_alloc(dev,
 
-+						      regmap,
 
-+						      sun8i_ths_sram_reg_field);
 
-+		if (IS_ERR(tmdev->sram_regmap_field))
 
-+			return PTR_ERR(tmdev->sram_regmap_field);
 
-+	}
 
-+
 
- 	ret = sun8i_ths_calibrate(tmdev);
 
- 	if (ret)
 
- 		return ret;
 
-@@ -427,6 +474,10 @@ static int sun50i_h6_thermal_init(struct
 
- {
 
- 	int val;
 
- 
-+	/* The H616 needs to have a bit in the SRAM control register cleared. */
 
-+	if (tmdev->sram_regmap_field)
 
-+		regmap_field_write(tmdev->sram_regmap_field, 0);
 
-+
 
- 	/*
 
- 	 * The manual recommends an overall sample frequency of 50 KHz (20us,
 
- 	 * 480 cycles at 24 MHz), which provides plenty of time for both the

+ 0 - 50
target/linux/sunxi/patches-6.1/014-v6.9-thermal-drivers-sun8i-Add-support-for-H616-THS-controller.patch
View File 

@@ -1,50 +0,0 @@
 
-From e7dbfa19572a1440a2e67ef70f94ff204849a0a8 Mon Sep 17 00:00:00 2001
 
-From: Martin Botka <[email protected]>
 
-Date: Mon, 19 Feb 2024 15:36:38 +0000
 
-Subject: [PATCH] thermal/drivers/sun8i: Add support for H616 THS controller
 
-
 
-Add support for the thermal sensor found in H616 SoCs, is the same as
 
-the H6 thermal sensor controller, but with four sensors.
 
-Also the registers readings are wrong, unless a bit in the first SYS_CFG
 
-register cleared, so set exercise the SRAM regmap to take care of that.
 
-
 
-Signed-off-by: Martin Botka <[email protected]>
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Acked-by: Vasily Khoruzhick <[email protected]>
 
-Signed-off-by: Daniel Lezcano <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
----
 
- drivers/thermal/sun8i_thermal.c | 15 +++++++++++++++
 
- 1 file changed, 15 insertions(+)
 
-
 
---- a/drivers/thermal/sun8i_thermal.c
 
-+++ b/drivers/thermal/sun8i_thermal.c
 
-@@ -688,6 +688,20 @@ static const struct ths_thermal_chip sun
 
- 	.calc_temp = sun8i_ths_calc_temp,
 
- };
 
- 
-+static const struct ths_thermal_chip sun50i_h616_ths = {
 
-+	.sensor_num = 4,
 
-+	.has_bus_clk_reset = true,
 
-+	.needs_sram = true,
 
-+	.ft_deviation = 8000,
 
-+	.offset = 263655,
 
-+	.scale = 810,
 
-+	.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
 
-+	.calibrate = sun50i_h6_ths_calibrate,
 
-+	.init = sun50i_h6_thermal_init,
 
-+	.irq_ack = sun50i_h6_irq_ack,
 
-+	.calc_temp = sun8i_ths_calc_temp,
 
-+};
 
-+
 
- static const struct of_device_id of_ths_match[] = {
 
- 	{ .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
 
- 	{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
 
-@@ -697,6 +711,7 @@ static const struct of_device_id of_ths_
 
- 	{ .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
 
- 	{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
 
- 	{ .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
 
-+	{ .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths },
 
- 	{ /* sentinel */ },
 
- };
 
- MODULE_DEVICE_TABLE(of, of_ths_match);

+ 0 - 68
target/linux/sunxi/patches-6.1/015-v6.9-thermal-drivers-sun8i-Dont-fail-probe-due-to-zone-registra.patch
View File 

@@ -1,68 +0,0 @@
 
-From 9ac53d5532cc4bb595bbee86ccba2172ccc336c3 Mon Sep 17 00:00:00 2001
 
-From: Mark Brown <[email protected]>
 
-Date: Tue, 23 Jan 2024 23:33:07 +0000
 
-Subject: [PATCH] thermal/drivers/sun8i: Don't fail probe due to zone
 
- registration failure
 
-
 
-Currently the sun8i thermal driver will fail to probe if any of the
 
-thermal zones it is registering fails to register with the thermal core.
 
-Since we currently do not define any trip points for the GPU thermal
 
-zones on at least A64 or H5 this means that we have no thermal support
 
-on these platforms:
 
-
 
-[    1.698703] thermal_sys: Failed to find 'trips' node
 
-[    1.698707] thermal_sys: Failed to find trip points for thermal-sensor id=1
 
-
 
-even though the main CPU thermal zone on both SoCs is fully configured.
 
-This does not seem ideal, while we may not be able to use all the zones
 
-it seems better to have those zones which are usable be operational.
 
-Instead just carry on registering zones if we get any non-deferral
 
-error, allowing use of those zones which are usable.
 
-
 
-This means that we also need to update the interrupt handler to not
 
-attempt to notify the core for events on zones which we have not
 
-registered, I didn't see an ability to mask individual interrupts and
 
-I would expect that interrupts would still be indicated in the ISR even
 
-if they were masked.
 
-
 
-Reviewed-by: Vasily Khoruzhick <[email protected]>
 
-Acked-by: Jernej Skrabec <[email protected]>
 
-Signed-off-by: Mark Brown <[email protected]>
 
-Signed-off-by: Daniel Lezcano <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
----
 
- drivers/thermal/sun8i_thermal.c | 16 ++++++++++++++--
 
- 1 file changed, 14 insertions(+), 2 deletions(-)
 
-
 
---- a/drivers/thermal/sun8i_thermal.c
 
-+++ b/drivers/thermal/sun8i_thermal.c
 
-@@ -197,6 +197,9 @@ static irqreturn_t sun8i_irq_thread(int
 
- 	int i;
 
- 
- 	for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) {
 
-+		/* We allow some zones to not register. */
 
-+		if (IS_ERR(tmdev->sensor[i].tzd))
 
-+			continue;
 
- 		thermal_zone_device_update(tmdev->sensor[i].tzd,
 
- 					   THERMAL_EVENT_UNSPECIFIED);
 
- 	}
 
-@@ -531,8 +534,17 @@ static int sun8i_ths_register(struct ths
 
- 						      i,
 
- 						      &tmdev->sensor[i],
 
- 						      &ths_ops);
 
--		if (IS_ERR(tmdev->sensor[i].tzd))
 
--			return PTR_ERR(tmdev->sensor[i].tzd);
 
-+
 
-+		/*
 
-+		 * If an individual zone fails to register for reasons
 
-+		 * other than probe deferral (eg, a bad DT) then carry
 
-+		 * on, other zones might register successfully.
 
-+		 */
 
-+		if (IS_ERR(tmdev->sensor[i].tzd)) {
 
-+			if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
 
-+				return PTR_ERR(tmdev->sensor[i].tzd);
 
-+			continue;
 
-+		}
 
- 
- 		if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd))
 
- 			dev_warn(tmdev->dev,

+ 0 - 138
target/linux/sunxi/patches-6.1/016-v6.9-arm64-dts-allwinner-h616-Add-thermal-sensor-and-zones.patch
View File 

@@ -1,138 +0,0 @@
 
-From f4318af40544b8e7ff5a6b667ede60e6cf808262 Mon Sep 17 00:00:00 2001
 
-From: Martin Botka <[email protected]>
 
-Date: Mon, 19 Feb 2024 15:36:39 +0000
 
-Subject: [PATCH] arm64: dts: allwinner: h616: Add thermal sensor and zones
 
-
 
-There are four thermal sensors:
 
-- CPU
 
-- GPU
 
-- VE
 
-- DRAM
 
-
 
-Add the thermal sensor configuration and the thermal zones.
 
-
 
-Signed-off-by: Martin Botka <[email protected]>
 
-Signed-off-by: Andre Przywara <[email protected]>
 
-Reviewed-by: Jernej Skrabec <[email protected]>
 
-Link: https://lore.kernel.org/r/[email protected]
 
-Signed-off-by: Jernej Skrabec <[email protected]>
 
----
 
- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 88 +++++++++++++++++++
 
- 1 file changed, 88 insertions(+)
 
-
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
 
-@@ -9,6 +9,7 @@
 
- #include <dt-bindings/clock/sun6i-rtc.h>
 
- #include <dt-bindings/reset/sun50i-h616-ccu.h>
 
- #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
 
-+#include <dt-bindings/thermal/thermal.h>
 
- 
- / {
 
- 	interrupt-parent = <&gic>;
 
-@@ -138,6 +139,10 @@
 
- 			reg = <0x03006000 0x1000>;
 
- 			#address-cells = <1>;
 
- 			#size-cells = <1>;
 
-+
 
-+			ths_calibration: thermal-sensor-calibration@14 {
 
-+				reg = <0x14 0x8>;
 
-+			};
 
- 		};
 
- 
- 		watchdog: watchdog@30090a0 {
 
-@@ -511,6 +516,19 @@
 
- 			};
 
- 		};
 
- 
-+		ths: thermal-sensor@5070400 {
 
-+			compatible = "allwinner,sun50i-h616-ths";
 
-+			reg = <0x05070400 0x400>;
 
-+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 
-+			clocks = <&ccu CLK_BUS_THS>;
 
-+			clock-names = "bus";
 
-+			resets = <&ccu RST_BUS_THS>;
 
-+			nvmem-cells = <&ths_calibration>;
 
-+			nvmem-cell-names = "calibration";
 
-+			allwinner,sram = <&syscon>;
 
-+			#thermal-sensor-cells = <1>;
 
-+		};
 
-+
 
- 		usbotg: usb@5100000 {
 
- 			compatible = "allwinner,sun50i-h616-musb",
 
- 				     "allwinner,sun8i-h3-musb";
 
-@@ -755,4 +773,74 @@
 
- 			#size-cells = <0>;
 
- 		};
 
- 	};
 
-+
 
-+	thermal-zones {
 
-+		cpu-thermal {
 
-+			polling-delay-passive = <500>;
 
-+			polling-delay = <1000>;
 
-+			thermal-sensors = <&ths 2>;
 
-+			sustainable-power = <1000>;
 
-+
 
-+			trips {
 
-+				cpu_threshold: cpu-trip-0 {
 
-+					temperature = <60000>;
 
-+					type = "passive";
 
-+					hysteresis = <0>;
 
-+				};
 
-+				cpu_target: cpu-trip-1 {
 
-+					temperature = <70000>;
 
-+					type = "passive";
 
-+					hysteresis = <0>;
 
-+				};
 
-+				cpu_critical: cpu-trip-2 {
 
-+					temperature = <110000>;
 
-+					type = "critical";
 
-+					hysteresis = <0>;
 
-+				};
 
-+			};
 
-+		};
 
-+
 
-+		gpu-thermal {
 
-+			polling-delay-passive = <500>;
 
-+			polling-delay = <1000>;
 
-+			thermal-sensors = <&ths 0>;
 
-+			sustainable-power = <1100>;
 
-+
 
-+			trips {
 
-+				gpu_temp_critical: gpu-trip-0 {
 
-+					temperature = <110000>;
 
-+					type = "critical";
 
-+					hysteresis = <0>;
 
-+				};
 
-+			};
 
-+		};
 
-+
 
-+		ve-thermal {
 
-+			polling-delay-passive = <0>;
 
-+			polling-delay = <0>;
 
-+			thermal-sensors = <&ths 1>;
 
-+
 
-+			trips {
 
-+				ve_temp_critical: ve-trip-0 {
 
-+					temperature = <110000>;
 
-+					type = "critical";
 
-+					hysteresis = <0>;
 
-+				};
 
-+			};
 
-+		};
 
-+
 
-+		ddr-thermal {
 
-+			polling-delay-passive = <0>;
 
-+			polling-delay = <0>;
 
-+			thermal-sensors = <&ths 3>;
 
-+
 
-+			trips {
 
-+				ddr_temp_critical: ddr-trip-0 {
 
-+					temperature = <110000>;
 
-+					type = "critical";
 
-+					hysteresis = <0>;
 
-+				};
 
-+			};
 
-+		};
 
-+	};
 
- };

+ 0 - 30
target/linux/sunxi/patches-6.1/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch
View File 

@@ -1,30 +0,0 @@
 
-From a896bc1d79e3c00f0aacfe225499d811775616f3 Mon Sep 17 00:00:00 2001
 
-From: Chukun Pan <[email protected]>
 
-Date: Sun, 10 Oct 2021 21:50:17 +0800
 
-Subject: [PATCH] arm64: allwinner: add OF node for USB eth on NanoPi R1S H5
 
-
 
-This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
 
-NanoPi R1S H5. Add the correct value for the RTL8153 LED configuration
 
-register to match the blink behavior of the other port on the device.
 
-
 
-Signed-off-by: Chukun Pan <[email protected]>
 
----
 
- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 +++++++
 
- 1 file changed, 7 insertions(+)
 
-
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
 
-@@ -116,6 +116,13 @@
 
- 
- &ehci1 {
 
- 	status = "okay";
 
-+
 
-+	usb-eth@1 {
 
-+		compatible = "realtek,rtl8153";
 
-+		reg = <1>;
 
-+
 
-+		realtek,led-data = <0x78>;
 
-+	};
 
- };
 
- 
- &ehci2 {

+ 0 - 20
target/linux/sunxi/patches-6.1/301-orangepi_pc2_usb_otg_to_host_key_power.patch
View File 

@@ -1,20 +0,0 @@
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
 
-@@ -59,7 +59,7 @@
 
- 
- 		key-sw4 {
 
- 			label = "sw4";
 
--			linux,code = <BTN_0>;
 
-+			linux,code = <KEY_POWER>;
 
- 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
 
- 			wakeup-source;
 
- 		};
 
-@@ -220,7 +220,7 @@
 
- };
 
- 
- &usb_otg {
 
--	dr_mode = "otg";
 
-+	dr_mode = "host";
 
- 	status = "okay";
 
- };
 
-

+ 0 - 46
target/linux/sunxi/patches-6.1/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch
View File 

@@ -1,46 +0,0 @@
 
-From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001
 
-From: Oskari Lemmela <[email protected]>
 
-Date: Mon, 31 Dec 2018 07:44:49 +0200
 
-Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions.
 
-
 
-First 896kB to u-boot. Enough space for SPL, u-boot and ATF.
 
-Next 128kB to u-boot environment and rest to firmware.
 
-
 
-Firmware partition is compatible FIT image dynamic splitting.
 
-
 
-Signed-off-by: Oskari Lemmela <[email protected]>
 
----
 
- .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++
 
- 1 file changed, 22 insertions(+)
 
-
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
 
-@@ -58,6 +58,28 @@
 
- 		compatible = "jedec,spi-nor";
 
- 		reg = <0>;
 
- 		spi-max-frequency = <40000000>;
 
-+
 
-+		partitions {
 
-+			compatible = "fixed-partitions";
 
-+			#address-cells = <1>;
 
-+			#size-cells = <1>;
 
-+
 
-+			partition@0 {
 
-+				label = "u-boot";
 
-+				reg = <0x000000 0x0E0000>;
 
-+			};
 
-+
 
-+			partition@e0000 {
 
-+				label = "u-boot-env";
 
-+				reg = <0x0E0000 0x020000>;
 
-+			};
 
-+
 
-+			partition@100000 {
 
-+				compatible = "denx,fit";
 
-+				label = "firmware";
 
-+				reg = <0x100000 0xF00000>;
 
-+			};
 
-+		};
 
- 	};
 
- };
 
-

+ 0 - 292
target/linux/sunxi/patches-6.1/410-sunxi-add-bananapi-p2-zero.patch
View File 

@@ -1,292 +0,0 @@
 
---- a/arch/arm/boot/dts/Makefile
 
-+++ b/arch/arm/boot/dts/Makefile
 
-@@ -1352,6 +1352,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 
- 	sun8i-a83t-cubietruck-plus.dtb \
 
- 	sun8i-a83t-tbs-a711.dtb \
 
- 	sun8i-h2-plus-bananapi-m2-zero.dtb \
 
-+	sun8i-h2-plus-bananapi-p2-zero.dtb \
 
- 	sun8i-h2-plus-libretech-all-h3-cc.dtb \
 
- 	sun8i-h2-plus-orangepi-r1.dtb \
 
- 	sun8i-h2-plus-orangepi-zero.dtb \
 
---- /dev/null
 
-+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-p2-zero.dts
 
-@@ -0,0 +1,279 @@
 
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 
-+/*
 
-+ * Copyright (C) 2023 Zoltan HERPAI <[email protected]>
 
-+ *
 
-+ * Based on sun8i-h2-plus-bananapi-m2-zero.dts, which is:
 
-+ *   Copyright (C) 2017 Icenowy Zheng <[email protected]>
 
-+ */
 
-+
 
-+/dts-v1/;
 
-+#include "sun8i-h3.dtsi"
 
-+#include "sunxi-common-regulators.dtsi"
 
-+
 
-+#include <dt-bindings/gpio/gpio.h>
 
-+#include <dt-bindings/input/input.h>
 
-+
 
-+/ {
 
-+	model = "Banana Pi BPI-P2-Zero";
 
-+	compatible = "sinovoip,bpi-p2-zero", "allwinner,sun8i-h2-plus";
 
-+
 
-+	aliases {
 
-+		serial0 = &uart0;
 
-+		serial1 = &uart1;
 
-+	};
 
-+
 
-+	chosen {
 
-+		stdout-path = "serial0:115200n8";
 
-+	};
 
-+
 
-+	connector {
 
-+		compatible = "hdmi-connector";
 
-+		type = "c";
 
-+
 
-+		port {
 
-+			hdmi_con_in: endpoint {
 
-+				remote-endpoint = <&hdmi_out_con>;
 
-+			};
 
-+		};
 
-+	};
 
-+
 
-+	leds {
 
-+		compatible = "gpio-leds";
 
-+
 
-+		pwr_led {
 
-+			label = "bananapi-p2-zero:red:pwr";
 
-+			gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
 
-+			default-state = "on";
 
-+		};
 
-+	};
 
-+
 
-+	gpio_keys {
 
-+		compatible = "gpio-keys";
 
-+
 
-+		sw4 {
 
-+			label = "power";
 
-+			linux,code = <BTN_0>;
 
-+			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
 
-+		};
 
-+	};
 
-+
 
-+	reg_vdd_cpux: vdd-cpux-regulator {
 
-+		compatible = "regulator-gpio";
 
-+		regulator-name = "vdd-cpux";
 
-+		regulator-type = "voltage";
 
-+		regulator-boot-on;
 
-+		regulator-always-on;
 
-+		regulator-min-microvolt = <1100000>;
 
-+		regulator-max-microvolt = <1300000>;
 
-+		regulator-ramp-delay = <50>; /* 4ms */
 
-+
 
-+		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
 
-+		enable-active-high;
 
-+		gpios-states = <0x1>;
 
-+		states = <1100000 0>, <1300000 1>;
 
-+	};
 
-+
 
-+	reg_vcc_dram: vcc-dram {
 
-+		compatible = "regulator-fixed";
 
-+		regulator-name = "vcc-dram";
 
-+		regulator-min-microvolt = <1500000>;
 
-+		regulator-max-microvolt = <1500000>;
 
-+		regulator-always-on;
 
-+		regulator-boot-on;
 
-+		enable-active-high;
 
-+		gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
 
-+		vin-supply = <&reg_vcc5v0>;
 
-+	};
 
-+
 
-+	reg_vcc1v2: vcc1v2 {
 
-+		compatible = "regulator-fixed";
 
-+		regulator-name = "vcc1v2";
 
-+		regulator-min-microvolt = <1200000>;
 
-+		regulator-max-microvolt = <1200000>;
 
-+		regulator-always-on;
 
-+		regulator-boot-on;
 
-+		enable-active-high;
 
-+		gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
 
-+		vin-supply = <&reg_vcc5v0>;
 
-+	};
 
-+
 
-+	poweroff {
 
-+		compatible = "regulator-poweroff";
 
-+		cpu-supply = <&reg_vcc1v2>;
 
-+	};
 
-+
 
-+	wifi_pwrseq: wifi_pwrseq {
 
-+		compatible = "mmc-pwrseq-simple";
 
-+		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
 
-+		clocks = <&rtc 1>;
 
-+		clock-names = "ext_clock";
 
-+	};
 
-+};
 
-+
 
-+&cpu0 {
 
-+	cpu-supply = <&reg_vdd_cpux>;
 
-+};
 
-+
 
-+&de {
 
-+	status = "okay";
 
-+};
 
-+
 
-+&ehci0 {
 
-+	status = "okay";
 
-+};
 
-+
 
-+&emac {
 
-+	phy-handle = <&int_mii_phy>;
 
-+	phy-mode = "mii";
 
-+	allwinner,leds-active-low;
 
-+	status = "okay";
 
-+};
 
-+
 
-+&hdmi {
 
-+	status = "okay";
 
-+};
 
-+
 
-+&hdmi_out {
 
-+	hdmi_out_con: endpoint {
 
-+		remote-endpoint = <&hdmi_con_in>;
 
-+	};
 
-+};
 
-+
 
-+&mmc0 {
 
-+	vmmc-supply = <&reg_vcc3v3>;
 
-+	bus-width = <4>;
 
-+	/*
 
-+	 * On the production batch of this board the card detect GPIO is
 
-+	 * high active (card inserted), although on the early samples it's
 
-+	 * low active.
 
-+	 */
 
-+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
 
-+	status = "okay";
 
-+};
 
-+
 
-+&mmc1 {
 
-+	vmmc-supply = <&reg_vcc3v3>;
 
-+	vqmmc-supply = <&reg_vcc3v3>;
 
-+	mmc-pwrseq = <&wifi_pwrseq>;
 
-+	bus-width = <4>;
 
-+	non-removable;
 
-+	status = "okay";
 
-+
 
-+	brcmf: wifi@1 {
 
-+		reg = <1>;
 
-+		compatible = "brcm,bcm4329-fmac";
 
-+		interrupt-parent = <&pio>;
 
-+		interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
 
-+		interrupt-names = "host-wake";
 
-+	};
 
-+};
 
-+
 
-+&ohci0 {
 
-+	status = "okay";
 
-+};
 
-+
 
-+&uart0 {
 
-+	pinctrl-names = "default";
 
-+	pinctrl-0 = <&uart0_pa_pins>;
 
-+	status = "okay";
 
-+};
 
-+
 
-+&uart1 {
 
-+	pinctrl-names = "default";
 
-+	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
 
-+	uart-has-rtscts;
 
-+	status = "okay";
 
-+
 
-+	bluetooth {
 
-+		compatible = "brcm,bcm43438-bt";
 
-+		max-speed = <1500000>;
 
-+		clocks = <&rtc 1>;
 
-+		clock-names = "lpo";
 
-+		vbat-supply = <&reg_vcc3v3>;
 
-+		vddio-supply = <&reg_vcc3v3>;
 
-+		device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
 
-+		host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
 
-+		shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
 
-+	};
 
-+
 
-+};
 
-+
 
-+&pio {
 
-+	gpio-line-names =
 
-+		/* PA */
 
-+		"CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15",
 
-+			"CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29",
 
-+		"CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05",
 
-+			"CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16",
 
-+		"CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27",
 
-+			"CON2-P40", "CON2-P38", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+
 
-+		/* PB */
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+
 
-+		/* PC */
 
-+		"CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24",
 
-+			"CON2-P18", "", "", "CON2-P26",
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+
 
-+		/* PD */
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "CSI-PWR-EN", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+
 
-+		/* PE */
 
-+		"CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07",
 
-+			"CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20",
 
-+		"CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12",
 
-+			"CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08",
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+
 
-+		/* PF */
 
-+		"SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
 
-+			"SDC0-D2", "SDC0-DET", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+
 
-+		/* PG */
 
-+		"WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
 
-+			"WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX",
 
-+		"BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP",
 
-+			"BT-RST-N", "AP-WAKE-BT", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "";
 
-+};
 
-+
 
-+&r_pio {
 
-+	gpio-line-names =
 
-+		/* PL */
 
-+		"", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36",
 
-+			"VCC-IO-EN", "USB0-ID", "WL-PWR-EN",
 
-+		"PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "",
 
-+		"", "", "", "", "", "", "", "";
 
-+};
 
-+
 
-+&usb_otg {
 
-+	dr_mode = "otg";
 
-+	status = "okay";
 
-+};
 
-+
 
-+&usbphy {
 
-+	usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
 
-+	/*
 
-+	 * There're two micro-USB connectors, one is power-only and another is
 
-+	 * OTG. The Vbus of these two connectors are connected together, so
 
-+	 * the external USB device will be powered just by the power input
 
-+	 * from the power-only USB port.
 
-+	 */
 
-+	status = "okay";
 
-+};

+ 0 - 32
target/linux/sunxi/patches-6.1/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch
View File 

@@ -1,32 +0,0 @@
 
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
 
-From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <[email protected]>
 
-Date: Thu, 26 Mar 2020 10:09:19 +0100
 
-Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases
 
-MIME-Version: 1.0
 
-Content-Type: text/plain; charset=UTF-8
 
-Content-Transfer-Encoding: 8bit
 
-
 
-Signed-off-by: Petr Štetiar <[email protected]>
 
-
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
 
-@@ -15,6 +15,10 @@
 
- 	aliases {
 
- 		ethernet0 = &emac;
 
- 		serial0 = &uart0;
 
-+		led-boot = &led_user;
 
-+		led-failsafe = &led_user;
 
-+		led-running = &led_user;
 
-+		led-upgrade = &led_user;
 
- 	};
 
- 
- 	chosen {
 
-@@ -35,7 +39,7 @@
 
- 	leds {
 
- 		compatible = "gpio-leds";
 
- 
--		led-0 {
 
-+		led_user: led-0 {
 
- 			label = "a64-olinuxino:red:user";
 
- 			gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
 
- 		};

+ 0 - 35
target/linux/sunxi/patches-6.1/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch
View File 

@@ -1,35 +0,0 @@
 
-From 1845163a052efac124f00656eb72f38947630a42 Mon Sep 17 00:00:00 2001
 
-From: Chukun Pan <[email protected]>
 
-Date: Sun, 10 Oct 2021 21:50:18 +0800
 
-Subject: [PATCH] arm64: dts: allwinner: NanoPi R1S H5: add status LED aliases
 
-
 
-Use the SYS LED on the casing for showing system status.
 
-
 
-Signed-off-by: Chukun Pan <[email protected]>
 
----
 
- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 ++++++-
 
- 1 file changed, 6 insertions(+), 1 deletion(-)
 
-
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
 
-@@ -23,6 +23,11 @@
 
- 		ethernet0 = &emac;
 
- 		ethernet1 = &rtl8189etv;
 
- 		serial0 = &uart0;
 
-+
 
-+		led-boot = &led_sys;
 
-+		led-failsafe = &led_sys;
 
-+		led-running = &led_sys;
 
-+		led-upgrade = &led_sys;
 
- 	};
 
- 
- 	chosen {
 
-@@ -38,7 +43,7 @@
 
- 			gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
 
- 		};
 
- 
--		led-1 {
 
-+		led_sys: led-1 {
 
- 			function = LED_FUNCTION_STATUS;
 
- 			color = <LED_COLOR_ID_RED>;
 
- 			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;

+ 0 - 10
target/linux/sunxi/patches-6.1/442-arm64-dts-orangepi-one-plus-enable-PWM.patch
View File 

@@ -1,10 +0,0 @@
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
 
-@@ -41,3 +41,7 @@
 
- 		reg = <1>;
 
- 	};
 
- };
 
-+
 
-+&pwm {
 
-+	status = "okay";
 
-+};

+ 0 - 72
target/linux/sunxi/patches-6.1/450-arm64-dts-enable-wifi-on-pine64-boards.patch
View File 

@@ -1,72 +0,0 @@
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
 
-@@ -42,6 +42,11 @@
 
- 		regulator-min-microvolt = <1800000>;
 
- 		regulator-max-microvolt = <1800000>;
 
- 	};
 
-+
 
-+	wifi_pwrseq: wifi_pwrseq {
 
-+		compatible = "mmc-pwrseq-simple";
 
-+		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
 
-+	};
 
- };
 
- 
- &ac_power_supply {
 
-@@ -102,6 +107,21 @@
 
- 		reg = <1>;
 
- 	};
 
- };
 
-+
 
-+&mmc1 {
 
-+	pinctrl-names = "default";
 
-+	pinctrl-0 = <&mmc1_pins>;
 
-+	vmmc-supply = <&reg_dldo4>;
 
-+	vqmmc-supply = <&reg_eldo1>;
 
-+	mmc-pwrseq = <&wifi_pwrseq>;
 
-+	bus-width = <4>;
 
-+	non-removable;
 
-+	status = "okay";
 
-+
 
-+	rtl8723cs: wifi@1 {
 
-+		reg = <1>;
 
-+	};
 
-+};
 
- 
- &mmc2 {
 
- 	pinctrl-names = "default";
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
 
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
 
-@@ -35,6 +35,11 @@
 
- 			};
 
- 		};
 
- 	};
 
-+
 
-+	wifi_pwrseq: wifi_pwrseq {
 
-+		compatible = "mmc-pwrseq-simple";
 
-+		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
 
-+	};
 
- };
 
- 
- &codec {
 
-@@ -124,6 +129,21 @@
 
- 	status = "okay";
 
- };
 
- 
-+&mmc1 {
 
-+	pinctrl-names = "default";
 
-+	pinctrl-0 = <&mmc1_pins>;
 
-+	vmmc-supply = <&reg_dldo4>;
 
-+	vqmmc-supply = <&reg_eldo1>;
 
-+	mmc-pwrseq = <&wifi_pwrseq>;
 
-+	bus-width = <4>;
 
-+	non-removable;
 
-+	status = "okay";
 
-+
 
-+	rtl8723cs: wifi@1 {
 
-+		reg = <1>;
 
-+	};
 
-+};
 
-+
 
- &ohci0 {
 
- 	status = "okay";
 
- };