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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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+ * Copyright (C) 2006 FON Technology, SL.
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+ * Copyright (C) 2006 Imre Kaloz <[email protected]>
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+ * Copyright (C) 2007 Othello <[email protected]>
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+ */
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+
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+/*
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+ * Support for AR531X GPIO -- General Purpose Input/Output Pins
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+ */
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+
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+#include <linux/autoconf.h>
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+#include <linux/init.h>
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+#include <linux/interrupt.h>
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+#include <linux/types.h>
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+#include <linux/module.h>
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+#include <linux/delay.h>
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+#include <linux/platform_device.h>
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+#include <linux/irq.h>
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+
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+#include <asm/addrspace.h>
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+#include <asm/io.h>
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+#include <asm/irq_cpu.h>
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+#include <asm/gpio.h>
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+#include "ar531x.h"
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+/*
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+ GPIO Interrupt Support
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+ Make use of request_irq() and the function gpio_to_irq() to trap gpio events
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+ */
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+
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+/* Global variables */
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+static u32 ar531x_gpio_intr_Mask = 0;
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+/*
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+ AR5312: I don't have any devices with this chip. Assumed to be similar to AR5215
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+ will someone who has one try the code and remove this message if it works?
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+ */
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+
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+#ifdef CONFIG_ATHEROS_AR5315
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+/*
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+ AR5315: Up to 2 GPIO pins may be monitored simultaneously
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+ specifying more pins if you already have 2 will not have any effect
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+ however, the excess gpio irqs will also be triggered if a valid gpio being monitored triggers
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+ only high, low or edge triggered interrupt supported
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+ */
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+static unsigned int ar5315_gpio_set_type_gpio = 0;
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+static unsigned int ar5315_gpio_set_type_lvl = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
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+#endif
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+
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+#ifdef CONFIG_ATHEROS_AR5312
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+/* Enable the specified AR5312_GPIO_IRQ interrupt */
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+static void ar5312_gpio_intr_enable(unsigned int irq) {
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+ u32 reg;
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+ unsigned int gpio;
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+ unsigned int imr;
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+
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+ gpio = irq - (AR531X_GPIO_IRQ(0));
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+ if (gpio >= AR531X_NUM_GPIO)
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+ return;
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+ ar531x_gpio_intr_Mask |= (1<<gpio);
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+
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+ reg = sysRegRead(AR531X_GPIO_CR);
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+ reg &= ~(AR531X_GPIO_CR_M(gpio) | AR531X_GPIO_CR_UART(gpio) | AR531X_GPIO_CR_INT(gpio));
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+ reg |= AR531X_GPIO_CR_I(gpio);
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+ reg |= AR531X_GPIO_CR_INT(gpio);
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+
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+ sysRegWrite(AR531X_GPIO_CR, reg);
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+ (void)sysRegRead(AR531X_GPIO_CR); /* flush to hardware */
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+
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+ imr = sysRegRead(AR531X_IMR);
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+ imr |= AR531X_ISR_GPIO;
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+ sysRegWrite(AR531X_IMR, imr);
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+ imr = sysRegRead(AR531X_IMR); /* flush write buffer */
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+}
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+
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+/* Disable the specified AR5312_GPIO_IRQ interrupt */
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+static void ar5312_gpio_intr_disable(unsigned int irq) {
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+ u32 reg;
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+ unsigned int gpio;
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+ gpio = irq - (AR531X_GPIO_IRQ(0));
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+ if (gpio >= AR531X_NUM_GPIO)
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+ return;
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+
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+ reg = sysRegRead(AR531X_GPIO_CR);
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+ reg &= ~(AR531X_GPIO_CR_M(gpio) | AR531X_GPIO_CR_UART(gpio) | AR531X_GPIO_CR_INT(gpio));
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+ reg |= AR531X_GPIO_CR_I(gpio);
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+ /* No GPIO_CR_INT bit */
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+
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+ sysRegWrite(AR531X_GPIO_CR, reg);
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+ (void)sysRegRead(AR531X_GPIO_CR); /* flush to hardware */
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+
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+ /* Disable Interrupt if no gpio needs triggering */
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+ if (ar531x_gpio_intr_Mask != 0) {
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+ unsigned int imr;
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+
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+ imr = sysRegRead(AR531X_IMR);
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+ imr &= ~AR531X_ISR_GPIO;
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+ sysRegWrite(AR531X_IMR, imr);
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+ imr = sysRegRead(AR531X_IMR); /* flush write buffer */
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+ }
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+
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+ ar531x_gpio_intr_Mask &= ~(1<<gpio);
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+}
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+
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+/* Turn on the specified AR5312_GPIO_IRQ interrupt */
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+static unsigned int ar5312_gpio_intr_startup(unsigned int irq) {
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+ ar5312_gpio_intr_enable(irq);
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+ return 0;
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+}
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+
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+static void ar5312_gpio_intr_end(unsigned int irq) {
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+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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+ ar5312_gpio_intr_enable(irq);
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+}
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+
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+asmlinkage void ar5312_gpio_irq_dispatch(void) {
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+ int i;
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+ u32 gpioIntPending;
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+ gpioIntPending = sysRegRead(AR531X_GPIO_DI) & ar531x_gpio_intr_Mask;
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+ sysRegWrite(AR531X_ISR, sysRegRead(AR531X_IMR) | ~AR531X_ISR_GPIO);
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+ for (i=0; i<AR531X_GPIO_IRQ_COUNT; i++) {
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+ if (gpioIntPending & (1 << i))
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+ do_IRQ(AR531X_GPIO_IRQ(i));
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+ }
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+}
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+#endif /* #ifdef CONFIG_ATHEROS_AR5312 */
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+
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+#ifdef CONFIG_ATHEROS_AR5315
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+/* Enable the specified AR5315_GPIO_IRQ interrupt */
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+static void ar5315_gpio_intr_enable(unsigned int irq) {
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+ u32 reg;
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+ unsigned int gpio;
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+ unsigned int imr;
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+ unsigned int i;
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+
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+ gpio = irq - (AR531X_GPIO_IRQ(0));
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+ if (gpio >= AR5315_NUM_GPIO)
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+ return;
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+ ar531x_gpio_intr_Mask |= (1<<gpio);
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+
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+ reg = sysRegRead(AR5315_GPIO_CR);
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+ reg &= ~(AR5315_GPIO_CR_M(gpio));
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+ reg |= AR5315_GPIO_CR_I(gpio);
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+ sysRegWrite(AR5315_GPIO_CR, reg);
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+ (void)sysRegRead(AR5315_GPIO_CR); /* flush write to hardware */
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+
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+ /* Locate a free register slot to enable gpio intr
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+ will fail silently if no more slots are available
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+ */
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+ reg = sysRegRead(AR5315_GPIO_INT);
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+ for (i=0 ; i<=AR5315_GPIO_INT_MAX_Y ; i++) {
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+ /* Free slot means trigger level = 0 */
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+ if ( AR5315_GPIO_INT_LVL_OFF ==
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+ (reg & AR5315_GPIO_INT_LVL_M) ) {
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+
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+ unsigned int def_lvl = AR5315_GPIO_INT_LVL_EDGE;
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+ if (ar5315_gpio_set_type_gpio == gpio)
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+ def_lvl = ar5315_gpio_set_type_lvl;
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+
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+ /* Set the gpio level trigger mode */
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+/* reg &= ~(AR5315_GPIO_INT_LVL_M(i)); */
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+ reg |= AR5315_GPIO_INT_LVL(i);
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+
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+ /* Enable the gpio pin */
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+ reg &= ~(AR5315_GPIO_INT_M);
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+ reg |= AR5315_GPIO_INT_S(i);
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+
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+ sysRegWrite(AR5315_GPIO_INT, reg);
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+ (void)sysRegRead(AR5315_GPIO_INT); /* flush write to hardware */
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+
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+ /* break out of for loop */
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+ break;
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+ } /* end if trigger level for slot i is 0 */
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+ } /* end for each slot */
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+
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+ imr = sysRegRead(AR5315_IMR);
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+ imr |= AR5315_ISR_GPIO;
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+ sysRegWrite(AR5315_IMR, imr);
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+ imr = sysRegRead(AR5315_IMR); /* flush write buffer */
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+}
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+
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+
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+/* Disable the specified AR5315_GPIO_IRQ interrupt */
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+static void ar5315_gpio_intr_disable(unsigned int irq) {
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+ u32 reg;
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+ unsigned int gpio;
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+ unsigned int i;
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+
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+ gpio = irq - (AR531X_GPIO_IRQ(0));
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+ if (gpio >= AR5315_NUM_GPIO)
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+ return;
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+
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+ reg = sysRegRead(AR5315_GPIO_CR);
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+ reg &= ~(AR5315_GPIO_CR_M(gpio));
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+ reg |= AR5315_GPIO_CR_I(gpio);
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+ sysRegWrite(AR5315_GPIO_CR, reg);
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+ (void)sysRegRead(AR5315_GPIO_CR); /* flush write to hardware */
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+
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+ /* Locate a the correct register slot to disable gpio intr */
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+ reg = sysRegRead(AR5315_GPIO_INT);
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+ for (i=0 ; i<=AR5315_GPIO_INT_MAX_Y ; i++) {
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+ /* If this correct */
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+ if ( AR5315_GPIO_INT_S(i) ==
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+ (reg & AR5315_GPIO_INT_M) ) {
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+ /* Clear the gpio level trigger mode */
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+ reg &= ~(AR5315_GPIO_INT_LVL_M);
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+
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+ sysRegWrite(AR5315_GPIO_INT, reg);
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+ (void)sysRegRead(AR5315_GPIO_INT); /* flush write to hardware */
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+ break;
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+ } /* end if trigger level for slot i is 0 */
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+ } /* end for each slot */
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+
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+ /* Disable interrupt only if no gpio needs triggering */
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+ if (ar531x_gpio_intr_Mask != 0) {
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+ unsigned int imr;
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+
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+ imr = sysRegRead(AR5315_IMR);
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+ imr &= ~AR5315_ISR_GPIO;
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+ sysRegWrite(AR5315_IMR, imr);
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+ imr = sysRegRead(AR5315_IMR); /* flush write buffer */
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+ }
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+
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+ ar531x_gpio_intr_Mask &= ~(1<<gpio);
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+}
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+
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+/* Turn on the specified AR5315_GPIO_IRQ interrupt */
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+static unsigned int ar5315_gpio_intr_startup(unsigned int irq) {
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+ ar5315_gpio_intr_enable(irq);
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+ return 0;
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+}
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+
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+static void ar5315_gpio_intr_end(unsigned int irq) {
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+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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+ ar5315_gpio_intr_enable(irq);
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+}
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+
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+static int ar5315_gpio_intr_set_type(unsigned int irq, unsigned int flow_type) {
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+ ar5315_gpio_set_type_gpio = irq - (AR531X_GPIO_IRQ(0));
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+ if (ar5315_gpio_set_type_gpio > AR5315_NUM_GPIO)
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+ return -EINVAL;
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+ switch (flow_type & IRQF_TRIGGER_MASK) {
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+ case IRQF_TRIGGER_RISING:
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+ case IRQF_TRIGGER_FALLING:
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+ printk(KERN_WARNING "AR5315 GPIO %u falling back to edge triggered\n", ar5315_gpio_set_type_gpio);
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+ case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
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+ ar5315_gpio_set_type_lvl = AR5315_GPIO_INT_LVL_EDGE;
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+ break;
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+ case IRQF_TRIGGER_LOW:
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+ ar5315_gpio_set_type_lvl = AR5315_GPIO_INT_LVL_LOW;
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+ break;
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+ case IRQF_TRIGGER_HIGH:
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+ ar5315_gpio_set_type_lvl = AR5315_GPIO_INT_LVL_HIGH;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+ return 0;
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+}
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+
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+asmlinkage void ar5315_gpio_irq_dispatch(void){
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+ int i;
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+ u32 gpioIntPending;
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+ gpioIntPending = sysRegRead(AR5315_GPIO_DI) & ar531x_gpio_intr_Mask;
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+ sysRegWrite(AR5315_ISR, sysRegRead(AR5315_IMR) | ~AR5315_ISR_GPIO);
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+ for (i=0; i<AR531X_GPIO_IRQ_COUNT; i++) {
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+ if (gpioIntPending & (1 << i))
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+ do_IRQ(AR531X_GPIO_IRQ(i));
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+ }
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+}
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+#endif /* #ifdef CONFIG_ATHEROS_AR5315 */
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+
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+/* Common Code */
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+static struct irq_chip ar531x_gpio_intr_controller = {
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+ .typename = "AR531X GPIO",
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+};
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+
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+/* ARGSUSED */
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+irqreturn_t
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+spurious_gpio_handler(int cpl, void *dev_id)
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+{
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+ u32 gpioDataIn;
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+ DO_AR5312(gpioDataIn = sysRegRead(AR531X_GPIO_DI);)
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+ DO_AR5315(gpioDataIn = sysRegRead(AR5315_GPIO_DI);)
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+
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+ printk("spurious_gpio_handler: 0x%08x dev=%p DI=0x%08x gpioIntMask=0x%08x\n",
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+ cpl, dev_id, gpioDataIn, ar531x_gpio_intr_Mask);
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+
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+ return IRQ_NONE;
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+}
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+
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+static struct irqaction spurious_gpio = {
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+ .handler = spurious_gpio_handler,
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+ .name = "spurious_gpio",
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+};
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+
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+/* Initialize AR531X GPIO interrupts */
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+static int __init ar531x_gpio_init(void)
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+{
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+ int i;
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+
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+ DO_AR5312( \
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+ ar531x_gpio_intr_controller.startup = ar5312_gpio_intr_startup; \
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+ ar531x_gpio_intr_controller.shutdown = ar5312_gpio_intr_disable; \
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+ ar531x_gpio_intr_controller.enable = ar5312_gpio_intr_enable; \
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+ ar531x_gpio_intr_controller.disable = ar5312_gpio_intr_disable; \
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+ ar531x_gpio_intr_controller.ack = ar5312_gpio_intr_disable; \
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+ ar531x_gpio_intr_controller.end = ar5312_gpio_intr_end; \
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+ )
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+
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+ DO_AR5315( \
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+ ar531x_gpio_intr_controller.startup = ar5315_gpio_intr_startup; \
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+ ar531x_gpio_intr_controller.shutdown = ar5315_gpio_intr_disable; \
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+ ar531x_gpio_intr_controller.enable = ar5315_gpio_intr_enable; \
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+ ar531x_gpio_intr_controller.disable = ar5315_gpio_intr_disable; \
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+ ar531x_gpio_intr_controller.ack = ar5315_gpio_intr_disable; \
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+ ar531x_gpio_intr_controller.end = ar5315_gpio_intr_end; \
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+ ar531x_gpio_intr_controller.set_type = ar5315_gpio_intr_set_type; \
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+ )
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+
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+ for (i = AR531X_GPIO_IRQ_BASE;
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+ i < AR531X_GPIO_IRQ_BASE + AR531X_GPIO_IRQ_COUNT;
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+ i++) {
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+ irq_desc[i].status = IRQ_DISABLED;
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+ irq_desc[i].action = NULL;
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+ irq_desc[i].depth = 1;
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+ irq_desc[i].chip = &ar531x_gpio_intr_controller;
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+ }
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+
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+ setup_irq(AR531X_GPIO_IRQ_NONE, &spurious_gpio);
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+
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+ return 0;
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+}
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+
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+subsys_initcall(ar531x_gpio_init);
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+
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John Crispin