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@@ -79,9 +79,10 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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targets += $(dtb-y)
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--- /dev/null
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+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
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-@@ -0,0 +1,20 @@
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+@@ -0,0 +1,35 @@
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+/*
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+ * Broadcom BCM470X / BCM5301X arm platform code.
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++ * DTS for Netgear R6250 V1
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+ *
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+ * Copyright 2013 Hauke Mehrtens <[email protected]>
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+ *
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@@ -93,37 +94,43 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+#include "bcm4708.dtsi"
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+
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+/ {
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-+ compatible = "netgear,r6250v1", "broadcom,bcm4708";
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++ compatible = "netgear,r6250v1", "brcm,bcm4708";
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+ model = "Netgear R6250 V1 (BCM4708)";
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+
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++ chosen {
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++ bootargs = "console=ttyS0,115200";
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++ };
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++
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+ memory {
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+ reg = <0x00000000 0x08000000>;
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+ };
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++
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++ chipcommonA {
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++ uart0: serial@0300 {
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++ status = "okay";
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++ };
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++
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++ uart1: serial@0400 {
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++ status = "okay";
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++ };
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++ };
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/bcm4708.dtsi
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-@@ -0,0 +1,100 @@
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+@@ -0,0 +1,34 @@
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+/*
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+ * Broadcom BCM470X / BCM5301X ARM platform code.
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++ * DTS for BCM4708 SoC.
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+ *
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-+ * Copyright 2013 Hauke Mehrtens <[email protected]>
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++ * Copyright 2013-2014 Hauke Mehrtens <[email protected]>
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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-+#include <dt-bindings/interrupt-controller/arm-gic.h>
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-+#include <dt-bindings/interrupt-controller/irq.h>
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-+
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-+#include "skeleton.dtsi"
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++#include "bcm5301x.dtsi"
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+
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+/ {
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-+ compatible = "broadcom,bcm4708";
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-+ model = "Broadcom BCM4708";
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-+ interrupt-parent = <&gic>;
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-+
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-+ chosen {
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-+ bootargs = "console=ttyS0,115200 debug earlyprintk";
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-+ };
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++ compatible = "brcm,bcm4708";
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+
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+ cpus {
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+ #address-cells = <1>;
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@@ -133,74 +140,114 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a9";
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+ next-level-cache = <&L2>;
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-+ reg = <0>;
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++ reg = <0x0>;
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+ };
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++
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+ cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a9";
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+ next-level-cache = <&L2>;
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-+ reg = <1>;
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++ reg = <0x1>;
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+ };
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+ };
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+
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-+ clocks {
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++};
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+--- /dev/null
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++++ b/arch/arm/boot/dts/bcm5301x.dtsi
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+@@ -0,0 +1,95 @@
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++/*
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++ * Broadcom BCM470X / BCM5301X ARM platform code.
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++ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
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++ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
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++ *
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++ * Copyright 2013-2014 Hauke Mehrtens <[email protected]>
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++ *
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++ * Licensed under the GNU/GPL. See COPYING for details.
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++ */
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++
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++#include <dt-bindings/interrupt-controller/irq.h>
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++#include <dt-bindings/interrupt-controller/arm-gic.h>
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++#include "skeleton.dtsi"
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++
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++/ {
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++ interrupt-parent = <&gic>;
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++
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++ chipcommonA {
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++ compatible = "simple-bus";
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++ ranges = <0x00000000 0x18000000 0x00001000>;
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+ #address-cells = <1>;
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-+ #size-cells = <0>;
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++ #size-cells = <1>;
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++
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++ uart0: serial@0300 {
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++ compatible = "ns16550";
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++ reg = <0x0300 0x100>;
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++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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++ clock-frequency = <100000000>;
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++ status = "disabled";
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++ };
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+
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-+ clk_periph: periph {
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-+ compatible = "fixed-clock";
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-+ #clock-cells = <0>;
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-+ clock-frequency = <400000000>;
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++ uart1: serial@0400 {
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++ compatible = "ns16550";
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++ reg = <0x0400 0x100>;
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++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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++ clock-frequency = <100000000>;
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++ status = "disabled";
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+ };
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+ };
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+
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-+ uart@18000300 {
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-+ compatible = "ns16550";
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-+ reg = <0x18000300 0x100>;
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-+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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-+ clock-frequency = <100000000>;
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-+ };
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++ mpcore {
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++ compatible = "simple-bus";
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++ ranges = <0x00000000 0x19020000 0x00003000>;
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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+
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-+ uart@18000400 {
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-+ compatible = "ns16550";
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-+ reg = <0x18000400 0x100>;
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-+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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-+ clock-frequency = <100000000>;
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-+ };
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++ scu@0000 {
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++ compatible = "arm,cortex-a9-scu";
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++ reg = <0x0000 0x100>;
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++ };
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+
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-+ gic: interrupt-controller@19021000 {
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-+ compatible = "arm,cortex-a9-gic";
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-+ #interrupt-cells = <3>;
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-+ #address-cells = <0>;
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-+ interrupt-controller;
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-+ reg = <0x19021000 0x1000>,
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-+ <0x19020100 0x100>;
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-+ };
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++ timer@0200 {
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++ compatible = "arm,cortex-a9-global-timer";
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++ reg = <0x0200 0x100>;
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++ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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++ clocks = <&clk_periph>;
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++ };
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+
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-+ timer@19020200 {
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-+ compatible = "arm,cortex-a9-global-timer";
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-+ reg = <0x19020200 0x100>;
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-+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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-+ clocks = <&clk_periph>;
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-+ };
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++ local-timer@0600 {
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++ compatible = "arm,cortex-a9-twd-timer";
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++ reg = <0x0600 0x100>;
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++ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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++ clocks = <&clk_periph>;
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++ };
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+
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-+ local-timer@19020600 {
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-+ compatible = "arm,cortex-a9-twd-timer";
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-+ reg = <0x19020600 0x100>;
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-+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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-+ clocks = <&clk_periph>;
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-+ };
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++ gic: interrupt-controller@1000 {
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++ compatible = "arm,cortex-a9-gic";
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++ #interrupt-cells = <3>;
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++ #address-cells = <0>;
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++ interrupt-controller;
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++ reg = <0x1000 0x1000>,
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++ <0x0100 0x100>;
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++ };
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+
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-+ L2: cache-controller@19022000 {
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-+ compatible = "arm,pl310-cache";
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-+ reg = <0x19022000 0x1000>;
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-+ cache-unified;
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-+ cache-level = <2>;
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++ L2: cache-controller@2000 {
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++ compatible = "arm,pl310-cache";
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++ reg = <0x2000 0x1000>;
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++ cache-unified;
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++ cache-level = <2>;
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++ };
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+ };
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+
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-+ scu@19020000 {
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-+ compatible = "arm,cortex-a9-scu";
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-+ reg = <0x19020000 0x100>;
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++ clocks {
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ /* As long as we do not have a real clock driver us this
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++ * fixed clock */
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++ clk_periph: periph {
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++ compatible = "fixed-clock";
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++ #clock-cells = <0>;
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++ clock-frequency = <400000000>;
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++ };
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+ };
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+};
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--- /dev/null
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@@ -227,7 +274,7 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+#include <asm/hardware/debug-8250.S>
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--- /dev/null
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+++ b/arch/arm/mach-bcm53xx/Kconfig
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-@@ -0,0 +1,26 @@
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+@@ -0,0 +1,25 @@
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+config ARCH_BCM_5301X
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+ bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
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+ depends on MMU
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@@ -238,7 +285,6 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+ select HAVE_SMP
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+ select COMMON_CLK
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+ select GENERIC_CLOCKEVENTS
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-+ select GENERIC_TIME
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+ select ARM_GLOBAL_TIMER
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+ select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
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+ select MIGHT_HAVE_PCI
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@@ -260,7 +306,7 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+obj-y += bcm53xx.o
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--- /dev/null
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+++ b/arch/arm/mach-bcm53xx/bcm53xx.c
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-@@ -0,0 +1,60 @@
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+@@ -0,0 +1,70 @@
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+/*
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+ * Broadcom BCM470X / BCM5301X ARM platform code.
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+ *
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@@ -268,33 +314,43 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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-+#include <linux/of_address.h>
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+#include <linux/of_platform.h>
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+#include <linux/clocksource.h>
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+#include <linux/clk-provider.h>
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+#include <asm/hardware/cache-l2x0.h>
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+
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+#include <asm/mach/arch.h>
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-+#include <asm/mach/map.h>
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++#include <asm/siginfo.h>
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+#include <asm/signal.h>
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+
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++
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++static bool first_fault = true;
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++
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+static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
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+ struct pt_regs *regs)
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+{
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-+ /*
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-+ * These happen for no good reason, possibly left over from CFE
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-+ */
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-+ pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
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++ if (fsr == 0x1c06 && first_fault) {
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++ first_fault = false;
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++
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++ /*
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++ * These faults with code 0x1c06 happens for no good reason,
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++ * possibly left over from the CFE boot loader.
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++ */
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++ pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
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+ addr, fsr);
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+
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-+ /* Returning non-zero causes fault display and panic */
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-+ return 0;
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++ /* Returning non-zero causes fault display and panic */
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++ return 0;
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++ }
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++
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++ /* Others should cause a fault */
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++ return 1;
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+}
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+
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+static void __init bcm5301x_init_early(void)
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+{
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+ /* Install our hook */
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-+ hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, 0,
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++ hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
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+ "imprecise external abort");
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+}
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+
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@@ -311,7 +367,7 @@ Signed-off-by: Hauke Mehrtens <[email protected]>
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+}
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+
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+static const char __initconst *bcm5301x_dt_compat[] = {
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-+ "broadcom,bcm4708",
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++ "brcm,bcm4708",
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+ NULL,
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+};
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+
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