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@@ -0,0 +1,87 @@
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+From 41ec72d74b9453cd0d4b60d188ae894b8bdc4ca6 Mon Sep 17 00:00:00 2001
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+From: Heiner Kallweit <[email protected]>
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+Date: Thu, 20 Nov 2014 18:33:47 +0100
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+Subject: [PATCH] create dts target p1010rdb-pa
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+ With kernel 3.14 dts target p1010rdb was renamed to p1010rdb-pa.
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+ Create a copy of p1010rdb.dts to maintain compatibility.
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+
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+---
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+ arch/powerpc/boot/dts/p1010rdb-pa.dts | 66 +++++++++++++++++++++++++++++++++++
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+ 1 file changed, 66 insertions(+)
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+ create mode 100644 arch/powerpc/boot/dts/p1010rdb-pa.dts
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+
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+diff --git a/arch/powerpc/boot/dts/p1010rdb-pa.dts b/arch/powerpc/boot/dts/p1010rdb-pa.dts
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+new file mode 100644
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+index 0000000..b868d22
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+--- /dev/null
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++++ b/arch/powerpc/boot/dts/p1010rdb-pa.dts
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+@@ -0,0 +1,66 @@
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++/*
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++ * P1010 RDB Device Tree Source
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++ *
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++ * Copyright 2011 Freescale Semiconductor Inc.
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++ *
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++ * This program is free software; you can redistribute it and/or modify it
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++ * under the terms of the GNU General Public License as published by the
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++ * Free Software Foundation; either version 2 of the License, or (at your
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++ * option) any later version.
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++ */
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++
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++/include/ "fsl/p1010si-pre.dtsi"
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++
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++/ {
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++ model = "fsl,P1010RDB";
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++ compatible = "fsl,P1010RDB";
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++
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++ memory {
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++ device_type = "memory";
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++ };
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++
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++ board_ifc: ifc: ifc@ffe1e000 {
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++ /* NOR, NAND Flashes and CPLD on board */
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++ ranges = <0x0 0x0 0x0 0xee000000 0x02000000
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++ 0x1 0x0 0x0 0xff800000 0x00010000
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++ 0x3 0x0 0x0 0xffb00000 0x00000020>;
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++ reg = <0x0 0xffe1e000 0 0x2000>;
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++ };
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++
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++ board_soc: soc: soc@ffe00000 {
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++ ranges = <0x0 0x0 0xffe00000 0x100000>;
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++ };
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++
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++ pci0: pcie@ffe09000 {
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++ reg = <0 0xffe09000 0 0x1000>;
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++ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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++ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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++ pcie@0 {
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++ ranges = <0x2000000 0x0 0xa0000000
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++ 0x2000000 0x0 0xa0000000
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++ 0x0 0x20000000
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++
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++ 0x1000000 0x0 0x0
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++ 0x1000000 0x0 0x0
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++ 0x0 0x100000>;
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++ };
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++ };
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++
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++ pci1: pcie@ffe0a000 {
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++ reg = <0 0xffe0a000 0 0x1000>;
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++ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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++ 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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++ pcie@0 {
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++ ranges = <0x2000000 0x0 0x80000000
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++ 0x2000000 0x0 0x80000000
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++ 0x0 0x20000000
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++
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++ 0x1000000 0x0 0x0
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++ 0x1000000 0x0 0x0
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++ 0x0 0x100000>;
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++ };
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++ };
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++};
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++
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++/include/ "p1010rdb.dtsi"
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++/include/ "fsl/p1010si-post.dtsi"
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+--
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+2.1.3
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+
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