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@@ -0,0 +1,327 @@
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+--- a/drivers/pci/controller/Kconfig
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++++ b/drivers/pci/controller/Kconfig
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+@@ -187,7 +187,7 @@ config PCI_MVEBU
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+
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+ config PCIE_MEDIATEK
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+ tristate "MediaTek PCIe controller"
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+- depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
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++ depends on ARCH_AIROHA || ARCH_MEDIATEK || ECONET || COMPILE_TEST
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+ depends on OF
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+ depends on PCI_MSI
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+ help
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+--- a/arch/mips/econet/Kconfig
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++++ b/arch/mips/econet/Kconfig
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+@@ -28,9 +28,11 @@ choice
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+ bool "EN7528 family"
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+ select COMMON_CLK
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+ select CPU_LITTLE_ENDIAN
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++ select HAVE_PCI
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+ select IRQ_MIPS_CPU
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+ select MIPS_CPU_SCACHE
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+ select MIPS_GIC
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++ select PCI_DRIVERS_GENERIC
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+ select SMP
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+ select SMP_UP
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+ select SYS_SUPPORTS_HIGHMEM
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+--- a/drivers/pci/controller/pcie-mediatek.c
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++++ b/drivers/pci/controller/pcie-mediatek.c
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+@@ -76,6 +76,7 @@
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+
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+ #define PCIE_CONF_VEND_ID 0x100
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+ #define PCIE_CONF_DEVICE_ID 0x102
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++#define PCIE_CONF_REV_CLASS 0x104
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+ #define PCIE_CONF_CLASS_ID 0x106
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+
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+ #define PCIE_INT_MASK 0x420
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+@@ -88,6 +89,11 @@
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+ #define MSI_MASK BIT(23)
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+ #define MTK_MSI_IRQS_NUM 32
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+
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++#define EN7528_HOST_MODE 0x00804201
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++#define EN7528_LINKUP_REG 0x50
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++#define EN7528_RC0_LINKUP BIT(1)
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++#define EN7528_RC1_LINKUP BIT(2)
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++
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+ #define PCIE_AHB_TRANS_BASE0_L 0x438
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+ #define PCIE_AHB_TRANS_BASE0_H 0x43c
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+ #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
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+@@ -748,6 +754,86 @@ static int mtk_pcie_startup_port_v2(stru
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+ return 0;
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+ }
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+
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++static int mtk_pcie_startup_port_en7528(struct mtk_pcie_port *port)
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++{
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++ struct mtk_pcie *pcie = port->pcie;
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++ struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
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++ struct resource *mem = NULL;
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++ struct resource_entry *entry;
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++ u32 val, link_mask;
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++ int err;
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++
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++ entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
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++ if (entry)
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++ mem = entry->res;
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++ if (!mem)
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++ return -EINVAL;
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++
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++ if (!pcie->cfg) {
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++ dev_err(pcie->dev, "EN7528: pciecfg syscon not available\n");
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++ return -EINVAL;
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++ }
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++
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++ /* Assert all reset signals */
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++ writel(0, port->base + PCIE_RST_CTRL);
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++
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++ /*
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++ * Enable PCIe link down reset, if link status changed from link up to
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++ * link down, this will reset MAC control registers and configuration
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++ * space.
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++ */
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++ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
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++
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++ /*
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++ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
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++ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST#
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++ * should be delayed 100ms (TPVPERL) for the power and clock to become
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++ * stable.
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++ */
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++ msleep(100);
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++
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++ /* De-assert PHY, PE, PIPE, MAC and configuration reset */
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++ val = readl(port->base + PCIE_RST_CTRL);
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++ val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
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++ PCIE_MAC_SRSTB | PCIE_CRSTB;
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++ writel(val, port->base + PCIE_RST_CTRL);
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++
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++ writel(PCIE_CLASS_CODE | PCIE_REVISION_ID,
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++ port->base + PCIE_CONF_REV_CLASS);
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++ writel(EN7528_HOST_MODE, port->base);
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++
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++ link_mask = (port->slot == 0) ? EN7528_RC0_LINKUP : EN7528_RC1_LINKUP;
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++
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++ /* 100ms timeout value should be enough for Gen1/2 training */
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++ err = regmap_read_poll_timeout(pcie->cfg, EN7528_LINKUP_REG, val,
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++ !!(val & link_mask), 20,
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++ 100 * USEC_PER_MSEC);
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++ if (err) {
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++ dev_err(pcie->dev, "EN7528: port%d link timeout\n", port->slot);
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++ return -ETIMEDOUT;
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++ }
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++
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++ /* Set INTx mask */
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++ val = readl(port->base + PCIE_INT_MASK);
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++ val &= ~INTX_MASK;
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++ writel(val, port->base + PCIE_INT_MASK);
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++
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++ if (IS_ENABLED(CONFIG_PCI_MSI))
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++ mtk_pcie_enable_msi(port);
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++
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++ /* Set AHB to PCIe translation windows */
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++ val = lower_32_bits(mem->start) |
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++ AHB2PCIE_SIZE(fls(resource_size(mem)));
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++ writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
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++
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++ val = upper_32_bits(mem->start);
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++ writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
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++
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++ writel(WIN_ENABLE, port->base + PCIE_AXI_WINDOW0);
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++
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++ return 0;
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++}
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++
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+ static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
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+ unsigned int devfn, int where)
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+ {
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+@@ -1114,6 +1200,20 @@ static int mtk_pcie_probe(struct platfor
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+ if (err)
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+ goto put_resources;
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+
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++ /* Retrain Gen1 links to reach Gen2 where supported */
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++ if (pcie->soc->startup == mtk_pcie_startup_port_en7528) {
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++ struct pci_bus *bus = host->bus;
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++ struct pci_dev *rc = NULL;
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++
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++ while ((rc = pci_get_class(PCI_CLASS_BRIDGE_PCI << 8, rc))) {
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++ if (rc->bus != bus)
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++ continue;
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++ if (!pcie_retrain_link(rc, true))
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++ dev_info(dev, "port%d link retrained\n",
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++ PCI_SLOT(rc->devfn));
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++ }
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++ }
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++
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+ return 0;
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+
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+ put_resources:
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+@@ -1223,12 +1323,19 @@ static const struct mtk_pcie_soc mtk_pci
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+ .setup_irq = mtk_pcie_setup_irq,
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+ };
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+
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++static const struct mtk_pcie_soc mtk_pcie_soc_en7528 = {
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++ .ops = &mtk_pcie_ops_v2,
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++ .startup = mtk_pcie_startup_port_en7528,
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++ .setup_irq = mtk_pcie_setup_irq,
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++};
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++
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+ static const struct of_device_id mtk_pcie_ids[] = {
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+ { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
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+ { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
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+ { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
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+ { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
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+ { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
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++ { .compatible = "econet,en7528-pcie", .data = &mtk_pcie_soc_en7528 },
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+ {},
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+ };
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+ MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
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+--- a/drivers/phy/Kconfig
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++++ b/drivers/phy/Kconfig
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+@@ -82,6 +82,17 @@ config PHY_AIROHA_PCIE
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+ This driver create the basic PHY instance and provides initialize
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+ callback for PCIe GEN3 port.
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+
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++config PHY_EN7528_PCIE
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++ tristate "EcoNet EN7528 PCIe PHY Driver"
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++ depends on ECONET || COMPILE_TEST
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++ depends on OF
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++ select GENERIC_PHY
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++ select REGMAP_MMIO
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++ help
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++ Say Y here to add support for EcoNet EN7528 PCIe PHY driver.
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++ This driver provides PHY initialization for the two PCIe ports
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++ on EN7528 SoC.
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++
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+ source "drivers/phy/allwinner/Kconfig"
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+ source "drivers/phy/amlogic/Kconfig"
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+ source "drivers/phy/broadcom/Kconfig"
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+--- a/drivers/phy/Makefile
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++++ b/drivers/phy/Makefile
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+@@ -11,6 +11,7 @@ obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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+ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
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+ obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
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+ obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
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++obj-$(CONFIG_PHY_EN7528_PCIE) += phy-en7528-pcie.o
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+ obj-y += allwinner/ \
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+ amlogic/ \
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+ broadcom/ \
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+--- /dev/null
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++++ b/drivers/phy/phy-en7528-pcie.c
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+@@ -0,0 +1,119 @@
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++// SPDX-License-Identifier: GPL-2.0+
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++/*
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++ * Copyright (C) 2026 Ahmed Naseef <[email protected]>
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++ *
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++ * EcoNet EN7528 PCIe PHY Driver
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++ */
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++
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++#include <linux/bitops.h>
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++#include <linux/module.h>
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++#include <linux/of.h>
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++#include <linux/phy/phy.h>
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++#include <linux/platform_device.h>
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++#include <linux/regmap.h>
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++
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++struct en7528_pcie_phy_data {
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++ u32 reg;
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++ u32 mask;
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++ u32 val;
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++ u32 max_reg;
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++};
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++
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++struct en7528_pcie_phy {
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++ struct regmap *regmap;
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++ const struct en7528_pcie_phy_data *data;
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++};
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++
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++/* Port 0 PHY: set LCDDS_CLK_PH_INV for PLL operation */
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++static const struct en7528_pcie_phy_data en7528_phy_port0 = {
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++ .reg = 0x4a0,
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++ .mask = BIT(5),
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++ .val = BIT(5),
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++ .max_reg = 0x4a0,
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++};
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++
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++/* Port 1 PHY: Rx impedance tuning, target R -5 Ohm */
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++static const struct en7528_pcie_phy_data en7528_phy_port1 = {
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++ .reg = 0xb2c,
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++ .mask = GENMASK(13, 12),
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++ .val = BIT(12),
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++ .max_reg = 0xb2c,
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++};
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++
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++static int en7528_pcie_phy_init(struct phy *phy)
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++{
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++ struct en7528_pcie_phy *ephy = phy_get_drvdata(phy);
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++ const struct en7528_pcie_phy_data *data = ephy->data;
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++
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++ return regmap_update_bits(ephy->regmap, data->reg,
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++ data->mask, data->val);
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++}
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++
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++static const struct phy_ops en7528_pcie_phy_ops = {
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++ .init = en7528_pcie_phy_init,
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++ .owner = THIS_MODULE,
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++};
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++
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++static int en7528_pcie_phy_probe(struct platform_device *pdev)
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++{
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++ struct device *dev = &pdev->dev;
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++ const struct en7528_pcie_phy_data *data;
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++ struct regmap_config regmap_config = {
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++ .reg_bits = 32,
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++ .val_bits = 32,
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++ .reg_stride = 4,
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++ };
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++ struct phy_provider *provider;
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++ struct en7528_pcie_phy *ephy;
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++ void __iomem *base;
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++ struct phy *phy;
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++
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++ data = of_device_get_match_data(dev);
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++ if (!data)
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++ return -EINVAL;
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++
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++ ephy = devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL);
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++ if (!ephy)
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++ return -ENOMEM;
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++
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++ ephy->data = data;
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++
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++ base = devm_platform_ioremap_resource(pdev, 0);
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++ if (IS_ERR(base))
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++ return PTR_ERR(base);
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++
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++ regmap_config.max_register = data->max_reg;
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++ ephy->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
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++ if (IS_ERR(ephy->regmap))
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++ return PTR_ERR(ephy->regmap);
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++
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++ phy = devm_phy_create(dev, dev->of_node, &en7528_pcie_phy_ops);
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++ if (IS_ERR(phy))
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++ return PTR_ERR(phy);
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++
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++ phy_set_drvdata(phy, ephy);
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++
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++ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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++
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++ return PTR_ERR_OR_ZERO(provider);
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++}
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++
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++static const struct of_device_id en7528_pcie_phy_ids[] = {
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++ { .compatible = "econet,en7528-pcie-phy0", .data = &en7528_phy_port0 },
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++ { .compatible = "econet,en7528-pcie-phy1", .data = &en7528_phy_port1 },
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++ { /* sentinel */ }
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++};
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++MODULE_DEVICE_TABLE(of, en7528_pcie_phy_ids);
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++
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++static struct platform_driver en7528_pcie_phy_driver = {
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++ .probe = en7528_pcie_phy_probe,
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++ .driver = {
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++ .name = "en7528-pcie-phy",
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++ .of_match_table = en7528_pcie_phy_ids,
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++ },
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++};
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++module_platform_driver(en7528_pcie_phy_driver);
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++
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++MODULE_AUTHOR("Ahmed Naseef <[email protected]>");
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++MODULE_DESCRIPTION("EcoNet EN7528 PCIe PHY driver");
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++MODULE_LICENSE("GPL v2");
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Ahmed Naseef