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@@ -0,0 +1,367 @@
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+From: Arend van Spriel <[email protected]>
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+Date: Wed, 11 Mar 2015 16:11:31 +0100
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+Subject: [PATCH] brcmfmac: extract ram size info from internal memory
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+ registers
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+
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+Instead of hard-coded memory sizes it is possible to obtain that
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+information from the internal memory registers.
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+
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+Reviewed-by: Hante Meuleman <[email protected]>
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+Reviewed-by: Franky (Zhenhui) Lin <[email protected]>
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+Reviewed-by: Pieter-Paul Giesberts <[email protected]>
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+Signed-off-by: Arend van Spriel <[email protected]>
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+Signed-off-by: Kalle Valo <[email protected]>
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+---
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+
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+--- a/drivers/net/wireless/brcm80211/brcmfmac/chip.c
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++++ b/drivers/net/wireless/brcm80211/brcmfmac/chip.c
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+@@ -100,9 +100,6 @@
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+ #define BCM4329_CORE_SOCRAM_BASE 0x18003000
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+ /* ARM Cortex M3 core, ID 0x82a */
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+ #define BCM4329_CORE_ARM_BASE 0x18002000
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+-#define BCM4329_RAMSIZE 0x48000
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+-/* bcm43143 */
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+-#define BCM43143_RAMSIZE 0x70000
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+
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+ #define CORE_SB(base, field) \
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+ (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
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+@@ -150,6 +147,78 @@ struct sbconfig {
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+ u32 sbidhigh; /* identification */
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+ };
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+
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++/* bankidx and bankinfo reg defines corerev >= 8 */
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++#define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
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++#define SOCRAM_BANKINFO_SZMASK 0x0000007f
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++#define SOCRAM_BANKIDX_ROM_MASK 0x00000100
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++
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++#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
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++/* socram bankinfo memtype */
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++#define SOCRAM_MEMTYPE_RAM 0
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++#define SOCRAM_MEMTYPE_R0M 1
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++#define SOCRAM_MEMTYPE_DEVRAM 2
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++
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++#define SOCRAM_BANKINFO_SZBASE 8192
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++#define SRCI_LSS_MASK 0x00f00000
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++#define SRCI_LSS_SHIFT 20
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++#define SRCI_SRNB_MASK 0xf0
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++#define SRCI_SRNB_SHIFT 4
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++#define SRCI_SRBSZ_MASK 0xf
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++#define SRCI_SRBSZ_SHIFT 0
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++#define SR_BSZ_BASE 14
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++
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++struct sbsocramregs {
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++ u32 coreinfo;
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++ u32 bwalloc;
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++ u32 extracoreinfo;
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++ u32 biststat;
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++ u32 bankidx;
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++ u32 standbyctrl;
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++
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++ u32 errlogstatus; /* rev 6 */
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++ u32 errlogaddr; /* rev 6 */
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++ /* used for patching rev 3 & 5 */
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++ u32 cambankidx;
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++ u32 cambankstandbyctrl;
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++ u32 cambankpatchctrl;
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++ u32 cambankpatchtblbaseaddr;
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++ u32 cambankcmdreg;
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++ u32 cambankdatareg;
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++ u32 cambankmaskreg;
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++ u32 PAD[1];
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++ u32 bankinfo; /* corev 8 */
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++ u32 bankpda;
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++ u32 PAD[14];
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++ u32 extmemconfig;
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++ u32 extmemparitycsr;
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++ u32 extmemparityerrdata;
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++ u32 extmemparityerrcnt;
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++ u32 extmemwrctrlandsize;
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++ u32 PAD[84];
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++ u32 workaround;
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++ u32 pwrctl; /* corerev >= 2 */
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++ u32 PAD[133];
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++ u32 sr_control; /* corerev >= 15 */
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++ u32 sr_status; /* corerev >= 15 */
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++ u32 sr_address; /* corerev >= 15 */
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++ u32 sr_data; /* corerev >= 15 */
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++};
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++
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++#define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
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++
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++#define ARMCR4_CAP (0x04)
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++#define ARMCR4_BANKIDX (0x40)
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++#define ARMCR4_BANKINFO (0x44)
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++#define ARMCR4_BANKPDA (0x4C)
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++
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++#define ARMCR4_TCBBNB_MASK 0xf0
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++#define ARMCR4_TCBBNB_SHIFT 4
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++#define ARMCR4_TCBANB_MASK 0xf
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++#define ARMCR4_TCBANB_SHIFT 0
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++
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++#define ARMCR4_BSZ_MASK 0x3f
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++#define ARMCR4_BSZ_MULT 8192
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++
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+ struct brcmf_core_priv {
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+ struct brcmf_core pub;
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+ u32 wrapbase;
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+@@ -443,10 +512,6 @@ static int brcmf_chip_cores_check(struct
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+ break;
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+ case BCMA_CORE_ARM_CR4:
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+ cpu_found = true;
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+- if (ci->pub.rambase == 0) {
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+- brcmf_err("RAM base not provided with ARM CR4 core\n");
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+- return -ENOMEM;
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+- }
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+ break;
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+ default:
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+ break;
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+@@ -462,60 +527,160 @@ static int brcmf_chip_cores_check(struct
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+ brcmf_err("RAM core not provided with ARM CM3 core\n");
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+ return -ENODEV;
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+ }
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+- if (!ci->pub.ramsize) {
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+- brcmf_err("RAM size is undetermined\n");
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+- return -ENOMEM;
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+- }
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+ return 0;
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+ }
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+
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+-static void brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
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++static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg)
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+ {
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+- switch (ci->pub.chip) {
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+- case BRCM_CC_4329_CHIP_ID:
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+- ci->pub.ramsize = BCM4329_RAMSIZE;
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+- break;
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+- case BRCM_CC_43143_CHIP_ID:
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+- ci->pub.ramsize = BCM43143_RAMSIZE;
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+- break;
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+- case BRCM_CC_43241_CHIP_ID:
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+- ci->pub.ramsize = 0x90000;
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+- break;
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+- case BRCM_CC_4330_CHIP_ID:
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+- ci->pub.ramsize = 0x48000;
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+- break;
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++ return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
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++}
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++
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++static void brcmf_chip_core_write32(struct brcmf_core_priv *core,
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++ u16 reg, u32 val)
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++{
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++ core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
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++}
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++
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++static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx,
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++ u32 *banksize)
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++{
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++ u32 bankinfo;
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++ u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
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++
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++ bankidx |= idx;
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++ brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx);
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++ bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo));
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++ *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1;
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++ *banksize *= SOCRAM_BANKINFO_SZBASE;
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++ return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK);
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++}
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++
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++static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
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++ u32 *srsize)
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++{
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++ u32 coreinfo;
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++ uint nb, banksize, lss;
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++ bool retent;
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++ int i;
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++
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++ *ramsize = 0;
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++ *srsize = 0;
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++
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++ if (WARN_ON(sr->pub.rev < 4))
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++ return;
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++
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++ if (!brcmf_chip_iscoreup(&sr->pub))
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++ brcmf_chip_resetcore(&sr->pub, 0, 0, 0);
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++
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++ /* Get info for determining size */
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++ coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo));
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++ nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
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++
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++ if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) {
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++ banksize = (coreinfo & SRCI_SRBSZ_MASK);
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++ lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
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++ if (lss != 0)
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++ nb--;
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++ *ramsize = nb * (1 << (banksize + SR_BSZ_BASE));
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++ if (lss != 0)
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++ *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
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++ } else {
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++ nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
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++ for (i = 0; i < nb; i++) {
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++ retent = brcmf_chip_socram_banksize(sr, i, &banksize);
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++ *ramsize += banksize;
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++ if (retent)
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++ *srsize += banksize;
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++ }
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++ }
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++
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++ /* hardcoded save&restore memory sizes */
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++ switch (sr->chip->pub.chip) {
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+ case BRCM_CC_4334_CHIP_ID:
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+- case BRCM_CC_43340_CHIP_ID:
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+- ci->pub.ramsize = 0x80000;
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++ if (sr->chip->pub.chiprev < 2)
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++ *srsize = (32 * 1024);
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+ break;
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+- case BRCM_CC_4335_CHIP_ID:
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+- ci->pub.ramsize = 0xc0000;
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+- ci->pub.rambase = 0x180000;
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+- break;
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+- case BRCM_CC_43362_CHIP_ID:
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+- ci->pub.ramsize = 0x3c000;
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++ default:
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+ break;
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++ }
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++}
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++
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++/** Return the TCM-RAM size of the ARMCR4 core. */
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++static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
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++{
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++ u32 corecap;
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++ u32 memsize = 0;
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++ u32 nab;
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++ u32 nbb;
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++ u32 totb;
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++ u32 bxinfo;
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++ u32 idx;
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++
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++ corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
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++
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++ nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
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++ nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
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++ totb = nab + nbb;
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++
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++ for (idx = 0; idx < totb; idx++) {
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++ brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
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++ bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
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++ memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
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++ }
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++
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++ return memsize;
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++}
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++
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++static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
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++{
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++ switch (ci->pub.chip) {
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+ case BRCM_CC_4345_CHIP_ID:
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+- ci->pub.ramsize = 0xc8000;
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+- ci->pub.rambase = 0x198000;
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+- break;
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++ return 0x198000;
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++ case BRCM_CC_4335_CHIP_ID:
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+ case BRCM_CC_4339_CHIP_ID:
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+ case BRCM_CC_4354_CHIP_ID:
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+ case BRCM_CC_4356_CHIP_ID:
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+ case BRCM_CC_43567_CHIP_ID:
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+ case BRCM_CC_43569_CHIP_ID:
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+ case BRCM_CC_43570_CHIP_ID:
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+- ci->pub.ramsize = 0xc0000;
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+- ci->pub.rambase = 0x180000;
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+- break;
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+ case BRCM_CC_43602_CHIP_ID:
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+- ci->pub.ramsize = 0xf0000;
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+- ci->pub.rambase = 0x180000;
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+- break;
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++ return 0x180000;
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+ default:
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+ brcmf_err("unknown chip: %s\n", ci->pub.name);
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+ break;
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+ }
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++ return 0;
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++}
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++
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++static int brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
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++{
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++ struct brcmf_core_priv *mem_core;
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++ struct brcmf_core *mem;
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++
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++ mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
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++ if (mem) {
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++ mem_core = container_of(mem, struct brcmf_core_priv, pub);
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++ ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
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++ ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
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++ if (!ci->pub.rambase) {
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++ brcmf_err("RAM base not provided with ARM CR4 core\n");
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++ return -EINVAL;
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++ }
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++ } else {
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++ mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_INTERNAL_MEM);
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++ mem_core = container_of(mem, struct brcmf_core_priv, pub);
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++ brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
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++ &ci->pub.srsize);
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++ }
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++ brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n",
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++ ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
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++ ci->pub.srsize, ci->pub.srsize);
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++
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++ if (!ci->pub.ramsize) {
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++ brcmf_err("RAM size is undetermined\n");
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++ return -ENOMEM;
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++ }
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++ return 0;
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+ }
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+
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+ static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
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+@@ -668,6 +833,7 @@ static int brcmf_chip_recognition(struct
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+ struct brcmf_core *core;
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+ u32 regdata;
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+ u32 socitype;
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++ int ret;
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+
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+ /* Get CC core rev
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+ * Chipid is assume to be at offset 0 from SI_ENUM_BASE
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+@@ -720,9 +886,13 @@ static int brcmf_chip_recognition(struct
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+ return -ENODEV;
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+ }
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+
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+- brcmf_chip_get_raminfo(ci);
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+-
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+- return brcmf_chip_cores_check(ci);
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++ ret = brcmf_chip_cores_check(ci);
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++ if (ret)
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++ return ret;
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++
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++ /* assure chip is passive for core access */
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++ brcmf_chip_set_passive(&ci->pub);
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++ return brcmf_chip_get_raminfo(ci);
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+ }
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+
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+ static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
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+@@ -827,8 +997,6 @@ struct brcmf_chip *brcmf_chip_attach(voi
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+ if (err < 0)
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+ goto fail;
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+
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+- /* assure chip is passive for download */
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+- brcmf_chip_set_passive(&chip->pub);
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+ return &chip->pub;
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+
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+ fail:
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+--- a/drivers/net/wireless/brcm80211/brcmfmac/chip.h
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++++ b/drivers/net/wireless/brcm80211/brcmfmac/chip.h
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+@@ -30,7 +30,8 @@
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+ * @pmucaps: PMU capabilities.
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+ * @pmurev: PMU revision.
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+ * @rambase: RAM base address (only applicable for ARM CR4 chips).
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+- * @ramsize: amount of RAM on chip.
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++ * @ramsize: amount of RAM on chip including retention.
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++ * @srsize: amount of retention RAM on chip.
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+ * @name: string representation of the chip identifier.
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+ */
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+ struct brcmf_chip {
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+@@ -41,6 +42,7 @@ struct brcmf_chip {
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+ u32 pmurev;
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+ u32 rambase;
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+ u32 ramsize;
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++ u32 srsize;
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+ char name[8];
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+ };
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+
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