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@@ -0,0 +1,524 @@
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+From patchwork Fri Nov 28 10:29:14 2025
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+ Fri, 28 Nov 2025 10:29:22 +0000 (UTC)
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+From: George Moussalem via B4 Relay
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+ <[email protected]>
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+Date: Fri, 28 Nov 2025 14:29:14 +0400
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+Subject: [PATCH v19 2/6] pwm: driver for qualcomm ipq6018 pwm block
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+Precedence: bulk
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+X-Mailing-List: [email protected]
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+List-Id: <linux-pwm.vger.kernel.org>
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+In-Reply-To: <[email protected]>
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+To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <[email protected]>,
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+ Rob Herring <[email protected]>, Krzysztof Kozlowski <[email protected]>,
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+ Conor Dooley <[email protected]>, Baruch Siach <[email protected]>,
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+ Bjorn Andersson <[email protected]>,
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+ Konrad Dybcio <[email protected]>
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+Cc: [email protected], [email protected],
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+ [email protected], [email protected],
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+ George Moussalem <[email protected]>,
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+ Devi Priya <[email protected]>,
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+ Baruch Siach <[email protected]>
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+X-Original-From: George Moussalem <[email protected]>
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+Reply-To: [email protected]
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+
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+From: Devi Priya <[email protected]>
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+
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+Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on
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+driver from downstream Codeaurora kernel tree. Removed support for older
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+(V1) variants because I have no access to that hardware.
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+
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+Tested on IPQ5018 and IPQ6010 based hardware.
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+
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+Co-developed-by: Baruch Siach <[email protected]>
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+Signed-off-by: Baruch Siach <[email protected]>
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+Signed-off-by: Devi Priya <[email protected]>
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+Reviewed-by: Bjorn Andersson <[email protected]>
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+Signed-off-by: George Moussalem <[email protected]>
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+---
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+v18:
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+
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+ Added hardware notes and limitations based on own findings as
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+ requested. NOTE: there's no publically available datasheet though.
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+
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+ Expanded comment on REG1_UPDATE to indicate that when this bit is set,
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+ values for div and pre-div take effect. The hardware automatically
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+ unsets it when the change is completed.
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+
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+ Added newline between MACRO definition and next comment
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+
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+ In config_div_and_duty, used mul_u64_u64_div_u64 to avoid overflow
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+
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+ Removed unncessary restriction of pwm_div to MAX_DIV - 1 after testing
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+
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+ Constrain pre_div to MAX_DIV is pre_div calculated is > MAX_DIV
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+
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+ Use of mul_u64_u64_div_u64 in .apply
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+
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+ Skip calculation of period and duty cycle when PWM_ENABLE REG is unset
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+
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+ Set duty cycle to period value when calculated duty cycle > period to
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+ return a valid config
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+
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+ Removed .npwm as it's taken care of in devm_pwmchip_alloc
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+
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+ Added call to devm_clk_rate_exclusive_get to lock the clock rate
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+
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+ Start all kernel messages with a capital letter and end with \n.
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+
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+v17:
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+
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+ Removed unnecessary code comments
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+
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+v16:
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+
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+ Simplified code to calculate divs and duty cycle as per Uwe's comments
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+
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+ Removed unused pwm_chip struct from ipq_pwm_chip struct
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+
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+ Removed unnecessary cast as per Uwe's comment
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+
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+ Replaced devm_clk_get & clk_prepare_enable by devm_clk_get_enabled
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+
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+ Replaced pwmchip_add by devm_pwmchip_add and removed .remove function
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+
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+ Removed .owner from driver struct
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+
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+v15:
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+
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+ No change
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+
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+v14:
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+
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+ Picked up the R-b tag
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+
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+v13:
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+
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+ Updated the file name to match the compatible
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+
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+ Sorted the properties and updated the order in the required field
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+
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+ Dropped the syscon node from examples
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+
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+v12:
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+
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+ Picked up the R-b tag
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+
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+v11:
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+
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+ No change
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+
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+v10:
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+
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+ No change
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+
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+v9:
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+
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+ Add 'ranges' property to example (Rob)
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+
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+ Drop label in example (Rob)
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+
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+v8:
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+
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+ Add size cell to 'reg' (Rob)
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+
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+v7:
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+
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+ Use 'reg' instead of 'offset' (Rob)
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+
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+ Drop 'clock-names' and 'assigned-clock*' (Bjorn)
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+
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+ Use single cell address/size in example node (Bjorn)
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+
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+ Move '#pwm-cells' lower in example node (Bjorn)
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+
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+ List 'reg' as required
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+
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+v6:
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+
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+ Device node is child of TCSR; remove phandle (Rob Herring)
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+
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+ Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König)
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+
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+v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn
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+ Andersson, Kathiravan T)
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+
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+v4: Update the binding example node as well (Rob Herring's bot)
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+
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+v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)
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+
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+v2: Make #pwm-cells const (Rob Herring)
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+---
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+ drivers/pwm/Kconfig | 12 +++
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+ drivers/pwm/Makefile | 1 +
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+ drivers/pwm/pwm-ipq.c | 239 ++++++++++++++++++++++++++++++++++++++++++++++++++
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+ 3 files changed, 252 insertions(+)
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+
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+diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
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+index bf2d101f67a1e0ae12a58b5630abd5cfd77ccc99..6393f4e91697ae471b1aba72e7ef3f94c5e18383 100644
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+--- a/drivers/pwm/Kconfig
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++++ b/drivers/pwm/Kconfig
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+@@ -347,6 +347,18 @@ config PWM_INTEL_LGM
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+ To compile this driver as a module, choose M here: the module
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+ will be called pwm-intel-lgm.
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+
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++config PWM_IPQ
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++ tristate "IPQ PWM support"
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++ depends on ARCH_QCOM || COMPILE_TEST
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++ depends on HAVE_CLK && HAS_IOMEM
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++ help
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++ Generic PWM framework driver for IPQ PWM block which supports
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++ 4 pwm channels. Each of the these channels can be configured
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++ independent of each other.
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++
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++ To compile this driver as a module, choose M here: the module
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++ will be called pwm-ipq.
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++
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+ config PWM_IQS620A
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+ tristate "Azoteq IQS620A PWM support"
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+ depends on MFD_IQS62X || COMPILE_TEST
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+diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
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+index 0dc0d2b69025dbd27013285cd335d3cb1ca2ab3f..5630a521a7cffeb83ff8c8960e15eb23ddb1c9f8 100644
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+--- a/drivers/pwm/Makefile
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++++ b/drivers/pwm/Makefile
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+@@ -29,6 +29,7 @@ obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
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+ obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o
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+ obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o
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+ obj-$(CONFIG_PWM_INTEL_LGM) += pwm-intel-lgm.o
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++obj-$(CONFIG_PWM_IPQ) += pwm-ipq.o
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+ obj-$(CONFIG_PWM_IQS620A) += pwm-iqs620a.o
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+ obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
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+ obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o
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+diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c
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+new file mode 100644
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+index 0000000000000000000000000000000000000000..9955b185bc60f27d770f3833d5acd7f587595324
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+--- /dev/null
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++++ b/drivers/pwm/pwm-ipq.c
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+@@ -0,0 +1,239 @@
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++// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
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++/*
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++ * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.
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++ *
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++ * Hardware notes / Limitations:
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++ * - The PWM controller has no publicly available datasheet.
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++ * - Each of the four channels is programmed via two 32-bit registers
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++ * (REG0 and REG1 at 8-byte stride).
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++ * - Period and duty-cycle reconfiguration is fully atomic: new divider,
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++ * pre-divider, and high-duration values are latched by setting the
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++ * UPDATE bit (bit 30 in REG1). The hardware applies the new settings
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++ * at the beginning of the next period without disabling the output,
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++ * so the currently running period is always completed.
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++ * - On disable (clearing the ENABLE bit 31 in REG1), the hardware
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++ * finishes the current period before stopping the output. The pin
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++ * is then driven to the inactive (low) level.
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++ * - Upon disabling, the hardware resets the pre-divider (PRE_DIV) and divider
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++ * fields (PWM_DIV) in REG0 and REG1 to 0x0000 and 0x0001 respectively.
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++ * - Only normal polarity is supported.
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++ */
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++
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++#include <linux/module.h>
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++#include <linux/platform_device.h>
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++#include <linux/pwm.h>
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++#include <linux/clk.h>
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++#include <linux/io.h>
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++#include <linux/of.h>
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++#include <linux/math64.h>
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++#include <linux/of_device.h>
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++#include <linux/bitfield.h>
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++#include <linux/units.h>
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++
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++/* The frequency range supported is 1 Hz to clock rate */
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++#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC)
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++
|
|
|
++/*
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|
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++ * The max value specified for each field is based on the number of bits
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|
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++ * in the pwm control register for that field
|
|
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++ */
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++#define IPQ_PWM_MAX_DIV 0xFFFF
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++
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|
|
++/*
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|
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++ * Two 32-bit registers for each PWM: REG0, and REG1.
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|
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++ * Base offset for PWM #i is at 8 * #i.
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|
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++ */
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++#define IPQ_PWM_REG0 0
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++#define IPQ_PWM_REG0_PWM_DIV GENMASK(15, 0)
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|
++#define IPQ_PWM_REG0_HI_DURATION GENMASK(31, 16)
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++
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++#define IPQ_PWM_REG1 4
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++#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0)
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++
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++/*
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++ * Enable bit is set to enable output toggling in pwm device.
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++ * Update bit is set to trigger the change and is unset automatically
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++ * to reflect the changed divider and high duration values in register.
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++ */
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++#define IPQ_PWM_REG1_UPDATE BIT(30)
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++#define IPQ_PWM_REG1_ENABLE BIT(31)
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++
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++struct ipq_pwm_chip {
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++ struct clk *clk;
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++ void __iomem *mem;
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|
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++};
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++
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++static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip)
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++{
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++ return pwmchip_get_drvdata(chip);
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++}
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++
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++static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned int reg)
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++{
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++ struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(pwm->chip);
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++ unsigned int off = 8 * pwm->hwpwm + reg;
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++
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++ return readl(ipq_chip->mem + off);
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++}
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++
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|
++static void ipq_pwm_reg_write(struct pwm_device *pwm, unsigned int reg,
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|
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++ unsigned int val)
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++{
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++ struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(pwm->chip);
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++ unsigned int off = 8 * pwm->hwpwm + reg;
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++
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++ writel(val, ipq_chip->mem + off);
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|
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++}
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++
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++static void config_div_and_duty(struct pwm_device *pwm, unsigned int pre_div,
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++ unsigned int pwm_div, unsigned long rate, u64 duty_ns,
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++ bool enable)
|
|
|
++{
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++ unsigned long hi_dur;
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++ unsigned long val = 0;
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++
|
|
|
++ /*
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++ * high duration = pwm duty * (pwm div + 1)
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++ * pwm duty = duty_ns / period_ns
|
|
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++ */
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++ hi_dur = mul_u64_u64_div_u64(duty_ns, rate, (pre_div + 1) * NSEC_PER_SEC);
|
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++
|
|
|
++ val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) |
|
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|
++ FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div);
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|
++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val);
|
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|
++
|
|
|
++ val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div);
|
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|
++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
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|
++
|
|
|
++ /* PWM enable toggle needs a separate write to REG1 */
|
|
|
++ val |= IPQ_PWM_REG1_UPDATE;
|
|
|
++ if (enable)
|
|
|
++ val |= IPQ_PWM_REG1_ENABLE;
|
|
|
++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
|
|
|
++}
|
|
|
++
|
|
|
++static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
|
|
++ const struct pwm_state *state)
|
|
|
++{
|
|
|
++ struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip);
|
|
|
++ unsigned long rate = clk_get_rate(ipq_chip->clk);
|
|
|
++ unsigned int pre_div, pwm_div;
|
|
|
++ u64 period_ns, duty_ns;
|
|
|
++
|
|
|
++ if (state->polarity != PWM_POLARITY_NORMAL)
|
|
|
++ return -EINVAL;
|
|
|
++
|
|
|
++ if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate))
|
|
|
++ return -ERANGE;
|
|
|
++
|
|
|
++ period_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS);
|
|
|
++ duty_ns = min(state->duty_cycle, period_ns);
|
|
|
++
|
|
|
++ pwm_div = IPQ_PWM_MAX_DIV;
|
|
|
++ pre_div = mul_u64_u64_div_u64(period_ns, rate, (u64)NSEC_PER_SEC * (pwm_div + 1));
|
|
|
++
|
|
|
++ if (pre_div > IPQ_PWM_MAX_DIV)
|
|
|
++ pre_div = IPQ_PWM_MAX_DIV;
|
|
|
++
|
|
|
++ config_div_and_duty(pwm, pre_div, pwm_div, rate, duty_ns, state->enabled);
|
|
|
++
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static int ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
|
|
|
++ struct pwm_state *state)
|
|
|
++{
|
|
|
++ struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip);
|
|
|
++ unsigned long rate = clk_get_rate(ipq_chip->clk);
|
|
|
++ unsigned int pre_div, pwm_div, hi_dur;
|
|
|
++ u64 effective_div, hi_div;
|
|
|
++ u32 reg0, reg1;
|
|
|
++
|
|
|
++ reg1 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG1);
|
|
|
++ state->enabled = reg1 & IPQ_PWM_REG1_ENABLE;
|
|
|
++
|
|
|
++ if (!state->enabled)
|
|
|
++ return 0;
|
|
|
++
|
|
|
++ reg0 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG0);
|
|
|
++
|
|
|
++ state->polarity = PWM_POLARITY_NORMAL;
|
|
|
++
|
|
|
++ pwm_div = FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0);
|
|
|
++ hi_dur = FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0);
|
|
|
++ pre_div = FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1);
|
|
|
++
|
|
|
++ /* No overflow here, both pre_div and pwm_div <= 0xffff */
|
|
|
++ effective_div = (pre_div + 1) * (pwm_div + 1);
|
|
|
++ state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, rate);
|
|
|
++
|
|
|
++ hi_div = hi_dur * (pre_div + 1);
|
|
|
++ state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate);
|
|
|
++
|
|
|
++ /*
|
|
|
++ * ensure a valid config is passed back to PWM core in case duty_cycle
|
|
|
++ * is > period (>100%)
|
|
|
++ */
|
|
|
++ state->duty_cycle = min(state->duty_cycle, state->period);
|
|
|
++
|
|
|
++ return 0;
|
|
|
++}
|
|
|
++
|
|
|
++static const struct pwm_ops ipq_pwm_ops = {
|
|
|
++ .apply = ipq_pwm_apply,
|
|
|
++ .get_state = ipq_pwm_get_state,
|
|
|
++};
|
|
|
++
|
|
|
++static int ipq_pwm_probe(struct platform_device *pdev)
|
|
|
++{
|
|
|
++ struct device *dev = &pdev->dev;
|
|
|
++ struct ipq_pwm_chip *pwm;
|
|
|
++ struct pwm_chip *chip;
|
|
|
++ int ret;
|
|
|
++
|
|
|
++ chip = devm_pwmchip_alloc(dev, 4, sizeof(*pwm));
|
|
|
++ if (IS_ERR(chip))
|
|
|
++ return PTR_ERR(chip);
|
|
|
++ pwm = ipq_pwm_from_chip(chip);
|
|
|
++
|
|
|
++ pwm->mem = devm_platform_ioremap_resource(pdev, 0);
|
|
|
++ if (IS_ERR(pwm->mem))
|
|
|
++ return dev_err_probe(dev, PTR_ERR(pwm->mem),
|
|
|
++ "Failed to acquire resource\n");
|
|
|
++
|
|
|
++ pwm->clk = devm_clk_get_enabled(dev, NULL);
|
|
|
++ if (IS_ERR(pwm->clk))
|
|
|
++ return dev_err_probe(dev, PTR_ERR(pwm->clk),
|
|
|
++ "Failed to get clock\n");
|
|
|
++
|
|
|
++ ret = devm_clk_rate_exclusive_get(dev, pwm->clk);
|
|
|
++ if (ret)
|
|
|
++ return dev_err_probe(dev, ret,
|
|
|
++ "Failed to lock clock rate\n");
|
|
|
++
|
|
|
++ chip->ops = &ipq_pwm_ops;
|
|
|
++
|
|
|
++ ret = devm_pwmchip_add(dev, chip);
|
|
|
++ if (ret < 0)
|
|
|
++ return dev_err_probe(dev, ret, "Failed to add pwm chip\n");
|
|
|
++
|
|
|
++ return ret;
|
|
|
++}
|
|
|
++
|
|
|
++static const struct of_device_id pwm_ipq_dt_match[] = {
|
|
|
++ { .compatible = "qcom,ipq6018-pwm", },
|
|
|
++ {}
|
|
|
++};
|
|
|
++MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match);
|
|
|
++
|
|
|
++static struct platform_driver ipq_pwm_driver = {
|
|
|
++ .driver = {
|
|
|
++ .name = "ipq-pwm",
|
|
|
++ .of_match_table = pwm_ipq_dt_match,
|
|
|
++ },
|
|
|
++ .probe = ipq_pwm_probe,
|
|
|
++};
|
|
|
++
|
|
|
++module_platform_driver(ipq_pwm_driver);
|
|
|
++
|
|
|
++MODULE_LICENSE("GPL");
|
Kenneth Kasilag