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+From 2961f69f151c0a6771f55cef46398fe49ca20902 Mon Sep 17 00:00:00 2001
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+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
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+Date: Thu, 12 Nov 2020 16:08:32 +0100
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+Subject: [PATCH] arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early
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+ DTS files
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+MIME-Version: 1.0
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+Content-Type: text/plain; charset=UTF-8
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+Content-Transfer-Encoding: 8bit
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+
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+They don't descibe hardware fully yet but it's enough to boot a system.
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+
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+Some missing blocks:
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+1. PMC (Power Management Controller?)
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+2. Ethernet
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+3. Crypto
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+4. Thermal
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+
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+Asus DTS is missing defining full NAND partitions layout and buttons.
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+
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+Further changes will fill those gaps as soon as required bindings will
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+be found / tested / added.
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+
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+Signed-off-by: Rafał Miłecki <[email protected]>
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+Signed-off-by: Florian Fainelli <[email protected]>
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+---
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+ arch/arm64/boot/dts/broadcom/Makefile | 1 +
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+ arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 2 +
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+ .../bcm4908/bcm4908-asus-gt-ac5300.dts | 66 +++++++
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+ .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 187 ++++++++++++++++++
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+ 4 files changed, 256 insertions(+)
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+ create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/Makefile
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+ create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
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+ create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
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+
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+--- a/arch/arm64/boot/dts/broadcom/Makefile
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++++ b/arch/arm64/boot/dts/broadcom/Makefile
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+@@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rp
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+ bcm2837-rpi-3-b-plus.dtb \
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+ bcm2837-rpi-cm3-io3.dtb
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+
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++subdir-y += bcm4908
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+ subdir-y += northstar2
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+ subdir-y += stingray
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+--- /dev/null
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++++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile
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+@@ -0,0 +1,2 @@
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++# SPDX-License-Identifier: GPL-2.0
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++dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb
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+--- /dev/null
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++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
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+@@ -0,0 +1,66 @@
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++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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++
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++#include <dt-bindings/gpio/gpio.h>
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++#include <dt-bindings/input/input.h>
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++
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++#include "bcm4908.dtsi"
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++
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++/ {
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++ compatible = "asus,gt-ac5300", "brcm,bcm4908";
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++ model = "Asus GT-AC5300";
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++
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++ memory@0 {
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++ device_type = "memory";
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++ reg = <0x00 0x00 0x00 0x40000000>;
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++ };
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++
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++ gpio-keys-polled {
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++ compatible = "gpio-keys-polled";
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++ poll-interval = <100>;
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++
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++ wifi {
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++ label = "WiFi";
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++ linux,code = <KEY_RFKILL>;
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++ gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
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++ };
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++
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++ wps {
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++ label = "WPS";
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++ linux,code = <KEY_WPS_BUTTON>;
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++ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
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++ };
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++
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++ restart {
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++ label = "Reset";
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++ linux,code = <KEY_RESTART>;
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++ gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
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++ };
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++
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++ brightness {
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++ label = "LEDs";
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++ linux,code = <KEY_BRIGHTNESS_ZERO>;
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++ gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
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++ };
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++ };
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++};
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++
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++&nandcs {
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++ nand-ecc-strength = <4>;
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++ nand-ecc-step-size = <512>;
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++ nand-on-flash-bbt;
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++ brcm,nand-has-wp;
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++
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ partitions {
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++ compatible = "fixed-partitions";
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++
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++ partition@0 {
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++ label = "cferom";
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++ reg = <0x0 0x100000>;
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++ };
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++ };
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++};
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+--- /dev/null
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++++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
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+@@ -0,0 +1,187 @@
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++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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++
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++#include <dt-bindings/interrupt-controller/irq.h>
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++#include <dt-bindings/interrupt-controller/arm-gic.h>
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++
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++/dts-v1/;
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++
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++/ {
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++ interrupt-parent = <&gic>;
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++
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++ #address-cells = <2>;
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++ #size-cells = <2>;
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++
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++ aliases {
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++ serial0 = &uart0;
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++ };
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++
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++ chosen {
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++ stdout-path = "serial0:115200n8";
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++ };
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++
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++ cpus {
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++
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++ cpu0: cpu@0 {
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++ device_type = "cpu";
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++ compatible = "brcm,brahma-b53";
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++ reg = <0x0>;
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++ next-level-cache = <&l2>;
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++ };
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++
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++ cpu1: cpu@1 {
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++ device_type = "cpu";
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++ compatible = "brcm,brahma-b53";
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++ reg = <0x1>;
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++ enable-method = "spin-table";
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++ cpu-release-addr = <0x0 0xfff8>;
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++ next-level-cache = <&l2>;
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++ };
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++
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++ cpu2: cpu@2 {
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++ device_type = "cpu";
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++ compatible = "brcm,brahma-b53";
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++ reg = <0x2>;
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++ enable-method = "spin-table";
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++ cpu-release-addr = <0x0 0xfff8>;
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++ next-level-cache = <&l2>;
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++ };
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++
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++ cpu3: cpu@3 {
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++ device_type = "cpu";
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++ compatible = "brcm,brahma-b53";
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++ reg = <0x3>;
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++ enable-method = "spin-table";
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++ cpu-release-addr = <0x0 0xfff8>;
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++ next-level-cache = <&l2>;
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++ };
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++
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++ l2: l2-cache0 {
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++ compatible = "cache";
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++ };
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++ };
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++
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++ axi@81000000 {
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++ compatible = "simple-bus";
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++ ranges = <0x00 0x00 0x81000000 0x4000>;
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++
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++ gic: interrupt-controller@1000 {
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++ compatible = "arm,gic-400";
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++ #interrupt-cells = <3>;
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++ #address-cells = <0>;
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++ interrupt-controller;
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++ reg = <0x1000 0x1000>,
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++ <0x2000 0x2000>;
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++ };
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++ };
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++
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++ timer {
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++ compatible = "arm,armv8-timer";
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++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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++ };
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++
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++ pmu {
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++ compatible = "arm,cortex-a53-pmu";
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++ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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++ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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++ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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++ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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++ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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++ };
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++
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++ clocks {
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++ periph_clk: periph_clk {
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++ compatible = "fixed-clock";
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++ #clock-cells = <0>;
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++ clock-frequency = <50000000>;
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++ clock-output-names = "periph";
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++ };
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++ };
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++
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++ soc {
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++ compatible = "simple-bus";
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++ ranges = <0x00 0x00 0x80000000 0x10000>;
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++
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++ usb@c300 {
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++ compatible = "generic-ehci";
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++ reg = <0xc300 0x100>;
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++ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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++ status = "disabled";
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++ };
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++
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++ usb@c400 {
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++ compatible = "generic-ohci";
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++ reg = <0xc400 0x100>;
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++ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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++ status = "disabled";
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++ };
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++
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++ usb@d000 {
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++ compatible = "generic-xhci";
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++ reg = <0xd000 0x8c8>;
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++ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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++ status = "disabled";
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++ };
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++ };
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++
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++ bus@ff800000 {
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++ compatible = "simple-bus";
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++ #address-cells = <1>;
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++ #size-cells = <1>;
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++ ranges = <0x00 0x00 0xff800000 0x3000>;
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++
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++ timer: timer@400 {
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++ compatible = "brcm,bcm6328-timer", "syscon";
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++ reg = <0x400 0x3c>;
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++ };
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++
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++ gpio0: gpio-controller@500 {
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++ compatible = "brcm,bcm6345-gpio";
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++ reg-names = "dirout", "dat";
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++ reg = <0x500 0x28>, <0x528 0x28>;
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++
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++ #gpio-cells = <2>;
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++ gpio-controller;
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++ };
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++
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++ uart0: serial@640 {
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++ compatible = "brcm,bcm6345-uart";
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++ reg = <0x640 0x18>;
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++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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++ clocks = <&periph_clk>;
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++ clock-names = "periph";
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++ status = "okay";
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++ };
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++
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++ nand@1800 {
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++ #address-cells = <1>;
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++ #size-cells = <0>;
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++ compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
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++ reg = <0x1800 0x600>, <0x2000 0x10>;
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++ reg-names = "nand", "nand-int-base";
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++ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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++ interrupt-names = "nand";
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++ status = "okay";
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++
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++ nandcs: nandcs@0 {
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++ compatible = "brcm,nandcs";
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++ reg = <0>;
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++ };
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++ };
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++
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++ reboot {
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++ compatible = "syscon-reboot";
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++ regmap = <&timer>;
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++ offset = <0x34>;
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++ mask = <1>;
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++ };
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++ };
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++};
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Rafał Miłecki